1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/dma-mapping.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/serial_8250.h>
15#include <linux/platform_device.h>
16#include <linux/platform_data/edma.h>
17#include <linux/platform_data/gpio-davinci.h>
18
19#include <asm/mach/map.h>
20
21#include <mach/cputype.h>
22#include <mach/irqs.h>
23#include <mach/psc.h>
24#include <mach/mux.h>
25#include <mach/time.h>
26#include <mach/serial.h>
27#include <mach/common.h>
28
29#include "davinci.h"
30#include "clock.h"
31#include "mux.h"
32#include "asp.h"
33
34#define DAVINCI_VPIF_BASE       (0x01C12000)
35
36#define VDD3P3V_VID_MASK	(BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
37					BIT_MASK(0))
38#define VSCLKDIS_MASK		(BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
39					BIT_MASK(8))
40
41/*
42 * Device specific clocks
43 */
44#define DM646X_REF_FREQ		27000000
45#define DM646X_AUX_FREQ		24000000
46
47#define DM646X_EMAC_BASE		0x01c80000
48#define DM646X_EMAC_MDIO_BASE		(DM646X_EMAC_BASE + 0x4000)
49#define DM646X_EMAC_CNTRL_OFFSET	0x0000
50#define DM646X_EMAC_CNTRL_MOD_OFFSET	0x1000
51#define DM646X_EMAC_CNTRL_RAM_OFFSET	0x2000
52#define DM646X_EMAC_CNTRL_RAM_SIZE	0x2000
53
54static struct pll_data pll1_data = {
55	.num       = 1,
56	.phys_base = DAVINCI_PLL1_BASE,
57};
58
59static struct pll_data pll2_data = {
60	.num       = 2,
61	.phys_base = DAVINCI_PLL2_BASE,
62};
63
64static struct clk ref_clk = {
65	.name = "ref_clk",
66	.rate = DM646X_REF_FREQ,
67	.set_rate = davinci_simple_set_rate,
68};
69
70static struct clk aux_clkin = {
71	.name = "aux_clkin",
72	.rate = DM646X_AUX_FREQ,
73};
74
75static struct clk pll1_clk = {
76	.name = "pll1",
77	.parent = &ref_clk,
78	.pll_data = &pll1_data,
79	.flags = CLK_PLL,
80};
81
82static struct clk pll1_sysclk1 = {
83	.name = "pll1_sysclk1",
84	.parent = &pll1_clk,
85	.flags = CLK_PLL,
86	.div_reg = PLLDIV1,
87};
88
89static struct clk pll1_sysclk2 = {
90	.name = "pll1_sysclk2",
91	.parent = &pll1_clk,
92	.flags = CLK_PLL,
93	.div_reg = PLLDIV2,
94};
95
96static struct clk pll1_sysclk3 = {
97	.name = "pll1_sysclk3",
98	.parent = &pll1_clk,
99	.flags = CLK_PLL,
100	.div_reg = PLLDIV3,
101};
102
103static struct clk pll1_sysclk4 = {
104	.name = "pll1_sysclk4",
105	.parent = &pll1_clk,
106	.flags = CLK_PLL,
107	.div_reg = PLLDIV4,
108};
109
110static struct clk pll1_sysclk5 = {
111	.name = "pll1_sysclk5",
112	.parent = &pll1_clk,
113	.flags = CLK_PLL,
114	.div_reg = PLLDIV5,
115};
116
117static struct clk pll1_sysclk6 = {
118	.name = "pll1_sysclk6",
119	.parent = &pll1_clk,
120	.flags = CLK_PLL,
121	.div_reg = PLLDIV6,
122};
123
124static struct clk pll1_sysclk8 = {
125	.name = "pll1_sysclk8",
126	.parent = &pll1_clk,
127	.flags = CLK_PLL,
128	.div_reg = PLLDIV8,
129};
130
131static struct clk pll1_sysclk9 = {
132	.name = "pll1_sysclk9",
133	.parent = &pll1_clk,
134	.flags = CLK_PLL,
135	.div_reg = PLLDIV9,
136};
137
138static struct clk pll1_sysclkbp = {
139	.name = "pll1_sysclkbp",
140	.parent = &pll1_clk,
141	.flags = CLK_PLL | PRE_PLL,
142	.div_reg = BPDIV,
143};
144
145static struct clk pll1_aux_clk = {
146	.name = "pll1_aux_clk",
147	.parent = &pll1_clk,
148	.flags = CLK_PLL | PRE_PLL,
149};
150
151static struct clk pll2_clk = {
152	.name = "pll2_clk",
153	.parent = &ref_clk,
154	.pll_data = &pll2_data,
155	.flags = CLK_PLL,
156};
157
158static struct clk pll2_sysclk1 = {
159	.name = "pll2_sysclk1",
160	.parent = &pll2_clk,
161	.flags = CLK_PLL,
162	.div_reg = PLLDIV1,
163};
164
165static struct clk dsp_clk = {
166	.name = "dsp",
167	.parent = &pll1_sysclk1,
168	.lpsc = DM646X_LPSC_C64X_CPU,
169	.usecount = 1,			/* REVISIT how to disable? */
170};
171
172static struct clk arm_clk = {
173	.name = "arm",
174	.parent = &pll1_sysclk2,
175	.lpsc = DM646X_LPSC_ARM,
176	.flags = ALWAYS_ENABLED,
177};
178
179static struct clk edma_cc_clk = {
180	.name = "edma_cc",
181	.parent = &pll1_sysclk2,
182	.lpsc = DM646X_LPSC_TPCC,
183	.flags = ALWAYS_ENABLED,
184};
185
186static struct clk edma_tc0_clk = {
187	.name = "edma_tc0",
188	.parent = &pll1_sysclk2,
189	.lpsc = DM646X_LPSC_TPTC0,
190	.flags = ALWAYS_ENABLED,
191};
192
193static struct clk edma_tc1_clk = {
194	.name = "edma_tc1",
195	.parent = &pll1_sysclk2,
196	.lpsc = DM646X_LPSC_TPTC1,
197	.flags = ALWAYS_ENABLED,
198};
199
200static struct clk edma_tc2_clk = {
201	.name = "edma_tc2",
202	.parent = &pll1_sysclk2,
203	.lpsc = DM646X_LPSC_TPTC2,
204	.flags = ALWAYS_ENABLED,
205};
206
207static struct clk edma_tc3_clk = {
208	.name = "edma_tc3",
209	.parent = &pll1_sysclk2,
210	.lpsc = DM646X_LPSC_TPTC3,
211	.flags = ALWAYS_ENABLED,
212};
213
214static struct clk uart0_clk = {
215	.name = "uart0",
216	.parent = &aux_clkin,
217	.lpsc = DM646X_LPSC_UART0,
218};
219
220static struct clk uart1_clk = {
221	.name = "uart1",
222	.parent = &aux_clkin,
223	.lpsc = DM646X_LPSC_UART1,
224};
225
226static struct clk uart2_clk = {
227	.name = "uart2",
228	.parent = &aux_clkin,
229	.lpsc = DM646X_LPSC_UART2,
230};
231
232static struct clk i2c_clk = {
233	.name = "I2CCLK",
234	.parent = &pll1_sysclk3,
235	.lpsc = DM646X_LPSC_I2C,
236};
237
238static struct clk gpio_clk = {
239	.name = "gpio",
240	.parent = &pll1_sysclk3,
241	.lpsc = DM646X_LPSC_GPIO,
242};
243
244static struct clk mcasp0_clk = {
245	.name = "mcasp0",
246	.parent = &pll1_sysclk3,
247	.lpsc = DM646X_LPSC_McASP0,
248};
249
250static struct clk mcasp1_clk = {
251	.name = "mcasp1",
252	.parent = &pll1_sysclk3,
253	.lpsc = DM646X_LPSC_McASP1,
254};
255
256static struct clk aemif_clk = {
257	.name = "aemif",
258	.parent = &pll1_sysclk3,
259	.lpsc = DM646X_LPSC_AEMIF,
260	.flags = ALWAYS_ENABLED,
261};
262
263static struct clk emac_clk = {
264	.name = "emac",
265	.parent = &pll1_sysclk3,
266	.lpsc = DM646X_LPSC_EMAC,
267};
268
269static struct clk pwm0_clk = {
270	.name = "pwm0",
271	.parent = &pll1_sysclk3,
272	.lpsc = DM646X_LPSC_PWM0,
273	.usecount = 1,            /* REVIST: disabling hangs system */
274};
275
276static struct clk pwm1_clk = {
277	.name = "pwm1",
278	.parent = &pll1_sysclk3,
279	.lpsc = DM646X_LPSC_PWM1,
280	.usecount = 1,            /* REVIST: disabling hangs system */
281};
282
283static struct clk timer0_clk = {
284	.name = "timer0",
285	.parent = &pll1_sysclk3,
286	.lpsc = DM646X_LPSC_TIMER0,
287};
288
289static struct clk timer1_clk = {
290	.name = "timer1",
291	.parent = &pll1_sysclk3,
292	.lpsc = DM646X_LPSC_TIMER1,
293};
294
295static struct clk timer2_clk = {
296	.name = "timer2",
297	.parent = &pll1_sysclk3,
298	.flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
299};
300
301
302static struct clk ide_clk = {
303	.name = "ide",
304	.parent = &pll1_sysclk4,
305	.lpsc = DAVINCI_LPSC_ATA,
306};
307
308static struct clk vpif0_clk = {
309	.name = "vpif0",
310	.parent = &ref_clk,
311	.lpsc = DM646X_LPSC_VPSSMSTR,
312	.flags = ALWAYS_ENABLED,
313};
314
315static struct clk vpif1_clk = {
316	.name = "vpif1",
317	.parent = &ref_clk,
318	.lpsc = DM646X_LPSC_VPSSSLV,
319	.flags = ALWAYS_ENABLED,
320};
321
322static struct clk_lookup dm646x_clks[] = {
323	CLK(NULL, "ref", &ref_clk),
324	CLK(NULL, "aux", &aux_clkin),
325	CLK(NULL, "pll1", &pll1_clk),
326	CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
327	CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
328	CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
329	CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
330	CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
331	CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
332	CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
333	CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
334	CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
335	CLK(NULL, "pll1_aux", &pll1_aux_clk),
336	CLK(NULL, "pll2", &pll2_clk),
337	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
338	CLK(NULL, "dsp", &dsp_clk),
339	CLK(NULL, "arm", &arm_clk),
340	CLK(NULL, "edma_cc", &edma_cc_clk),
341	CLK(NULL, "edma_tc0", &edma_tc0_clk),
342	CLK(NULL, "edma_tc1", &edma_tc1_clk),
343	CLK(NULL, "edma_tc2", &edma_tc2_clk),
344	CLK(NULL, "edma_tc3", &edma_tc3_clk),
345	CLK("serial8250.0", NULL, &uart0_clk),
346	CLK("serial8250.1", NULL, &uart1_clk),
347	CLK("serial8250.2", NULL, &uart2_clk),
348	CLK("i2c_davinci.1", NULL, &i2c_clk),
349	CLK(NULL, "gpio", &gpio_clk),
350	CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
351	CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
352	CLK(NULL, "aemif", &aemif_clk),
353	CLK("davinci_emac.1", NULL, &emac_clk),
354	CLK("davinci_mdio.0", "fck", &emac_clk),
355	CLK(NULL, "pwm0", &pwm0_clk),
356	CLK(NULL, "pwm1", &pwm1_clk),
357	CLK(NULL, "timer0", &timer0_clk),
358	CLK(NULL, "timer1", &timer1_clk),
359	CLK("davinci-wdt", NULL, &timer2_clk),
360	CLK("palm_bk3710", NULL, &ide_clk),
361	CLK(NULL, "vpif0", &vpif0_clk),
362	CLK(NULL, "vpif1", &vpif1_clk),
363	CLK(NULL, NULL, NULL),
364};
365
366static struct emac_platform_data dm646x_emac_pdata = {
367	.ctrl_reg_offset	= DM646X_EMAC_CNTRL_OFFSET,
368	.ctrl_mod_reg_offset	= DM646X_EMAC_CNTRL_MOD_OFFSET,
369	.ctrl_ram_offset	= DM646X_EMAC_CNTRL_RAM_OFFSET,
370	.ctrl_ram_size		= DM646X_EMAC_CNTRL_RAM_SIZE,
371	.version		= EMAC_VERSION_2,
372};
373
374static struct resource dm646x_emac_resources[] = {
375	{
376		.start	= DM646X_EMAC_BASE,
377		.end	= DM646X_EMAC_BASE + SZ_16K - 1,
378		.flags	= IORESOURCE_MEM,
379	},
380	{
381		.start	= IRQ_DM646X_EMACRXTHINT,
382		.end	= IRQ_DM646X_EMACRXTHINT,
383		.flags	= IORESOURCE_IRQ,
384	},
385	{
386		.start	= IRQ_DM646X_EMACRXINT,
387		.end	= IRQ_DM646X_EMACRXINT,
388		.flags	= IORESOURCE_IRQ,
389	},
390	{
391		.start	= IRQ_DM646X_EMACTXINT,
392		.end	= IRQ_DM646X_EMACTXINT,
393		.flags	= IORESOURCE_IRQ,
394	},
395	{
396		.start	= IRQ_DM646X_EMACMISCINT,
397		.end	= IRQ_DM646X_EMACMISCINT,
398		.flags	= IORESOURCE_IRQ,
399	},
400};
401
402static struct platform_device dm646x_emac_device = {
403	.name		= "davinci_emac",
404	.id		= 1,
405	.dev = {
406		.platform_data	= &dm646x_emac_pdata,
407	},
408	.num_resources	= ARRAY_SIZE(dm646x_emac_resources),
409	.resource	= dm646x_emac_resources,
410};
411
412static struct resource dm646x_mdio_resources[] = {
413	{
414		.start	= DM646X_EMAC_MDIO_BASE,
415		.end	= DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
416		.flags	= IORESOURCE_MEM,
417	},
418};
419
420static struct platform_device dm646x_mdio_device = {
421	.name		= "davinci_mdio",
422	.id		= 0,
423	.num_resources	= ARRAY_SIZE(dm646x_mdio_resources),
424	.resource	= dm646x_mdio_resources,
425};
426
427/*
428 * Device specific mux setup
429 *
430 *	soc	description	mux  mode   mode  mux	 dbg
431 *				reg  offset mask  mode
432 */
433static const struct mux_config dm646x_pins[] = {
434#ifdef CONFIG_DAVINCI_MUX
435MUX_CFG(DM646X, ATAEN,		0,   0,     5,	  1,	 true)
436
437MUX_CFG(DM646X, AUDCK1,		0,   29,    1,	  0,	 false)
438
439MUX_CFG(DM646X, AUDCK0,		0,   28,    1,	  0,	 false)
440
441MUX_CFG(DM646X, CRGMUX,			0,   24,    7,    5,	 true)
442
443MUX_CFG(DM646X, STSOMUX_DISABLE,	0,   22,    3,    0,	 true)
444
445MUX_CFG(DM646X, STSIMUX_DISABLE,	0,   20,    3,    0,	 true)
446
447MUX_CFG(DM646X, PTSOMUX_DISABLE,	0,   18,    3,    0,	 true)
448
449MUX_CFG(DM646X, PTSIMUX_DISABLE,	0,   16,    3,    0,	 true)
450
451MUX_CFG(DM646X, STSOMUX,		0,   22,    3,    2,	 true)
452
453MUX_CFG(DM646X, STSIMUX,		0,   20,    3,    2,	 true)
454
455MUX_CFG(DM646X, PTSOMUX_PARALLEL,	0,   18,    3,    2,	 true)
456
457MUX_CFG(DM646X, PTSIMUX_PARALLEL,	0,   16,    3,    2,	 true)
458
459MUX_CFG(DM646X, PTSOMUX_SERIAL,		0,   18,    3,    3,	 true)
460
461MUX_CFG(DM646X, PTSIMUX_SERIAL,		0,   16,    3,    3,	 true)
462#endif
463};
464
465static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
466	[IRQ_DM646X_VP_VERTINT0]        = 7,
467	[IRQ_DM646X_VP_VERTINT1]        = 7,
468	[IRQ_DM646X_VP_VERTINT2]        = 7,
469	[IRQ_DM646X_VP_VERTINT3]        = 7,
470	[IRQ_DM646X_VP_ERRINT]          = 7,
471	[IRQ_DM646X_RESERVED_1]         = 7,
472	[IRQ_DM646X_RESERVED_2]         = 7,
473	[IRQ_DM646X_WDINT]              = 7,
474	[IRQ_DM646X_CRGENINT0]          = 7,
475	[IRQ_DM646X_CRGENINT1]          = 7,
476	[IRQ_DM646X_TSIFINT0]           = 7,
477	[IRQ_DM646X_TSIFINT1]           = 7,
478	[IRQ_DM646X_VDCEINT]            = 7,
479	[IRQ_DM646X_USBINT]             = 7,
480	[IRQ_DM646X_USBDMAINT]          = 7,
481	[IRQ_DM646X_PCIINT]             = 7,
482	[IRQ_CCINT0]                    = 7,    /* dma */
483	[IRQ_CCERRINT]                  = 7,    /* dma */
484	[IRQ_TCERRINT0]                 = 7,    /* dma */
485	[IRQ_TCERRINT]                  = 7,    /* dma */
486	[IRQ_DM646X_TCERRINT2]          = 7,
487	[IRQ_DM646X_TCERRINT3]          = 7,
488	[IRQ_DM646X_IDE]                = 7,
489	[IRQ_DM646X_HPIINT]             = 7,
490	[IRQ_DM646X_EMACRXTHINT]        = 7,
491	[IRQ_DM646X_EMACRXINT]          = 7,
492	[IRQ_DM646X_EMACTXINT]          = 7,
493	[IRQ_DM646X_EMACMISCINT]        = 7,
494	[IRQ_DM646X_MCASP0TXINT]        = 7,
495	[IRQ_DM646X_MCASP0RXINT]        = 7,
496	[IRQ_DM646X_RESERVED_3]         = 7,
497	[IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
498	[IRQ_TINT0_TINT34]              = 7,    /* clocksource */
499	[IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
500	[IRQ_TINT1_TINT34]              = 7,    /* system tick */
501	[IRQ_PWMINT0]                   = 7,
502	[IRQ_PWMINT1]                   = 7,
503	[IRQ_DM646X_VLQINT]             = 7,
504	[IRQ_I2C]                       = 7,
505	[IRQ_UARTINT0]                  = 7,
506	[IRQ_UARTINT1]                  = 7,
507	[IRQ_DM646X_UARTINT2]           = 7,
508	[IRQ_DM646X_SPINT0]             = 7,
509	[IRQ_DM646X_SPINT1]             = 7,
510	[IRQ_DM646X_DSP2ARMINT]         = 7,
511	[IRQ_DM646X_RESERVED_4]         = 7,
512	[IRQ_DM646X_PSCINT]             = 7,
513	[IRQ_DM646X_GPIO0]              = 7,
514	[IRQ_DM646X_GPIO1]              = 7,
515	[IRQ_DM646X_GPIO2]              = 7,
516	[IRQ_DM646X_GPIO3]              = 7,
517	[IRQ_DM646X_GPIO4]              = 7,
518	[IRQ_DM646X_GPIO5]              = 7,
519	[IRQ_DM646X_GPIO6]              = 7,
520	[IRQ_DM646X_GPIO7]              = 7,
521	[IRQ_DM646X_GPIOBNK0]           = 7,
522	[IRQ_DM646X_GPIOBNK1]           = 7,
523	[IRQ_DM646X_GPIOBNK2]           = 7,
524	[IRQ_DM646X_DDRINT]             = 7,
525	[IRQ_DM646X_AEMIFINT]           = 7,
526	[IRQ_COMMTX]                    = 7,
527	[IRQ_COMMRX]                    = 7,
528	[IRQ_EMUINT]                    = 7,
529};
530
531/*----------------------------------------------------------------------*/
532
533/* Four Transfer Controllers on DM646x */
534static s8
535dm646x_queue_priority_mapping[][2] = {
536	/* {event queue no, Priority} */
537	{0, 4},
538	{1, 0},
539	{2, 5},
540	{3, 1},
541	{-1, -1},
542};
543
544static struct edma_soc_info edma_cc0_info = {
545	.queue_priority_mapping	= dm646x_queue_priority_mapping,
546	.default_queue		= EVENTQ_1,
547};
548
549static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
550	&edma_cc0_info,
551};
552
553static struct resource edma_resources[] = {
554	{
555		.name	= "edma_cc0",
556		.start	= 0x01c00000,
557		.end	= 0x01c00000 + SZ_64K - 1,
558		.flags	= IORESOURCE_MEM,
559	},
560	{
561		.name	= "edma_tc0",
562		.start	= 0x01c10000,
563		.end	= 0x01c10000 + SZ_1K - 1,
564		.flags	= IORESOURCE_MEM,
565	},
566	{
567		.name	= "edma_tc1",
568		.start	= 0x01c10400,
569		.end	= 0x01c10400 + SZ_1K - 1,
570		.flags	= IORESOURCE_MEM,
571	},
572	{
573		.name	= "edma_tc2",
574		.start	= 0x01c10800,
575		.end	= 0x01c10800 + SZ_1K - 1,
576		.flags	= IORESOURCE_MEM,
577	},
578	{
579		.name	= "edma_tc3",
580		.start	= 0x01c10c00,
581		.end	= 0x01c10c00 + SZ_1K - 1,
582		.flags	= IORESOURCE_MEM,
583	},
584	{
585		.name	= "edma0",
586		.start	= IRQ_CCINT0,
587		.flags	= IORESOURCE_IRQ,
588	},
589	{
590		.name	= "edma0_err",
591		.start	= IRQ_CCERRINT,
592		.flags	= IORESOURCE_IRQ,
593	},
594	/* not using TC*_ERR */
595};
596
597static struct platform_device dm646x_edma_device = {
598	.name			= "edma",
599	.id			= 0,
600	.dev.platform_data	= dm646x_edma_info,
601	.num_resources		= ARRAY_SIZE(edma_resources),
602	.resource		= edma_resources,
603};
604
605static struct resource dm646x_mcasp0_resources[] = {
606	{
607		.name	= "mpu",
608		.start 	= DAVINCI_DM646X_MCASP0_REG_BASE,
609		.end 	= DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
610		.flags 	= IORESOURCE_MEM,
611	},
612	{
613		.name	= "tx",
614		.start	= DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
615		.end	= DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
616		.flags	= IORESOURCE_DMA,
617	},
618	{
619		.name	= "rx",
620		.start	= DAVINCI_DM646X_DMA_MCASP0_AREVT0,
621		.end	= DAVINCI_DM646X_DMA_MCASP0_AREVT0,
622		.flags	= IORESOURCE_DMA,
623	},
624	{
625		.name	= "tx",
626		.start	= IRQ_DM646X_MCASP0TXINT,
627		.flags	= IORESOURCE_IRQ,
628	},
629	{
630		.name	= "rx",
631		.start	= IRQ_DM646X_MCASP0RXINT,
632		.flags	= IORESOURCE_IRQ,
633	},
634};
635
636/* DIT mode only, rx is not supported */
637static struct resource dm646x_mcasp1_resources[] = {
638	{
639		.name	= "mpu",
640		.start	= DAVINCI_DM646X_MCASP1_REG_BASE,
641		.end	= DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
642		.flags	= IORESOURCE_MEM,
643	},
644	{
645		.name	= "tx",
646		.start	= DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
647		.end	= DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
648		.flags	= IORESOURCE_DMA,
649	},
650	{
651		.name	= "tx",
652		.start	= IRQ_DM646X_MCASP1TXINT,
653		.flags	= IORESOURCE_IRQ,
654	},
655};
656
657static struct platform_device dm646x_mcasp0_device = {
658	.name		= "davinci-mcasp",
659	.id		= 0,
660	.num_resources	= ARRAY_SIZE(dm646x_mcasp0_resources),
661	.resource	= dm646x_mcasp0_resources,
662};
663
664static struct platform_device dm646x_mcasp1_device = {
665	.name		= "davinci-mcasp",
666	.id		= 1,
667	.num_resources	= ARRAY_SIZE(dm646x_mcasp1_resources),
668	.resource	= dm646x_mcasp1_resources,
669};
670
671static struct platform_device dm646x_dit_device = {
672	.name	= "spdif-dit",
673	.id	= -1,
674};
675
676static u64 vpif_dma_mask = DMA_BIT_MASK(32);
677
678static struct resource vpif_resource[] = {
679	{
680		.start	= DAVINCI_VPIF_BASE,
681		.end	= DAVINCI_VPIF_BASE + 0x03ff,
682		.flags	= IORESOURCE_MEM,
683	}
684};
685
686static struct platform_device vpif_dev = {
687	.name		= "vpif",
688	.id		= -1,
689	.dev		= {
690			.dma_mask 		= &vpif_dma_mask,
691			.coherent_dma_mask	= DMA_BIT_MASK(32),
692	},
693	.resource	= vpif_resource,
694	.num_resources	= ARRAY_SIZE(vpif_resource),
695};
696
697static struct resource vpif_display_resource[] = {
698	{
699		.start = IRQ_DM646X_VP_VERTINT2,
700		.end   = IRQ_DM646X_VP_VERTINT2,
701		.flags = IORESOURCE_IRQ,
702	},
703	{
704		.start = IRQ_DM646X_VP_VERTINT3,
705		.end   = IRQ_DM646X_VP_VERTINT3,
706		.flags = IORESOURCE_IRQ,
707	},
708};
709
710static struct platform_device vpif_display_dev = {
711	.name		= "vpif_display",
712	.id		= -1,
713	.dev		= {
714			.dma_mask 		= &vpif_dma_mask,
715			.coherent_dma_mask	= DMA_BIT_MASK(32),
716	},
717	.resource	= vpif_display_resource,
718	.num_resources	= ARRAY_SIZE(vpif_display_resource),
719};
720
721static struct resource vpif_capture_resource[] = {
722	{
723		.start = IRQ_DM646X_VP_VERTINT0,
724		.end   = IRQ_DM646X_VP_VERTINT0,
725		.flags = IORESOURCE_IRQ,
726	},
727	{
728		.start = IRQ_DM646X_VP_VERTINT1,
729		.end   = IRQ_DM646X_VP_VERTINT1,
730		.flags = IORESOURCE_IRQ,
731	},
732};
733
734static struct platform_device vpif_capture_dev = {
735	.name		= "vpif_capture",
736	.id		= -1,
737	.dev		= {
738			.dma_mask 		= &vpif_dma_mask,
739			.coherent_dma_mask	= DMA_BIT_MASK(32),
740	},
741	.resource	= vpif_capture_resource,
742	.num_resources	= ARRAY_SIZE(vpif_capture_resource),
743};
744
745static struct resource dm646x_gpio_resources[] = {
746	{	/* registers */
747		.start	= DAVINCI_GPIO_BASE,
748		.end	= DAVINCI_GPIO_BASE + SZ_4K - 1,
749		.flags	= IORESOURCE_MEM,
750	},
751	{	/* interrupt */
752		.start	= IRQ_DM646X_GPIOBNK0,
753		.end	= IRQ_DM646X_GPIOBNK2,
754		.flags	= IORESOURCE_IRQ,
755	},
756};
757
758static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
759	.ngpio		= 43,
760};
761
762int __init dm646x_gpio_register(void)
763{
764	return davinci_gpio_register(dm646x_gpio_resources,
765				     ARRAY_SIZE(dm646x_gpio_resources),
766				     &dm646x_gpio_platform_data);
767}
768/*----------------------------------------------------------------------*/
769
770static struct map_desc dm646x_io_desc[] = {
771	{
772		.virtual	= IO_VIRT,
773		.pfn		= __phys_to_pfn(IO_PHYS),
774		.length		= IO_SIZE,
775		.type		= MT_DEVICE
776	},
777};
778
779/* Contents of JTAG ID register used to identify exact cpu type */
780static struct davinci_id dm646x_ids[] = {
781	{
782		.variant	= 0x0,
783		.part_no	= 0xb770,
784		.manufacturer	= 0x017,
785		.cpu_id		= DAVINCI_CPU_ID_DM6467,
786		.name		= "dm6467_rev1.x",
787	},
788	{
789		.variant	= 0x1,
790		.part_no	= 0xb770,
791		.manufacturer	= 0x017,
792		.cpu_id		= DAVINCI_CPU_ID_DM6467,
793		.name		= "dm6467_rev3.x",
794	},
795};
796
797static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
798
799/*
800 * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
801 * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
802 * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
803 * T1_TOP: Timer 1, top   :  <unused>
804 */
805static struct davinci_timer_info dm646x_timer_info = {
806	.timers		= davinci_timer_instance,
807	.clockevent_id	= T0_BOT,
808	.clocksource_id	= T0_TOP,
809};
810
811static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
812	{
813		.mapbase	= DAVINCI_UART0_BASE,
814		.irq		= IRQ_UARTINT0,
815		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
816				  UPF_IOREMAP,
817		.iotype		= UPIO_MEM32,
818		.regshift	= 2,
819	},
820	{
821		.flags	= 0,
822	}
823};
824static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
825	{
826		.mapbase	= DAVINCI_UART1_BASE,
827		.irq		= IRQ_UARTINT1,
828		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
829				  UPF_IOREMAP,
830		.iotype		= UPIO_MEM32,
831		.regshift	= 2,
832	},
833	{
834		.flags	= 0,
835	}
836};
837static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
838	{
839		.mapbase	= DAVINCI_UART2_BASE,
840		.irq		= IRQ_DM646X_UARTINT2,
841		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
842				  UPF_IOREMAP,
843		.iotype		= UPIO_MEM32,
844		.regshift	= 2,
845	},
846	{
847		.flags	= 0,
848	}
849};
850
851struct platform_device dm646x_serial_device[] = {
852	{
853		.name			= "serial8250",
854		.id			= PLAT8250_DEV_PLATFORM,
855		.dev			= {
856			.platform_data	= dm646x_serial0_platform_data,
857		}
858	},
859	{
860		.name			= "serial8250",
861		.id			= PLAT8250_DEV_PLATFORM1,
862		.dev			= {
863			.platform_data	= dm646x_serial1_platform_data,
864		}
865	},
866	{
867		.name			= "serial8250",
868		.id			= PLAT8250_DEV_PLATFORM2,
869		.dev			= {
870			.platform_data	= dm646x_serial2_platform_data,
871		}
872	},
873	{
874	}
875};
876
877static struct davinci_soc_info davinci_soc_info_dm646x = {
878	.io_desc		= dm646x_io_desc,
879	.io_desc_num		= ARRAY_SIZE(dm646x_io_desc),
880	.jtag_id_reg		= 0x01c40028,
881	.ids			= dm646x_ids,
882	.ids_num		= ARRAY_SIZE(dm646x_ids),
883	.cpu_clks		= dm646x_clks,
884	.psc_bases		= dm646x_psc_bases,
885	.psc_bases_num		= ARRAY_SIZE(dm646x_psc_bases),
886	.pinmux_base		= DAVINCI_SYSTEM_MODULE_BASE,
887	.pinmux_pins		= dm646x_pins,
888	.pinmux_pins_num	= ARRAY_SIZE(dm646x_pins),
889	.intc_base		= DAVINCI_ARM_INTC_BASE,
890	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
891	.intc_irq_prios		= dm646x_default_priorities,
892	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
893	.timer_info		= &dm646x_timer_info,
894	.emac_pdata		= &dm646x_emac_pdata,
895	.sram_dma		= 0x10010000,
896	.sram_len		= SZ_32K,
897};
898
899void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
900{
901	dm646x_mcasp0_device.dev.platform_data = pdata;
902	platform_device_register(&dm646x_mcasp0_device);
903}
904
905void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
906{
907	dm646x_mcasp1_device.dev.platform_data = pdata;
908	platform_device_register(&dm646x_mcasp1_device);
909	platform_device_register(&dm646x_dit_device);
910}
911
912void dm646x_setup_vpif(struct vpif_display_config *display_config,
913		       struct vpif_capture_config *capture_config)
914{
915	unsigned int value;
916
917	value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
918	value &= ~VSCLKDIS_MASK;
919	__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
920
921	value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
922	value &= ~VDD3P3V_VID_MASK;
923	__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
924
925	davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
926	davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
927	davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
928	davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
929
930	vpif_display_dev.dev.platform_data = display_config;
931	vpif_capture_dev.dev.platform_data = capture_config;
932	platform_device_register(&vpif_dev);
933	platform_device_register(&vpif_display_dev);
934	platform_device_register(&vpif_capture_dev);
935}
936
937int __init dm646x_init_edma(struct edma_rsv_info *rsv)
938{
939	edma_cc0_info.rsv = rsv;
940
941	return platform_device_register(&dm646x_edma_device);
942}
943
944void __init dm646x_init(void)
945{
946	davinci_common_init(&davinci_soc_info_dm646x);
947	davinci_map_sysmod();
948}
949
950static int __init dm646x_init_devices(void)
951{
952	int ret = 0;
953
954	if (!cpu_is_davinci_dm646x())
955		return 0;
956
957	platform_device_register(&dm646x_mdio_device);
958	platform_device_register(&dm646x_emac_device);
959
960	ret = davinci_init_wdt();
961	if (ret)
962		pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
963
964	return ret;
965}
966postcore_initcall(dm646x_init_devices);
967