1/* 2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * EXYNOS - Suspend support 6 * 7 * Based on arch/arm/mach-s3c2410/pm.c 8 * Copyright (c) 2006 Simtec Electronics 9 * Ben Dooks <ben@simtec.co.uk> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16#include <linux/init.h> 17#include <linux/suspend.h> 18#include <linux/syscore_ops.h> 19#include <linux/cpu_pm.h> 20#include <linux/io.h> 21#include <linux/irq.h> 22#include <linux/irqdomain.h> 23#include <linux/of_address.h> 24#include <linux/err.h> 25#include <linux/regulator/machine.h> 26 27#include <asm/cacheflush.h> 28#include <asm/hardware/cache-l2x0.h> 29#include <asm/firmware.h> 30#include <asm/mcpm.h> 31#include <asm/smp_scu.h> 32#include <asm/suspend.h> 33 34#include <plat/pm-common.h> 35#include <plat/regs-srom.h> 36 37#include "common.h" 38#include "regs-pmu.h" 39#include "exynos-pmu.h" 40 41#define S5P_CHECK_SLEEP 0x00000BAD 42 43#define REG_TABLE_END (-1U) 44 45#define EXYNOS5420_CPU_STATE 0x28 46 47/** 48 * struct exynos_wkup_irq - PMU IRQ to mask mapping 49 * @hwirq: Hardware IRQ signal of the PMU 50 * @mask: Mask in PMU wake-up mask register 51 */ 52struct exynos_wkup_irq { 53 unsigned int hwirq; 54 u32 mask; 55}; 56 57static struct sleep_save exynos_core_save[] = { 58 /* SROM side */ 59 SAVE_ITEM(S5P_SROM_BW), 60 SAVE_ITEM(S5P_SROM_BC0), 61 SAVE_ITEM(S5P_SROM_BC1), 62 SAVE_ITEM(S5P_SROM_BC2), 63 SAVE_ITEM(S5P_SROM_BC3), 64}; 65 66struct exynos_pm_data { 67 const struct exynos_wkup_irq *wkup_irq; 68 unsigned int wake_disable_mask; 69 unsigned int *release_ret_regs; 70 71 void (*pm_prepare)(void); 72 void (*pm_resume_prepare)(void); 73 void (*pm_resume)(void); 74 int (*pm_suspend)(void); 75 int (*cpu_suspend)(unsigned long); 76}; 77 78static const struct exynos_pm_data *pm_data; 79 80static int exynos5420_cpu_state; 81static unsigned int exynos_pmu_spare3; 82 83/* 84 * GIC wake-up support 85 */ 86 87static u32 exynos_irqwake_intmask = 0xffffffff; 88 89static const struct exynos_wkup_irq exynos3250_wkup_irq[] = { 90 { 73, BIT(1) }, /* RTC alarm */ 91 { 74, BIT(2) }, /* RTC tick */ 92 { /* sentinel */ }, 93}; 94 95static const struct exynos_wkup_irq exynos4_wkup_irq[] = { 96 { 44, BIT(1) }, /* RTC alarm */ 97 { 45, BIT(2) }, /* RTC tick */ 98 { /* sentinel */ }, 99}; 100 101static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { 102 { 43, BIT(1) }, /* RTC alarm */ 103 { 44, BIT(2) }, /* RTC tick */ 104 { /* sentinel */ }, 105}; 106 107static unsigned int exynos_release_ret_regs[] = { 108 S5P_PAD_RET_MAUDIO_OPTION, 109 S5P_PAD_RET_GPIO_OPTION, 110 S5P_PAD_RET_UART_OPTION, 111 S5P_PAD_RET_MMCA_OPTION, 112 S5P_PAD_RET_MMCB_OPTION, 113 S5P_PAD_RET_EBIA_OPTION, 114 S5P_PAD_RET_EBIB_OPTION, 115 REG_TABLE_END, 116}; 117 118static unsigned int exynos3250_release_ret_regs[] = { 119 S5P_PAD_RET_MAUDIO_OPTION, 120 S5P_PAD_RET_GPIO_OPTION, 121 S5P_PAD_RET_UART_OPTION, 122 S5P_PAD_RET_MMCA_OPTION, 123 S5P_PAD_RET_MMCB_OPTION, 124 S5P_PAD_RET_EBIA_OPTION, 125 S5P_PAD_RET_EBIB_OPTION, 126 S5P_PAD_RET_MMC2_OPTION, 127 S5P_PAD_RET_SPI_OPTION, 128 REG_TABLE_END, 129}; 130 131static unsigned int exynos5420_release_ret_regs[] = { 132 EXYNOS_PAD_RET_DRAM_OPTION, 133 EXYNOS_PAD_RET_MAUDIO_OPTION, 134 EXYNOS_PAD_RET_JTAG_OPTION, 135 EXYNOS5420_PAD_RET_GPIO_OPTION, 136 EXYNOS5420_PAD_RET_UART_OPTION, 137 EXYNOS5420_PAD_RET_MMCA_OPTION, 138 EXYNOS5420_PAD_RET_MMCB_OPTION, 139 EXYNOS5420_PAD_RET_MMCC_OPTION, 140 EXYNOS5420_PAD_RET_HSI_OPTION, 141 EXYNOS_PAD_RET_EBIA_OPTION, 142 EXYNOS_PAD_RET_EBIB_OPTION, 143 EXYNOS5420_PAD_RET_SPI_OPTION, 144 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, 145 REG_TABLE_END, 146}; 147 148static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) 149{ 150 const struct exynos_wkup_irq *wkup_irq; 151 152 if (!pm_data->wkup_irq) 153 return -ENOENT; 154 wkup_irq = pm_data->wkup_irq; 155 156 while (wkup_irq->mask) { 157 if (wkup_irq->hwirq == data->hwirq) { 158 if (!state) 159 exynos_irqwake_intmask |= wkup_irq->mask; 160 else 161 exynos_irqwake_intmask &= ~wkup_irq->mask; 162 return 0; 163 } 164 ++wkup_irq; 165 } 166 167 return -ENOENT; 168} 169 170static struct irq_chip exynos_pmu_chip = { 171 .name = "PMU", 172 .irq_eoi = irq_chip_eoi_parent, 173 .irq_mask = irq_chip_mask_parent, 174 .irq_unmask = irq_chip_unmask_parent, 175 .irq_retrigger = irq_chip_retrigger_hierarchy, 176 .irq_set_wake = exynos_irq_set_wake, 177#ifdef CONFIG_SMP 178 .irq_set_affinity = irq_chip_set_affinity_parent, 179#endif 180}; 181 182static int exynos_pmu_domain_xlate(struct irq_domain *domain, 183 struct device_node *controller, 184 const u32 *intspec, 185 unsigned int intsize, 186 unsigned long *out_hwirq, 187 unsigned int *out_type) 188{ 189 if (domain->of_node != controller) 190 return -EINVAL; /* Shouldn't happen, really... */ 191 if (intsize != 3) 192 return -EINVAL; /* Not GIC compliant */ 193 if (intspec[0] != 0) 194 return -EINVAL; /* No PPI should point to this domain */ 195 196 *out_hwirq = intspec[1]; 197 *out_type = intspec[2]; 198 return 0; 199} 200 201static int exynos_pmu_domain_alloc(struct irq_domain *domain, 202 unsigned int virq, 203 unsigned int nr_irqs, void *data) 204{ 205 struct of_phandle_args *args = data; 206 struct of_phandle_args parent_args; 207 irq_hw_number_t hwirq; 208 int i; 209 210 if (args->args_count != 3) 211 return -EINVAL; /* Not GIC compliant */ 212 if (args->args[0] != 0) 213 return -EINVAL; /* No PPI should point to this domain */ 214 215 hwirq = args->args[1]; 216 217 for (i = 0; i < nr_irqs; i++) 218 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 219 &exynos_pmu_chip, NULL); 220 221 parent_args = *args; 222 parent_args.np = domain->parent->of_node; 223 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args); 224} 225 226static struct irq_domain_ops exynos_pmu_domain_ops = { 227 .xlate = exynos_pmu_domain_xlate, 228 .alloc = exynos_pmu_domain_alloc, 229 .free = irq_domain_free_irqs_common, 230}; 231 232static int __init exynos_pmu_irq_init(struct device_node *node, 233 struct device_node *parent) 234{ 235 struct irq_domain *parent_domain, *domain; 236 237 if (!parent) { 238 pr_err("%s: no parent, giving up\n", node->full_name); 239 return -ENODEV; 240 } 241 242 parent_domain = irq_find_host(parent); 243 if (!parent_domain) { 244 pr_err("%s: unable to obtain parent domain\n", node->full_name); 245 return -ENXIO; 246 } 247 248 pmu_base_addr = of_iomap(node, 0); 249 250 if (!pmu_base_addr) { 251 pr_err("%s: failed to find exynos pmu register\n", 252 node->full_name); 253 return -ENOMEM; 254 } 255 256 domain = irq_domain_add_hierarchy(parent_domain, 0, 0, 257 node, &exynos_pmu_domain_ops, 258 NULL); 259 if (!domain) { 260 iounmap(pmu_base_addr); 261 return -ENOMEM; 262 } 263 264 return 0; 265} 266 267#define EXYNOS_PMU_IRQ(symbol, name) OF_DECLARE_2(irqchip, symbol, name, exynos_pmu_irq_init) 268 269EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu"); 270EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu"); 271EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu"); 272EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu"); 273EXYNOS_PMU_IRQ(exynos4415_pmu_irq, "samsung,exynos4415-pmu"); 274EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu"); 275EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu"); 276 277static int exynos_cpu_do_idle(void) 278{ 279 /* issue the standby signal into the pm unit. */ 280 cpu_do_idle(); 281 282 pr_info("Failed to suspend the system\n"); 283 return 1; /* Aborting suspend */ 284} 285static void exynos_flush_cache_all(void) 286{ 287 flush_cache_all(); 288 outer_flush_all(); 289} 290 291static int exynos_cpu_suspend(unsigned long arg) 292{ 293 exynos_flush_cache_all(); 294 return exynos_cpu_do_idle(); 295} 296 297static int exynos3250_cpu_suspend(unsigned long arg) 298{ 299 flush_cache_all(); 300 return exynos_cpu_do_idle(); 301} 302 303static int exynos5420_cpu_suspend(unsigned long arg) 304{ 305 /* MCPM works with HW CPU identifiers */ 306 unsigned int mpidr = read_cpuid_mpidr(); 307 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); 308 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); 309 310 __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE); 311 312 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) { 313 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume); 314 315 /* 316 * Residency value passed to mcpm_cpu_suspend back-end 317 * has to be given clear semantics. Set to 0 as a 318 * temporary value. 319 */ 320 mcpm_cpu_suspend(0); 321 } 322 323 pr_info("Failed to suspend the system\n"); 324 325 /* return value != 0 means failure */ 326 return 1; 327} 328 329static void exynos_pm_set_wakeup_mask(void) 330{ 331 /* Set wake-up mask registers */ 332 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); 333 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 334} 335 336static void exynos_pm_enter_sleep_mode(void) 337{ 338 /* Set value of power down register for sleep mode */ 339 exynos_sys_powerdown_conf(SYS_SLEEP); 340 pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 341} 342 343static void exynos_pm_prepare(void) 344{ 345 exynos_set_delayed_reset_assertion(false); 346 347 /* Set wake-up mask registers */ 348 exynos_pm_set_wakeup_mask(); 349 350 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 351 352 exynos_pm_enter_sleep_mode(); 353 354 /* ensure at least INFORM0 has the resume address */ 355 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 356} 357 358static void exynos3250_pm_prepare(void) 359{ 360 unsigned int tmp; 361 362 /* Set wake-up mask registers */ 363 exynos_pm_set_wakeup_mask(); 364 365 tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION); 366 tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 367 pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION); 368 369 exynos_pm_enter_sleep_mode(); 370 371 /* ensure at least INFORM0 has the resume address */ 372 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 373} 374 375static void exynos5420_pm_prepare(void) 376{ 377 unsigned int tmp; 378 379 /* Set wake-up mask registers */ 380 exynos_pm_set_wakeup_mask(); 381 382 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 383 384 exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3); 385 /* 386 * The cpu state needs to be saved and restored so that the 387 * secondary CPUs will enter low power start. Though the U-Boot 388 * is setting the cpu state with low power flag, the kernel 389 * needs to restore it back in case, the primary cpu fails to 390 * suspend for any reason. 391 */ 392 exynos5420_cpu_state = __raw_readl(sysram_base_addr + 393 EXYNOS5420_CPU_STATE); 394 395 exynos_pm_enter_sleep_mode(); 396 397 /* ensure at least INFORM0 has the resume address */ 398 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) 399 pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0); 400 401 tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION); 402 tmp &= ~EXYNOS5_USE_RETENTION; 403 pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION); 404 405 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); 406 tmp |= EXYNOS5420_UFS; 407 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); 408 409 tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION); 410 tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE; 411 pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION); 412 413 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); 414 tmp |= EXYNOS5420_EMULATION; 415 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); 416 417 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); 418 tmp |= EXYNOS5420_EMULATION; 419 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); 420} 421 422 423static int exynos_pm_suspend(void) 424{ 425 exynos_pm_central_suspend(); 426 427 /* Setting SEQ_OPTION register */ 428 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, 429 S5P_CENTRAL_SEQ_OPTION); 430 431 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 432 exynos_cpu_save_register(); 433 434 return 0; 435} 436 437static int exynos5420_pm_suspend(void) 438{ 439 u32 this_cluster; 440 441 exynos_pm_central_suspend(); 442 443 /* Setting SEQ_OPTION register */ 444 445 this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); 446 if (!this_cluster) 447 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0, 448 S5P_CENTRAL_SEQ_OPTION); 449 else 450 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0, 451 S5P_CENTRAL_SEQ_OPTION); 452 return 0; 453} 454 455static void exynos_pm_release_retention(void) 456{ 457 unsigned int i; 458 459 for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++) 460 pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR, 461 pm_data->release_ret_regs[i]); 462} 463 464static void exynos_pm_resume(void) 465{ 466 u32 cpuid = read_cpuid_part(); 467 468 if (exynos_pm_central_resume()) 469 goto early_wakeup; 470 471 /* For release retention */ 472 exynos_pm_release_retention(); 473 474 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 475 476 if (cpuid == ARM_CPU_PART_CORTEX_A9) 477 scu_enable(S5P_VA_SCU); 478 479 if (call_firmware_op(resume) == -ENOSYS 480 && cpuid == ARM_CPU_PART_CORTEX_A9) 481 exynos_cpu_restore_register(); 482 483early_wakeup: 484 485 /* Clear SLEEP mode set in INFORM1 */ 486 pmu_raw_writel(0x0, S5P_INFORM1); 487 exynos_set_delayed_reset_assertion(true); 488} 489 490static void exynos3250_pm_resume(void) 491{ 492 u32 cpuid = read_cpuid_part(); 493 494 if (exynos_pm_central_resume()) 495 goto early_wakeup; 496 497 /* For release retention */ 498 exynos_pm_release_retention(); 499 500 pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION); 501 502 if (call_firmware_op(resume) == -ENOSYS 503 && cpuid == ARM_CPU_PART_CORTEX_A9) 504 exynos_cpu_restore_register(); 505 506early_wakeup: 507 508 /* Clear SLEEP mode set in INFORM1 */ 509 pmu_raw_writel(0x0, S5P_INFORM1); 510} 511 512static void exynos5420_prepare_pm_resume(void) 513{ 514 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) 515 WARN_ON(mcpm_cpu_powered_up()); 516} 517 518static void exynos5420_pm_resume(void) 519{ 520 unsigned long tmp; 521 522 /* Restore the CPU0 low power state register */ 523 tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG); 524 pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN, 525 EXYNOS5_ARM_CORE0_SYS_PWR_REG); 526 527 /* Restore the sysram cpu state register */ 528 __raw_writel(exynos5420_cpu_state, 529 sysram_base_addr + EXYNOS5420_CPU_STATE); 530 531 pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, 532 S5P_CENTRAL_SEQ_OPTION); 533 534 if (exynos_pm_central_resume()) 535 goto early_wakeup; 536 537 /* For release retention */ 538 exynos_pm_release_retention(); 539 540 pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3); 541 542 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 543 544early_wakeup: 545 546 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); 547 tmp &= ~EXYNOS5420_UFS; 548 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); 549 550 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); 551 tmp &= ~EXYNOS5420_EMULATION; 552 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); 553 554 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); 555 tmp &= ~EXYNOS5420_EMULATION; 556 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); 557 558 /* Clear SLEEP mode set in INFORM1 */ 559 pmu_raw_writel(0x0, S5P_INFORM1); 560} 561 562/* 563 * Suspend Ops 564 */ 565 566static int exynos_suspend_enter(suspend_state_t state) 567{ 568 int ret; 569 570 s3c_pm_debug_init(); 571 572 S3C_PMDBG("%s: suspending the system...\n", __func__); 573 574 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, 575 exynos_irqwake_intmask, exynos_get_eint_wake_mask()); 576 577 if (exynos_irqwake_intmask == -1U 578 && exynos_get_eint_wake_mask() == -1U) { 579 pr_err("%s: No wake-up sources!\n", __func__); 580 pr_err("%s: Aborting sleep\n", __func__); 581 return -EINVAL; 582 } 583 584 s3c_pm_save_uarts(); 585 if (pm_data->pm_prepare) 586 pm_data->pm_prepare(); 587 flush_cache_all(); 588 s3c_pm_check_store(); 589 590 ret = call_firmware_op(suspend); 591 if (ret == -ENOSYS) 592 ret = cpu_suspend(0, pm_data->cpu_suspend); 593 if (ret) 594 return ret; 595 596 if (pm_data->pm_resume_prepare) 597 pm_data->pm_resume_prepare(); 598 s3c_pm_restore_uarts(); 599 600 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, 601 pmu_raw_readl(S5P_WAKEUP_STAT)); 602 603 s3c_pm_check_restore(); 604 605 S3C_PMDBG("%s: resuming the system...\n", __func__); 606 607 return 0; 608} 609 610static int exynos_suspend_prepare(void) 611{ 612 int ret; 613 614 /* 615 * REVISIT: It would be better if struct platform_suspend_ops 616 * .prepare handler get the suspend_state_t as a parameter to 617 * avoid hard-coding the suspend to mem state. It's safe to do 618 * it now only because the suspend_valid_only_mem function is 619 * used as the .valid callback used to check if a given state 620 * is supported by the platform anyways. 621 */ 622 ret = regulator_suspend_prepare(PM_SUSPEND_MEM); 623 if (ret) { 624 pr_err("Failed to prepare regulators for suspend (%d)\n", ret); 625 return ret; 626 } 627 628 s3c_pm_check_prepare(); 629 630 return 0; 631} 632 633static void exynos_suspend_finish(void) 634{ 635 int ret; 636 637 s3c_pm_check_cleanup(); 638 639 ret = regulator_suspend_finish(); 640 if (ret) 641 pr_warn("Failed to resume regulators from suspend (%d)\n", ret); 642} 643 644static const struct platform_suspend_ops exynos_suspend_ops = { 645 .enter = exynos_suspend_enter, 646 .prepare = exynos_suspend_prepare, 647 .finish = exynos_suspend_finish, 648 .valid = suspend_valid_only_mem, 649}; 650 651static const struct exynos_pm_data exynos3250_pm_data = { 652 .wkup_irq = exynos3250_wkup_irq, 653 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 654 .release_ret_regs = exynos3250_release_ret_regs, 655 .pm_suspend = exynos_pm_suspend, 656 .pm_resume = exynos3250_pm_resume, 657 .pm_prepare = exynos3250_pm_prepare, 658 .cpu_suspend = exynos3250_cpu_suspend, 659}; 660 661static const struct exynos_pm_data exynos4_pm_data = { 662 .wkup_irq = exynos4_wkup_irq, 663 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 664 .release_ret_regs = exynos_release_ret_regs, 665 .pm_suspend = exynos_pm_suspend, 666 .pm_resume = exynos_pm_resume, 667 .pm_prepare = exynos_pm_prepare, 668 .cpu_suspend = exynos_cpu_suspend, 669}; 670 671static const struct exynos_pm_data exynos5250_pm_data = { 672 .wkup_irq = exynos5250_wkup_irq, 673 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 674 .release_ret_regs = exynos_release_ret_regs, 675 .pm_suspend = exynos_pm_suspend, 676 .pm_resume = exynos_pm_resume, 677 .pm_prepare = exynos_pm_prepare, 678 .cpu_suspend = exynos_cpu_suspend, 679}; 680 681static const struct exynos_pm_data exynos5420_pm_data = { 682 .wkup_irq = exynos5250_wkup_irq, 683 .wake_disable_mask = (0x7F << 7) | (0x1F << 1), 684 .release_ret_regs = exynos5420_release_ret_regs, 685 .pm_resume_prepare = exynos5420_prepare_pm_resume, 686 .pm_resume = exynos5420_pm_resume, 687 .pm_suspend = exynos5420_pm_suspend, 688 .pm_prepare = exynos5420_pm_prepare, 689 .cpu_suspend = exynos5420_cpu_suspend, 690}; 691 692static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { 693 { 694 .compatible = "samsung,exynos3250-pmu", 695 .data = &exynos3250_pm_data, 696 }, { 697 .compatible = "samsung,exynos4210-pmu", 698 .data = &exynos4_pm_data, 699 }, { 700 .compatible = "samsung,exynos4212-pmu", 701 .data = &exynos4_pm_data, 702 }, { 703 .compatible = "samsung,exynos4412-pmu", 704 .data = &exynos4_pm_data, 705 }, { 706 .compatible = "samsung,exynos5250-pmu", 707 .data = &exynos5250_pm_data, 708 }, { 709 .compatible = "samsung,exynos5420-pmu", 710 .data = &exynos5420_pm_data, 711 }, 712 { /*sentinel*/ }, 713}; 714 715static struct syscore_ops exynos_pm_syscore_ops; 716 717void __init exynos_pm_init(void) 718{ 719 const struct of_device_id *match; 720 struct device_node *np; 721 u32 tmp; 722 723 np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match); 724 if (!np) { 725 pr_err("Failed to find PMU node\n"); 726 return; 727 } 728 729 if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) { 730 pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); 731 return; 732 } 733 734 pm_data = (const struct exynos_pm_data *) match->data; 735 736 /* All wakeup disable */ 737 tmp = pmu_raw_readl(S5P_WAKEUP_MASK); 738 tmp |= pm_data->wake_disable_mask; 739 pmu_raw_writel(tmp, S5P_WAKEUP_MASK); 740 741 exynos_pm_syscore_ops.suspend = pm_data->pm_suspend; 742 exynos_pm_syscore_ops.resume = pm_data->pm_resume; 743 744 register_syscore_ops(&exynos_pm_syscore_ops); 745 suspend_set_ops(&exynos_suspend_ops); 746} 747