1/* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/io.h> 16#include <linux/irq.h> 17#include <linux/of.h> 18#include <linux/of_address.h> 19#include <linux/of_irq.h> 20#include <linux/platform_device.h> 21#include <linux/pm_domain.h> 22#include <linux/regulator/consumer.h> 23#include <linux/irqchip/arm-gic.h> 24#include "common.h" 25#include "hardware.h" 26 27#define GPC_CNTR 0x000 28#define GPC_IMR1 0x008 29#define GPC_PGC_GPU_PDN 0x260 30#define GPC_PGC_GPU_PUPSCR 0x264 31#define GPC_PGC_GPU_PDNSCR 0x268 32#define GPC_PGC_CPU_PDN 0x2a0 33#define GPC_PGC_CPU_PUPSCR 0x2a4 34#define GPC_PGC_CPU_PDNSCR 0x2a8 35#define GPC_PGC_SW2ISO_SHIFT 0x8 36#define GPC_PGC_SW_SHIFT 0x0 37 38#define IMR_NUM 4 39#define GPC_MAX_IRQS (IMR_NUM * 32) 40 41#define GPU_VPU_PUP_REQ BIT(1) 42#define GPU_VPU_PDN_REQ BIT(0) 43 44#define GPC_CLK_MAX 6 45 46struct pu_domain { 47 struct generic_pm_domain base; 48 struct regulator *reg; 49 struct clk *clk[GPC_CLK_MAX]; 50 int num_clks; 51}; 52 53static void __iomem *gpc_base; 54static u32 gpc_wake_irqs[IMR_NUM]; 55static u32 gpc_saved_imrs[IMR_NUM]; 56 57void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw) 58{ 59 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | 60 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR); 61} 62 63void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw) 64{ 65 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | 66 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR); 67} 68 69void imx_gpc_set_arm_power_in_lpm(bool power_off) 70{ 71 writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN); 72} 73 74void imx_gpc_pre_suspend(bool arm_power_off) 75{ 76 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 77 int i; 78 79 /* Tell GPC to power off ARM core when suspend */ 80 if (arm_power_off) 81 imx_gpc_set_arm_power_in_lpm(arm_power_off); 82 83 for (i = 0; i < IMR_NUM; i++) { 84 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); 85 writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4); 86 } 87} 88 89void imx_gpc_post_resume(void) 90{ 91 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 92 int i; 93 94 /* Keep ARM core powered on for other low-power modes */ 95 imx_gpc_set_arm_power_in_lpm(false); 96 97 for (i = 0; i < IMR_NUM; i++) 98 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); 99} 100 101static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on) 102{ 103 unsigned int idx = d->hwirq / 32; 104 u32 mask; 105 106 mask = 1 << d->hwirq % 32; 107 gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask : 108 gpc_wake_irqs[idx] & ~mask; 109 110 /* 111 * Do *not* call into the parent, as the GIC doesn't have any 112 * wake-up facility... 113 */ 114 return 0; 115} 116 117void imx_gpc_mask_all(void) 118{ 119 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 120 int i; 121 122 for (i = 0; i < IMR_NUM; i++) { 123 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); 124 writel_relaxed(~0, reg_imr1 + i * 4); 125 } 126 127} 128 129void imx_gpc_restore_all(void) 130{ 131 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 132 int i; 133 134 for (i = 0; i < IMR_NUM; i++) 135 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); 136} 137 138void imx_gpc_hwirq_unmask(unsigned int hwirq) 139{ 140 void __iomem *reg; 141 u32 val; 142 143 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; 144 val = readl_relaxed(reg); 145 val &= ~(1 << hwirq % 32); 146 writel_relaxed(val, reg); 147} 148 149void imx_gpc_hwirq_mask(unsigned int hwirq) 150{ 151 void __iomem *reg; 152 u32 val; 153 154 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; 155 val = readl_relaxed(reg); 156 val |= 1 << (hwirq % 32); 157 writel_relaxed(val, reg); 158} 159 160static void imx_gpc_irq_unmask(struct irq_data *d) 161{ 162 imx_gpc_hwirq_unmask(d->hwirq); 163 irq_chip_unmask_parent(d); 164} 165 166static void imx_gpc_irq_mask(struct irq_data *d) 167{ 168 imx_gpc_hwirq_mask(d->hwirq); 169 irq_chip_mask_parent(d); 170} 171 172static struct irq_chip imx_gpc_chip = { 173 .name = "GPC", 174 .irq_eoi = irq_chip_eoi_parent, 175 .irq_mask = imx_gpc_irq_mask, 176 .irq_unmask = imx_gpc_irq_unmask, 177 .irq_retrigger = irq_chip_retrigger_hierarchy, 178 .irq_set_wake = imx_gpc_irq_set_wake, 179#ifdef CONFIG_SMP 180 .irq_set_affinity = irq_chip_set_affinity_parent, 181#endif 182}; 183 184static int imx_gpc_domain_xlate(struct irq_domain *domain, 185 struct device_node *controller, 186 const u32 *intspec, 187 unsigned int intsize, 188 unsigned long *out_hwirq, 189 unsigned int *out_type) 190{ 191 if (domain->of_node != controller) 192 return -EINVAL; /* Shouldn't happen, really... */ 193 if (intsize != 3) 194 return -EINVAL; /* Not GIC compliant */ 195 if (intspec[0] != 0) 196 return -EINVAL; /* No PPI should point to this domain */ 197 198 *out_hwirq = intspec[1]; 199 *out_type = intspec[2]; 200 return 0; 201} 202 203static int imx_gpc_domain_alloc(struct irq_domain *domain, 204 unsigned int irq, 205 unsigned int nr_irqs, void *data) 206{ 207 struct of_phandle_args *args = data; 208 struct of_phandle_args parent_args; 209 irq_hw_number_t hwirq; 210 int i; 211 212 if (args->args_count != 3) 213 return -EINVAL; /* Not GIC compliant */ 214 if (args->args[0] != 0) 215 return -EINVAL; /* No PPI should point to this domain */ 216 217 hwirq = args->args[1]; 218 if (hwirq >= GPC_MAX_IRQS) 219 return -EINVAL; /* Can't deal with this */ 220 221 for (i = 0; i < nr_irqs; i++) 222 irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i, 223 &imx_gpc_chip, NULL); 224 225 parent_args = *args; 226 parent_args.np = domain->parent->of_node; 227 return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, &parent_args); 228} 229 230static struct irq_domain_ops imx_gpc_domain_ops = { 231 .xlate = imx_gpc_domain_xlate, 232 .alloc = imx_gpc_domain_alloc, 233 .free = irq_domain_free_irqs_common, 234}; 235 236static int __init imx_gpc_init(struct device_node *node, 237 struct device_node *parent) 238{ 239 struct irq_domain *parent_domain, *domain; 240 int i; 241 242 if (!parent) { 243 pr_err("%s: no parent, giving up\n", node->full_name); 244 return -ENODEV; 245 } 246 247 parent_domain = irq_find_host(parent); 248 if (!parent_domain) { 249 pr_err("%s: unable to obtain parent domain\n", node->full_name); 250 return -ENXIO; 251 } 252 253 gpc_base = of_iomap(node, 0); 254 if (WARN_ON(!gpc_base)) 255 return -ENOMEM; 256 257 domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS, 258 node, &imx_gpc_domain_ops, 259 NULL); 260 if (!domain) { 261 iounmap(gpc_base); 262 return -ENOMEM; 263 } 264 265 /* Initially mask all interrupts */ 266 for (i = 0; i < IMR_NUM; i++) 267 writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); 268 269 return 0; 270} 271 272/* 273 * We cannot use the IRQCHIP_DECLARE macro that lives in 274 * drivers/irqchip, so we're forced to roll our own. Not very nice. 275 */ 276OF_DECLARE_2(irqchip, imx_gpc, "fsl,imx6q-gpc", imx_gpc_init); 277 278void __init imx_gpc_check_dt(void) 279{ 280 struct device_node *np; 281 282 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); 283 if (WARN_ON(!np)) 284 return; 285 286 if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) { 287 pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); 288 289 /* map GPC, so that at least CPUidle and WARs keep working */ 290 gpc_base = of_iomap(np, 0); 291 } 292} 293 294static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd) 295{ 296 int iso, iso2sw; 297 u32 val; 298 299 /* Read ISO and ISO2SW power down delays */ 300 val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR); 301 iso = val & 0x3f; 302 iso2sw = (val >> 8) & 0x3f; 303 304 /* Gate off PU domain when GPU/VPU when powered down */ 305 writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN); 306 307 /* Request GPC to power down GPU/VPU */ 308 val = readl_relaxed(gpc_base + GPC_CNTR); 309 val |= GPU_VPU_PDN_REQ; 310 writel_relaxed(val, gpc_base + GPC_CNTR); 311 312 /* Wait ISO + ISO2SW IPG clock cycles */ 313 ndelay((iso + iso2sw) * 1000 / 66); 314} 315 316static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd) 317{ 318 struct pu_domain *pu = container_of(genpd, struct pu_domain, base); 319 320 _imx6q_pm_pu_power_off(genpd); 321 322 if (pu->reg) 323 regulator_disable(pu->reg); 324 325 return 0; 326} 327 328static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd) 329{ 330 struct pu_domain *pu = container_of(genpd, struct pu_domain, base); 331 int i, ret, sw, sw2iso; 332 u32 val; 333 334 if (pu->reg) 335 ret = regulator_enable(pu->reg); 336 if (pu->reg && ret) { 337 pr_err("%s: failed to enable regulator: %d\n", __func__, ret); 338 return ret; 339 } 340 341 /* Enable reset clocks for all devices in the PU domain */ 342 for (i = 0; i < pu->num_clks; i++) 343 clk_prepare_enable(pu->clk[i]); 344 345 /* Gate off PU domain when GPU/VPU when powered down */ 346 writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN); 347 348 /* Read ISO and ISO2SW power down delays */ 349 val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR); 350 sw = val & 0x3f; 351 sw2iso = (val >> 8) & 0x3f; 352 353 /* Request GPC to power up GPU/VPU */ 354 val = readl_relaxed(gpc_base + GPC_CNTR); 355 val |= GPU_VPU_PUP_REQ; 356 writel_relaxed(val, gpc_base + GPC_CNTR); 357 358 /* Wait ISO + ISO2SW IPG clock cycles */ 359 ndelay((sw + sw2iso) * 1000 / 66); 360 361 /* Disable reset clocks for all devices in the PU domain */ 362 for (i = 0; i < pu->num_clks; i++) 363 clk_disable_unprepare(pu->clk[i]); 364 365 return 0; 366} 367 368static struct generic_pm_domain imx6q_arm_domain = { 369 .name = "ARM", 370}; 371 372static struct pu_domain imx6q_pu_domain = { 373 .base = { 374 .name = "PU", 375 .power_off = imx6q_pm_pu_power_off, 376 .power_on = imx6q_pm_pu_power_on, 377 .power_off_latency_ns = 25000, 378 .power_on_latency_ns = 2000000, 379 }, 380}; 381 382static struct generic_pm_domain imx6sl_display_domain = { 383 .name = "DISPLAY", 384}; 385 386static struct generic_pm_domain *imx_gpc_domains[] = { 387 &imx6q_arm_domain, 388 &imx6q_pu_domain.base, 389 &imx6sl_display_domain, 390}; 391 392static struct genpd_onecell_data imx_gpc_onecell_data = { 393 .domains = imx_gpc_domains, 394 .num_domains = ARRAY_SIZE(imx_gpc_domains), 395}; 396 397static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg) 398{ 399 struct clk *clk; 400 int i; 401 402 imx6q_pu_domain.reg = pu_reg; 403 404 for (i = 0; ; i++) { 405 clk = of_clk_get(dev->of_node, i); 406 if (IS_ERR(clk)) 407 break; 408 if (i >= GPC_CLK_MAX) { 409 dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX); 410 goto clk_err; 411 } 412 imx6q_pu_domain.clk[i] = clk; 413 } 414 imx6q_pu_domain.num_clks = i; 415 416 /* Enable power always in case bootloader disabled it. */ 417 imx6q_pm_pu_power_on(&imx6q_pu_domain.base); 418 419 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) 420 return 0; 421 422 pm_genpd_init(&imx6q_pu_domain.base, NULL, false); 423 return of_genpd_add_provider_onecell(dev->of_node, 424 &imx_gpc_onecell_data); 425 426clk_err: 427 while (i--) 428 clk_put(imx6q_pu_domain.clk[i]); 429 return -EINVAL; 430} 431 432static int imx_gpc_probe(struct platform_device *pdev) 433{ 434 struct regulator *pu_reg; 435 int ret; 436 437 /* bail out if DT too old and doesn't provide the necessary info */ 438 if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells")) 439 return 0; 440 441 pu_reg = devm_regulator_get_optional(&pdev->dev, "pu"); 442 if (PTR_ERR(pu_reg) == -ENODEV) 443 pu_reg = NULL; 444 if (IS_ERR(pu_reg)) { 445 ret = PTR_ERR(pu_reg); 446 dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret); 447 return ret; 448 } 449 450 return imx_gpc_genpd_init(&pdev->dev, pu_reg); 451} 452 453static const struct of_device_id imx_gpc_dt_ids[] = { 454 { .compatible = "fsl,imx6q-gpc" }, 455 { .compatible = "fsl,imx6sl-gpc" }, 456 { } 457}; 458 459static struct platform_driver imx_gpc_driver = { 460 .driver = { 461 .name = "imx-gpc", 462 .owner = THIS_MODULE, 463 .of_match_table = imx_gpc_dt_ids, 464 }, 465 .probe = imx_gpc_probe, 466}; 467 468static int __init imx_pgc_init(void) 469{ 470 return platform_driver_register(&imx_gpc_driver); 471} 472subsys_initcall(imx_pgc_init); 473