1/* 2 * OMAP2plus display device setup / initialization. 3 * 4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 5 * Senthilvadivu Guruswamy 6 * Sumit Semwal 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18#include <linux/string.h> 19#include <linux/kernel.h> 20#include <linux/init.h> 21#include <linux/platform_device.h> 22#include <linux/io.h> 23#include <linux/clk.h> 24#include <linux/err.h> 25#include <linux/delay.h> 26#include <linux/of.h> 27#include <linux/of_platform.h> 28#include <linux/slab.h> 29#include <linux/mfd/syscon.h> 30#include <linux/regmap.h> 31 32#include <video/omapdss.h> 33#include "omap_hwmod.h" 34#include "omap_device.h" 35#include "omap-pm.h" 36#include "common.h" 37 38#include "soc.h" 39#include "iomap.h" 40#include "control.h" 41#include "display.h" 42#include "prm.h" 43 44#define DISPC_CONTROL 0x0040 45#define DISPC_CONTROL2 0x0238 46#define DISPC_CONTROL3 0x0848 47#define DISPC_IRQSTATUS 0x0018 48 49#define DSS_SYSCONFIG 0x10 50#define DSS_SYSSTATUS 0x14 51#define DSS_CONTROL 0x40 52#define DSS_SDI_CONTROL 0x44 53#define DSS_PLL_CONTROL 0x48 54 55#define LCD_EN_MASK (0x1 << 0) 56#define DIGIT_EN_MASK (0x1 << 1) 57 58#define FRAMEDONE_IRQ_SHIFT 0 59#define EVSYNC_EVEN_IRQ_SHIFT 2 60#define EVSYNC_ODD_IRQ_SHIFT 3 61#define FRAMEDONE2_IRQ_SHIFT 22 62#define FRAMEDONE3_IRQ_SHIFT 30 63#define FRAMEDONETV_IRQ_SHIFT 24 64 65/* 66 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC 67 * reset before deciding that something has gone wrong 68 */ 69#define FRAMEDONE_IRQ_TIMEOUT 100 70 71static struct platform_device omap_display_device = { 72 .name = "omapdss", 73 .id = -1, 74 .dev = { 75 .platform_data = NULL, 76 }, 77}; 78 79struct omap_dss_hwmod_data { 80 const char *oh_name; 81 const char *dev_name; 82 const int id; 83}; 84 85static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = { 86 { "dss_core", "omapdss_dss", -1 }, 87 { "dss_dispc", "omapdss_dispc", -1 }, 88 { "dss_rfbi", "omapdss_rfbi", -1 }, 89 { "dss_venc", "omapdss_venc", -1 }, 90}; 91 92static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = { 93 { "dss_core", "omapdss_dss", -1 }, 94 { "dss_dispc", "omapdss_dispc", -1 }, 95 { "dss_rfbi", "omapdss_rfbi", -1 }, 96 { "dss_venc", "omapdss_venc", -1 }, 97 { "dss_dsi1", "omapdss_dsi", 0 }, 98}; 99 100static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = { 101 { "dss_core", "omapdss_dss", -1 }, 102 { "dss_dispc", "omapdss_dispc", -1 }, 103 { "dss_rfbi", "omapdss_rfbi", -1 }, 104 { "dss_dsi1", "omapdss_dsi", 0 }, 105 { "dss_dsi2", "omapdss_dsi", 1 }, 106 { "dss_hdmi", "omapdss_hdmi", -1 }, 107}; 108 109#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78 110 111static struct regmap *omap4_dsi_mux_syscon; 112 113static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) 114{ 115 u32 enable_mask, enable_shift; 116 u32 pipd_mask, pipd_shift; 117 u32 reg; 118 119 if (dsi_id == 0) { 120 enable_mask = OMAP4_DSI1_LANEENABLE_MASK; 121 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; 122 pipd_mask = OMAP4_DSI1_PIPD_MASK; 123 pipd_shift = OMAP4_DSI1_PIPD_SHIFT; 124 } else if (dsi_id == 1) { 125 enable_mask = OMAP4_DSI2_LANEENABLE_MASK; 126 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; 127 pipd_mask = OMAP4_DSI2_PIPD_MASK; 128 pipd_shift = OMAP4_DSI2_PIPD_SHIFT; 129 } else { 130 return -ENODEV; 131 } 132 133 regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, ®); 134 135 reg &= ~enable_mask; 136 reg &= ~pipd_mask; 137 138 reg |= (lanes << enable_shift) & enable_mask; 139 reg |= (lanes << pipd_shift) & pipd_mask; 140 141 regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg); 142 143 return 0; 144} 145 146static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) 147{ 148 if (cpu_is_omap44xx()) 149 return omap4_dsi_mux_pads(dsi_id, lane_mask); 150 151 return 0; 152} 153 154static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) 155{ 156 if (cpu_is_omap44xx()) 157 omap4_dsi_mux_pads(dsi_id, 0); 158} 159 160static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput) 161{ 162 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput); 163} 164 165static struct platform_device *create_dss_pdev(const char *pdev_name, 166 int pdev_id, const char *oh_name, void *pdata, int pdata_len, 167 struct platform_device *parent) 168{ 169 struct platform_device *pdev; 170 struct omap_device *od; 171 struct omap_hwmod *ohs[1]; 172 struct omap_hwmod *oh; 173 int r; 174 175 oh = omap_hwmod_lookup(oh_name); 176 if (!oh) { 177 pr_err("Could not look up %s\n", oh_name); 178 r = -ENODEV; 179 goto err; 180 } 181 182 pdev = platform_device_alloc(pdev_name, pdev_id); 183 if (!pdev) { 184 pr_err("Could not create pdev for %s\n", pdev_name); 185 r = -ENOMEM; 186 goto err; 187 } 188 189 if (parent != NULL) 190 pdev->dev.parent = &parent->dev; 191 192 if (pdev->id != -1) 193 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); 194 else 195 dev_set_name(&pdev->dev, "%s", pdev->name); 196 197 ohs[0] = oh; 198 od = omap_device_alloc(pdev, ohs, 1); 199 if (IS_ERR(od)) { 200 pr_err("Could not alloc omap_device for %s\n", pdev_name); 201 r = -ENOMEM; 202 goto err; 203 } 204 205 r = platform_device_add_data(pdev, pdata, pdata_len); 206 if (r) { 207 pr_err("Could not set pdata for %s\n", pdev_name); 208 goto err; 209 } 210 211 r = omap_device_register(pdev); 212 if (r) { 213 pr_err("Could not register omap_device for %s\n", pdev_name); 214 goto err; 215 } 216 217 return pdev; 218 219err: 220 return ERR_PTR(r); 221} 222 223static struct platform_device *create_simple_dss_pdev(const char *pdev_name, 224 int pdev_id, void *pdata, int pdata_len, 225 struct platform_device *parent) 226{ 227 struct platform_device *pdev; 228 int r; 229 230 pdev = platform_device_alloc(pdev_name, pdev_id); 231 if (!pdev) { 232 pr_err("Could not create pdev for %s\n", pdev_name); 233 r = -ENOMEM; 234 goto err; 235 } 236 237 if (parent != NULL) 238 pdev->dev.parent = &parent->dev; 239 240 if (pdev->id != -1) 241 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); 242 else 243 dev_set_name(&pdev->dev, "%s", pdev->name); 244 245 r = platform_device_add_data(pdev, pdata, pdata_len); 246 if (r) { 247 pr_err("Could not set pdata for %s\n", pdev_name); 248 goto err; 249 } 250 251 r = platform_device_add(pdev); 252 if (r) { 253 pr_err("Could not register platform_device for %s\n", pdev_name); 254 goto err; 255 } 256 257 return pdev; 258 259err: 260 return ERR_PTR(r); 261} 262 263static enum omapdss_version __init omap_display_get_version(void) 264{ 265 if (cpu_is_omap24xx()) 266 return OMAPDSS_VER_OMAP24xx; 267 else if (cpu_is_omap3630()) 268 return OMAPDSS_VER_OMAP3630; 269 else if (cpu_is_omap34xx()) { 270 if (soc_is_am35xx()) { 271 return OMAPDSS_VER_AM35xx; 272 } else { 273 if (omap_rev() < OMAP3430_REV_ES3_0) 274 return OMAPDSS_VER_OMAP34xx_ES1; 275 else 276 return OMAPDSS_VER_OMAP34xx_ES3; 277 } 278 } else if (omap_rev() == OMAP4430_REV_ES1_0) 279 return OMAPDSS_VER_OMAP4430_ES1; 280 else if (omap_rev() == OMAP4430_REV_ES2_0 || 281 omap_rev() == OMAP4430_REV_ES2_1 || 282 omap_rev() == OMAP4430_REV_ES2_2) 283 return OMAPDSS_VER_OMAP4430_ES2; 284 else if (cpu_is_omap44xx()) 285 return OMAPDSS_VER_OMAP4; 286 else if (soc_is_omap54xx()) 287 return OMAPDSS_VER_OMAP5; 288 else if (soc_is_am43xx()) 289 return OMAPDSS_VER_AM43xx; 290 else 291 return OMAPDSS_VER_UNKNOWN; 292} 293 294int __init omap_display_init(struct omap_dss_board_info *board_data) 295{ 296 int r = 0; 297 struct platform_device *pdev; 298 int i, oh_count; 299 const struct omap_dss_hwmod_data *curr_dss_hwmod; 300 struct platform_device *dss_pdev; 301 enum omapdss_version ver; 302 303 /* create omapdss device */ 304 305 ver = omap_display_get_version(); 306 307 if (ver == OMAPDSS_VER_UNKNOWN) { 308 pr_err("DSS not supported on this SoC\n"); 309 return -ENODEV; 310 } 311 312 board_data->version = ver; 313 board_data->dsi_enable_pads = omap_dsi_enable_pads; 314 board_data->dsi_disable_pads = omap_dsi_disable_pads; 315 board_data->set_min_bus_tput = omap_dss_set_min_bus_tput; 316 317 omap_display_device.dev.platform_data = board_data; 318 319 r = platform_device_register(&omap_display_device); 320 if (r < 0) { 321 pr_err("Unable to register omapdss device\n"); 322 return r; 323 } 324 325 /* create devices for dss hwmods */ 326 327 if (cpu_is_omap24xx()) { 328 curr_dss_hwmod = omap2_dss_hwmod_data; 329 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data); 330 } else if (cpu_is_omap34xx()) { 331 curr_dss_hwmod = omap3_dss_hwmod_data; 332 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data); 333 } else { 334 curr_dss_hwmod = omap4_dss_hwmod_data; 335 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data); 336 } 337 338 /* 339 * First create the pdev for dss_core, which is used as a parent device 340 * by the other dss pdevs. Note: dss_core has to be the first item in 341 * the hwmod list. 342 */ 343 dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name, 344 curr_dss_hwmod[0].id, 345 curr_dss_hwmod[0].oh_name, 346 board_data, sizeof(*board_data), 347 NULL); 348 349 if (IS_ERR(dss_pdev)) { 350 pr_err("Could not build omap_device for %s\n", 351 curr_dss_hwmod[0].oh_name); 352 353 return PTR_ERR(dss_pdev); 354 } 355 356 for (i = 1; i < oh_count; i++) { 357 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name, 358 curr_dss_hwmod[i].id, 359 curr_dss_hwmod[i].oh_name, 360 board_data, sizeof(*board_data), 361 dss_pdev); 362 363 if (IS_ERR(pdev)) { 364 pr_err("Could not build omap_device for %s\n", 365 curr_dss_hwmod[i].oh_name); 366 367 return PTR_ERR(pdev); 368 } 369 } 370 371 /* Create devices for DPI and SDI */ 372 373 pdev = create_simple_dss_pdev("omapdss_dpi", 0, 374 board_data, sizeof(*board_data), dss_pdev); 375 if (IS_ERR(pdev)) { 376 pr_err("Could not build platform_device for omapdss_dpi\n"); 377 return PTR_ERR(pdev); 378 } 379 380 if (cpu_is_omap34xx()) { 381 pdev = create_simple_dss_pdev("omapdss_sdi", 0, 382 board_data, sizeof(*board_data), dss_pdev); 383 if (IS_ERR(pdev)) { 384 pr_err("Could not build platform_device for omapdss_sdi\n"); 385 return PTR_ERR(pdev); 386 } 387 } 388 389 /* create DRM device */ 390 r = omap_init_drm(); 391 if (r < 0) { 392 pr_err("Unable to register omapdrm device\n"); 393 return r; 394 } 395 396 /* create vrfb device */ 397 r = omap_init_vrfb(); 398 if (r < 0) { 399 pr_err("Unable to register omapvrfb device\n"); 400 return r; 401 } 402 403 /* create FB device */ 404 r = omap_init_fb(); 405 if (r < 0) { 406 pr_err("Unable to register omapfb device\n"); 407 return r; 408 } 409 410 /* create V4L2 display device */ 411 r = omap_init_vout(); 412 if (r < 0) { 413 pr_err("Unable to register omap_vout device\n"); 414 return r; 415 } 416 417 return 0; 418} 419 420static void dispc_disable_outputs(void) 421{ 422 u32 v, irq_mask = 0; 423 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; 424 int i; 425 struct omap_dss_dispc_dev_attr *da; 426 struct omap_hwmod *oh; 427 428 oh = omap_hwmod_lookup("dss_dispc"); 429 if (!oh) { 430 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n"); 431 return; 432 } 433 434 if (!oh->dev_attr) { 435 pr_err("display: could not disable outputs during reset due to missing dev_attr\n"); 436 return; 437 } 438 439 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr; 440 441 /* store value of LCDENABLE and DIGITENABLE bits */ 442 v = omap_hwmod_read(oh, DISPC_CONTROL); 443 lcd_en = v & LCD_EN_MASK; 444 digit_en = v & DIGIT_EN_MASK; 445 446 /* store value of LCDENABLE for LCD2 */ 447 if (da->manager_count > 2) { 448 v = omap_hwmod_read(oh, DISPC_CONTROL2); 449 lcd2_en = v & LCD_EN_MASK; 450 } 451 452 /* store value of LCDENABLE for LCD3 */ 453 if (da->manager_count > 3) { 454 v = omap_hwmod_read(oh, DISPC_CONTROL3); 455 lcd3_en = v & LCD_EN_MASK; 456 } 457 458 if (!(lcd_en | digit_en | lcd2_en | lcd3_en)) 459 return; /* no managers currently enabled */ 460 461 /* 462 * If any manager was enabled, we need to disable it before 463 * DSS clocks are disabled or DISPC module is reset 464 */ 465 if (lcd_en) 466 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT; 467 468 if (digit_en) { 469 if (da->has_framedonetv_irq) { 470 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT; 471 } else { 472 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT | 473 1 << EVSYNC_ODD_IRQ_SHIFT; 474 } 475 } 476 477 if (lcd2_en) 478 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT; 479 if (lcd3_en) 480 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT; 481 482 /* 483 * clear any previous FRAMEDONE, FRAMEDONETV, 484 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts 485 */ 486 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS); 487 488 /* disable LCD and TV managers */ 489 v = omap_hwmod_read(oh, DISPC_CONTROL); 490 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK); 491 omap_hwmod_write(v, oh, DISPC_CONTROL); 492 493 /* disable LCD2 manager */ 494 if (da->manager_count > 2) { 495 v = omap_hwmod_read(oh, DISPC_CONTROL2); 496 v &= ~LCD_EN_MASK; 497 omap_hwmod_write(v, oh, DISPC_CONTROL2); 498 } 499 500 /* disable LCD3 manager */ 501 if (da->manager_count > 3) { 502 v = omap_hwmod_read(oh, DISPC_CONTROL3); 503 v &= ~LCD_EN_MASK; 504 omap_hwmod_write(v, oh, DISPC_CONTROL3); 505 } 506 507 i = 0; 508 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) != 509 irq_mask) { 510 i++; 511 if (i > FRAMEDONE_IRQ_TIMEOUT) { 512 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n"); 513 break; 514 } 515 mdelay(1); 516 } 517} 518 519int omap_dss_reset(struct omap_hwmod *oh) 520{ 521 struct omap_hwmod_opt_clk *oc; 522 int c = 0; 523 int i, r; 524 525 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) { 526 pr_err("dss_core: hwmod data doesn't contain reset data\n"); 527 return -EINVAL; 528 } 529 530 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 531 if (oc->_clk) 532 clk_prepare_enable(oc->_clk); 533 534 dispc_disable_outputs(); 535 536 /* clear SDI registers */ 537 if (cpu_is_omap3430()) { 538 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL); 539 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL); 540 } 541 542 /* 543 * clear DSS_CONTROL register to switch DSS clock sources to 544 * PRCM clock, if any 545 */ 546 omap_hwmod_write(0x0, oh, DSS_CONTROL); 547 548 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) 549 & SYSS_RESETDONE_MASK), 550 MAX_MODULE_SOFTRESET_WAIT, c); 551 552 if (c == MAX_MODULE_SOFTRESET_WAIT) 553 pr_warn("dss_core: waiting for reset to finish failed\n"); 554 else 555 pr_debug("dss_core: softreset done\n"); 556 557 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 558 if (oc->_clk) 559 clk_disable_unprepare(oc->_clk); 560 561 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; 562 563 return r; 564} 565 566void __init omapdss_early_init_of(void) 567{ 568 569} 570 571struct device_node * __init omapdss_find_dss_of_node(void) 572{ 573 struct device_node *node; 574 575 node = of_find_compatible_node(NULL, NULL, "ti,omap2-dss"); 576 if (node) 577 return node; 578 579 node = of_find_compatible_node(NULL, NULL, "ti,omap3-dss"); 580 if (node) 581 return node; 582 583 node = of_find_compatible_node(NULL, NULL, "ti,omap4-dss"); 584 if (node) 585 return node; 586 587 node = of_find_compatible_node(NULL, NULL, "ti,omap5-dss"); 588 if (node) 589 return node; 590 591 return NULL; 592} 593 594int __init omapdss_init_of(void) 595{ 596 int r; 597 enum omapdss_version ver; 598 struct device_node *node; 599 struct platform_device *pdev; 600 601 static struct omap_dss_board_info board_data = { 602 .dsi_enable_pads = omap_dsi_enable_pads, 603 .dsi_disable_pads = omap_dsi_disable_pads, 604 .set_min_bus_tput = omap_dss_set_min_bus_tput, 605 }; 606 607 /* only create dss helper devices if dss is enabled in the .dts */ 608 609 node = omapdss_find_dss_of_node(); 610 if (!node) 611 return 0; 612 613 if (!of_device_is_available(node)) 614 return 0; 615 616 ver = omap_display_get_version(); 617 618 if (ver == OMAPDSS_VER_UNKNOWN) { 619 pr_err("DSS not supported on this SoC\n"); 620 return -ENODEV; 621 } 622 623 pdev = of_find_device_by_node(node); 624 625 if (!pdev) { 626 pr_err("Unable to find DSS platform device\n"); 627 return -ENODEV; 628 } 629 630 r = of_platform_populate(node, NULL, NULL, &pdev->dev); 631 if (r) { 632 pr_err("Unable to populate DSS submodule devices\n"); 633 return r; 634 } 635 636 board_data.version = ver; 637 638 omap_display_device.dev.platform_data = &board_data; 639 640 r = platform_device_register(&omap_display_device); 641 if (r < 0) { 642 pr_err("Unable to register omapdss device\n"); 643 return r; 644 } 645 646 /* create DRM device */ 647 r = omap_init_drm(); 648 if (r < 0) { 649 pr_err("Unable to register omapdrm device\n"); 650 return r; 651 } 652 653 /* create vrfb device */ 654 r = omap_init_vrfb(); 655 if (r < 0) { 656 pr_err("Unable to register omapvrfb device\n"); 657 return r; 658 } 659 660 /* create FB device */ 661 r = omap_init_fb(); 662 if (r < 0) { 663 pr_err("Unable to register omapfb device\n"); 664 return r; 665 } 666 667 /* create V4L2 display device */ 668 r = omap_init_vout(); 669 if (r < 0) { 670 pr_err("Unable to register omap_vout device\n"); 671 return r; 672 } 673 674 /* add DSI info for omap4 */ 675 node = of_find_node_by_name(NULL, "omap4_padconf_global"); 676 if (node) 677 omap4_dsi_mux_syscon = syscon_node_to_regmap(node); 678 679 return 0; 680} 681