1/* 2 * linux/arch/arm/mach-omap2/id.c 3 * 4 * OMAP2 CPU identification code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Written by Tony Lindgren <tony@atomide.com> 8 * 9 * Copyright (C) 2009-11 Texas Instruments 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17#include <linux/module.h> 18#include <linux/kernel.h> 19#include <linux/init.h> 20#include <linux/io.h> 21#include <linux/random.h> 22#include <linux/slab.h> 23 24#ifdef CONFIG_SOC_BUS 25#include <linux/sys_soc.h> 26#endif 27 28#include <asm/cputype.h> 29 30#include "common.h" 31 32#include "id.h" 33 34#include "soc.h" 35#include "control.h" 36 37#define OMAP4_SILICON_TYPE_STANDARD 0x01 38#define OMAP4_SILICON_TYPE_PERFORMANCE 0x02 39 40#define OMAP_SOC_MAX_NAME_LENGTH 16 41 42static unsigned int omap_revision; 43static char soc_name[OMAP_SOC_MAX_NAME_LENGTH]; 44static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH]; 45u32 omap_features; 46 47unsigned int omap_rev(void) 48{ 49 return omap_revision; 50} 51EXPORT_SYMBOL(omap_rev); 52 53int omap_type(void) 54{ 55 static u32 val = OMAP2_DEVICETYPE_MASK; 56 57 if (val < OMAP2_DEVICETYPE_MASK) 58 return val; 59 60 if (cpu_is_omap24xx()) { 61 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); 62 } else if (cpu_is_ti81xx()) { 63 val = omap_ctrl_readl(TI81XX_CONTROL_STATUS); 64 } else if (soc_is_am33xx() || soc_is_am43xx()) { 65 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); 66 } else if (cpu_is_omap34xx()) { 67 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 68 } else if (cpu_is_omap44xx()) { 69 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); 70 } else if (soc_is_omap54xx() || soc_is_dra7xx()) { 71 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); 72 val &= OMAP5_DEVICETYPE_MASK; 73 val >>= 6; 74 goto out; 75 } else { 76 pr_err("Cannot detect omap type!\n"); 77 goto out; 78 } 79 80 val &= OMAP2_DEVICETYPE_MASK; 81 val >>= 8; 82 83out: 84 return val; 85} 86EXPORT_SYMBOL(omap_type); 87 88 89/*----------------------------------------------------------------------------*/ 90 91#define OMAP_TAP_IDCODE 0x0204 92#define OMAP_TAP_DIE_ID_0 0x0218 93#define OMAP_TAP_DIE_ID_1 0x021C 94#define OMAP_TAP_DIE_ID_2 0x0220 95#define OMAP_TAP_DIE_ID_3 0x0224 96 97#define OMAP_TAP_DIE_ID_44XX_0 0x0200 98#define OMAP_TAP_DIE_ID_44XX_1 0x0208 99#define OMAP_TAP_DIE_ID_44XX_2 0x020c 100#define OMAP_TAP_DIE_ID_44XX_3 0x0210 101 102#define read_tap_reg(reg) readl_relaxed(tap_base + (reg)) 103 104struct omap_id { 105 u16 hawkeye; /* Silicon type (Hawkeye id) */ 106 u8 dev; /* Device type from production_id reg */ 107 u32 type; /* Combined type id copied to omap_revision */ 108}; 109 110/* Register values to detect the OMAP version */ 111static struct omap_id omap_ids[] __initdata = { 112 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, 113 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, 114 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, 115 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, 116 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, 117 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, 118}; 119 120static void __iomem *tap_base; 121static u16 tap_prod_id; 122 123void omap_get_die_id(struct omap_die_id *odi) 124{ 125 if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { 126 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); 127 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); 128 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); 129 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); 130 131 return; 132 } 133 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); 134 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); 135 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); 136 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); 137} 138 139static int __init omap_feed_randpool(void) 140{ 141 struct omap_die_id odi; 142 143 /* Throw the die ID into the entropy pool at boot */ 144 omap_get_die_id(&odi); 145 add_device_randomness(&odi, sizeof(odi)); 146 return 0; 147} 148omap_device_initcall(omap_feed_randpool); 149 150void __init omap2xxx_check_revision(void) 151{ 152 int i, j; 153 u32 idcode, prod_id; 154 u16 hawkeye; 155 u8 dev_type, rev; 156 struct omap_die_id odi; 157 158 idcode = read_tap_reg(OMAP_TAP_IDCODE); 159 prod_id = read_tap_reg(tap_prod_id); 160 hawkeye = (idcode >> 12) & 0xffff; 161 rev = (idcode >> 28) & 0x0f; 162 dev_type = (prod_id >> 16) & 0x0f; 163 omap_get_die_id(&odi); 164 165 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", 166 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); 167 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); 168 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", 169 odi.id_1, (odi.id_1 >> 28) & 0xf); 170 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); 171 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); 172 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", 173 prod_id, dev_type); 174 175 /* Check hawkeye ids */ 176 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { 177 if (hawkeye == omap_ids[i].hawkeye) 178 break; 179 } 180 181 if (i == ARRAY_SIZE(omap_ids)) { 182 printk(KERN_ERR "Unknown OMAP CPU id\n"); 183 return; 184 } 185 186 for (j = i; j < ARRAY_SIZE(omap_ids); j++) { 187 if (dev_type == omap_ids[j].dev) 188 break; 189 } 190 191 if (j == ARRAY_SIZE(omap_ids)) { 192 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n", 193 omap_ids[i].type >> 16); 194 j = i; 195 } 196 197 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); 198 sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf); 199 200 pr_info("%s", soc_name); 201 if ((omap_rev() >> 8) & 0x0f) 202 pr_info("%s", soc_rev); 203 pr_info("\n"); 204} 205 206#define OMAP3_SHOW_FEATURE(feat) \ 207 if (omap3_has_ ##feat()) \ 208 printk(#feat" "); 209 210static void __init omap3_cpuinfo(void) 211{ 212 const char *cpu_name; 213 214 /* 215 * OMAP3430 and OMAP3530 are assumed to be same. 216 * 217 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based 218 * on available features. Upon detection, update the CPU id 219 * and CPU class bits. 220 */ 221 if (cpu_is_omap3630()) { 222 cpu_name = "OMAP3630"; 223 } else if (soc_is_am35xx()) { 224 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; 225 } else if (cpu_is_ti816x()) { 226 cpu_name = "TI816X"; 227 } else if (soc_is_am335x()) { 228 cpu_name = "AM335X"; 229 } else if (soc_is_am437x()) { 230 cpu_name = "AM437x"; 231 } else if (cpu_is_ti814x()) { 232 cpu_name = "TI814X"; 233 } else if (omap3_has_iva() && omap3_has_sgx()) { 234 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ 235 cpu_name = "OMAP3430/3530"; 236 } else if (omap3_has_iva()) { 237 cpu_name = "OMAP3525"; 238 } else if (omap3_has_sgx()) { 239 cpu_name = "OMAP3515"; 240 } else { 241 cpu_name = "OMAP3503"; 242 } 243 244 sprintf(soc_name, "%s", cpu_name); 245 246 /* Print verbose information */ 247 pr_info("%s %s (", soc_name, soc_rev); 248 249 OMAP3_SHOW_FEATURE(l2cache); 250 OMAP3_SHOW_FEATURE(iva); 251 OMAP3_SHOW_FEATURE(sgx); 252 OMAP3_SHOW_FEATURE(neon); 253 OMAP3_SHOW_FEATURE(isp); 254 OMAP3_SHOW_FEATURE(192mhz_clk); 255 256 printk(")\n"); 257} 258 259#define OMAP3_CHECK_FEATURE(status,feat) \ 260 if (((status & OMAP3_ ##feat## _MASK) \ 261 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ 262 omap_features |= OMAP3_HAS_ ##feat; \ 263 } 264 265void __init omap3xxx_check_features(void) 266{ 267 u32 status; 268 269 omap_features = 0; 270 271 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); 272 273 OMAP3_CHECK_FEATURE(status, L2CACHE); 274 OMAP3_CHECK_FEATURE(status, IVA); 275 OMAP3_CHECK_FEATURE(status, SGX); 276 OMAP3_CHECK_FEATURE(status, NEON); 277 OMAP3_CHECK_FEATURE(status, ISP); 278 if (cpu_is_omap3630()) 279 omap_features |= OMAP3_HAS_192MHZ_CLK; 280 if (cpu_is_omap3430() || cpu_is_omap3630()) 281 omap_features |= OMAP3_HAS_IO_WAKEUP; 282 if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 || 283 omap_rev() == OMAP3430_REV_ES3_1_2) 284 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL; 285 286 omap_features |= OMAP3_HAS_SDRC; 287 288 /* 289 * am35x fixups: 290 * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as 291 * reserved and therefore return 0 when read. Unfortunately, 292 * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to 293 * mean that a feature is present even though it isn't so clear 294 * the incorrectly set feature bits. 295 */ 296 if (soc_is_am35xx()) 297 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP); 298 299 /* 300 * TODO: Get additional info (where applicable) 301 * e.g. Size of L2 cache. 302 */ 303 304 omap3_cpuinfo(); 305} 306 307void __init omap4xxx_check_features(void) 308{ 309 u32 si_type; 310 311 si_type = 312 (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03; 313 314 if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE) 315 omap_features = OMAP4_HAS_PERF_SILICON; 316} 317 318void __init ti81xx_check_features(void) 319{ 320 omap_features = OMAP3_HAS_NEON; 321 omap3_cpuinfo(); 322} 323 324void __init am33xx_check_features(void) 325{ 326 u32 status; 327 328 omap_features = OMAP3_HAS_NEON; 329 330 status = omap_ctrl_readl(AM33XX_DEV_FEATURE); 331 if (status & AM33XX_SGX_MASK) 332 omap_features |= OMAP3_HAS_SGX; 333 334 omap3_cpuinfo(); 335} 336 337void __init omap3xxx_check_revision(void) 338{ 339 const char *cpu_rev; 340 u32 cpuid, idcode; 341 u16 hawkeye; 342 u8 rev; 343 344 /* 345 * We cannot access revision registers on ES1.0. 346 * If the processor type is Cortex-A8 and the revision is 0x0 347 * it means its Cortex r0p0 which is 3430 ES1.0. 348 */ 349 cpuid = read_cpuid_id(); 350 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { 351 omap_revision = OMAP3430_REV_ES1_0; 352 cpu_rev = "1.0"; 353 return; 354 } 355 356 /* 357 * Detection for 34xx ES2.0 and above can be done with just 358 * hawkeye and rev. See TRM 1.5.2 Device Identification. 359 * Note that rev does not map directly to our defined processor 360 * revision numbers as ES1.0 uses value 0. 361 */ 362 idcode = read_tap_reg(OMAP_TAP_IDCODE); 363 hawkeye = (idcode >> 12) & 0xffff; 364 rev = (idcode >> 28) & 0xff; 365 366 switch (hawkeye) { 367 case 0xb7ae: 368 /* Handle 34xx/35xx devices */ 369 switch (rev) { 370 case 0: /* Take care of early samples */ 371 case 1: 372 omap_revision = OMAP3430_REV_ES2_0; 373 cpu_rev = "2.0"; 374 break; 375 case 2: 376 omap_revision = OMAP3430_REV_ES2_1; 377 cpu_rev = "2.1"; 378 break; 379 case 3: 380 omap_revision = OMAP3430_REV_ES3_0; 381 cpu_rev = "3.0"; 382 break; 383 case 4: 384 omap_revision = OMAP3430_REV_ES3_1; 385 cpu_rev = "3.1"; 386 break; 387 case 7: 388 /* FALLTHROUGH */ 389 default: 390 /* Use the latest known revision as default */ 391 omap_revision = OMAP3430_REV_ES3_1_2; 392 cpu_rev = "3.1.2"; 393 } 394 break; 395 case 0xb868: 396 /* 397 * Handle OMAP/AM 3505/3517 devices 398 * 399 * Set the device to be OMAP3517 here. Actual device 400 * is identified later based on the features. 401 */ 402 switch (rev) { 403 case 0: 404 omap_revision = AM35XX_REV_ES1_0; 405 cpu_rev = "1.0"; 406 break; 407 case 1: 408 /* FALLTHROUGH */ 409 default: 410 omap_revision = AM35XX_REV_ES1_1; 411 cpu_rev = "1.1"; 412 } 413 break; 414 case 0xb891: 415 /* Handle 36xx devices */ 416 417 switch(rev) { 418 case 0: /* Take care of early samples */ 419 omap_revision = OMAP3630_REV_ES1_0; 420 cpu_rev = "1.0"; 421 break; 422 case 1: 423 omap_revision = OMAP3630_REV_ES1_1; 424 cpu_rev = "1.1"; 425 break; 426 case 2: 427 /* FALLTHROUGH */ 428 default: 429 omap_revision = OMAP3630_REV_ES1_2; 430 cpu_rev = "1.2"; 431 } 432 break; 433 case 0xb81e: 434 switch (rev) { 435 case 0: 436 omap_revision = TI8168_REV_ES1_0; 437 cpu_rev = "1.0"; 438 break; 439 case 1: 440 omap_revision = TI8168_REV_ES1_1; 441 cpu_rev = "1.1"; 442 break; 443 case 2: 444 omap_revision = TI8168_REV_ES2_0; 445 cpu_rev = "2.0"; 446 break; 447 case 3: 448 /* FALLTHROUGH */ 449 default: 450 omap_revision = TI8168_REV_ES2_1; 451 cpu_rev = "2.1"; 452 } 453 break; 454 case 0xb944: 455 switch (rev) { 456 case 0: 457 omap_revision = AM335X_REV_ES1_0; 458 cpu_rev = "1.0"; 459 break; 460 case 1: 461 omap_revision = AM335X_REV_ES2_0; 462 cpu_rev = "2.0"; 463 break; 464 case 2: 465 /* FALLTHROUGH */ 466 default: 467 omap_revision = AM335X_REV_ES2_1; 468 cpu_rev = "2.1"; 469 break; 470 } 471 break; 472 case 0xb98c: 473 switch (rev) { 474 case 0: 475 omap_revision = AM437X_REV_ES1_0; 476 cpu_rev = "1.0"; 477 break; 478 case 1: 479 omap_revision = AM437X_REV_ES1_1; 480 cpu_rev = "1.1"; 481 break; 482 case 2: 483 /* FALLTHROUGH */ 484 default: 485 omap_revision = AM437X_REV_ES1_2; 486 cpu_rev = "1.2"; 487 break; 488 } 489 break; 490 case 0xb8f2: 491 switch (rev) { 492 case 0: 493 /* FALLTHROUGH */ 494 case 1: 495 omap_revision = TI8148_REV_ES1_0; 496 cpu_rev = "1.0"; 497 break; 498 case 2: 499 omap_revision = TI8148_REV_ES2_0; 500 cpu_rev = "2.0"; 501 break; 502 case 3: 503 /* FALLTHROUGH */ 504 default: 505 omap_revision = TI8148_REV_ES2_1; 506 cpu_rev = "2.1"; 507 break; 508 } 509 break; 510 default: 511 /* Unknown default to latest silicon rev as default */ 512 omap_revision = OMAP3630_REV_ES1_2; 513 cpu_rev = "1.2"; 514 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); 515 } 516 sprintf(soc_rev, "ES%s", cpu_rev); 517} 518 519void __init omap4xxx_check_revision(void) 520{ 521 u32 idcode; 522 u16 hawkeye; 523 u8 rev; 524 525 /* 526 * The IC rev detection is done with hawkeye and rev. 527 * Note that rev does not map directly to defined processor 528 * revision numbers as ES1.0 uses value 0. 529 */ 530 idcode = read_tap_reg(OMAP_TAP_IDCODE); 531 hawkeye = (idcode >> 12) & 0xffff; 532 rev = (idcode >> 28) & 0xf; 533 534 /* 535 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 536 * Use ARM register to detect the correct ES version 537 */ 538 if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { 539 idcode = read_cpuid_id(); 540 rev = (idcode & 0xf) - 1; 541 } 542 543 switch (hawkeye) { 544 case 0xb852: 545 switch (rev) { 546 case 0: 547 omap_revision = OMAP4430_REV_ES1_0; 548 break; 549 case 1: 550 default: 551 omap_revision = OMAP4430_REV_ES2_0; 552 } 553 break; 554 case 0xb95c: 555 switch (rev) { 556 case 3: 557 omap_revision = OMAP4430_REV_ES2_1; 558 break; 559 case 4: 560 omap_revision = OMAP4430_REV_ES2_2; 561 break; 562 case 6: 563 default: 564 omap_revision = OMAP4430_REV_ES2_3; 565 } 566 break; 567 case 0xb94e: 568 switch (rev) { 569 case 0: 570 omap_revision = OMAP4460_REV_ES1_0; 571 break; 572 case 2: 573 default: 574 omap_revision = OMAP4460_REV_ES1_1; 575 break; 576 } 577 break; 578 case 0xb975: 579 switch (rev) { 580 case 0: 581 default: 582 omap_revision = OMAP4470_REV_ES1_0; 583 break; 584 } 585 break; 586 default: 587 /* Unknown default to latest silicon rev as default */ 588 omap_revision = OMAP4430_REV_ES2_3; 589 } 590 591 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); 592 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, 593 (omap_rev() >> 8) & 0xf); 594 pr_info("%s %s\n", soc_name, soc_rev); 595} 596 597void __init omap5xxx_check_revision(void) 598{ 599 u32 idcode; 600 u16 hawkeye; 601 u8 rev; 602 603 idcode = read_tap_reg(OMAP_TAP_IDCODE); 604 hawkeye = (idcode >> 12) & 0xffff; 605 rev = (idcode >> 28) & 0xff; 606 switch (hawkeye) { 607 case 0xb942: 608 switch (rev) { 609 case 0: 610 /* No support for ES1.0 Test chip */ 611 BUG(); 612 case 1: 613 default: 614 omap_revision = OMAP5430_REV_ES2_0; 615 } 616 break; 617 618 case 0xb998: 619 switch (rev) { 620 case 0: 621 /* No support for ES1.0 Test chip */ 622 BUG(); 623 case 1: 624 default: 625 omap_revision = OMAP5432_REV_ES2_0; 626 } 627 break; 628 629 default: 630 /* Unknown default to latest silicon rev as default*/ 631 omap_revision = OMAP5430_REV_ES2_0; 632 } 633 634 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); 635 sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf); 636 637 pr_info("%s %s\n", soc_name, soc_rev); 638} 639 640void __init dra7xxx_check_revision(void) 641{ 642 u32 idcode; 643 u16 hawkeye; 644 u8 rev; 645 646 idcode = read_tap_reg(OMAP_TAP_IDCODE); 647 hawkeye = (idcode >> 12) & 0xffff; 648 rev = (idcode >> 28) & 0xff; 649 switch (hawkeye) { 650 case 0xb990: 651 switch (rev) { 652 case 0: 653 omap_revision = DRA752_REV_ES1_0; 654 break; 655 case 1: 656 default: 657 omap_revision = DRA752_REV_ES1_1; 658 } 659 break; 660 661 case 0xb9bc: 662 switch (rev) { 663 case 0: 664 omap_revision = DRA722_REV_ES1_0; 665 break; 666 default: 667 /* If we have no new revisions */ 668 omap_revision = DRA722_REV_ES1_0; 669 break; 670 } 671 break; 672 673 default: 674 /* Unknown default to latest silicon rev as default*/ 675 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n", 676 __func__, idcode, hawkeye, rev); 677 omap_revision = DRA752_REV_ES1_1; 678 } 679 680 sprintf(soc_name, "DRA%03x", omap_rev() >> 16); 681 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, 682 (omap_rev() >> 8) & 0xf); 683 684 pr_info("%s %s\n", soc_name, soc_rev); 685} 686 687/* 688 * Set up things for map_io and processor detection later on. Gets called 689 * pretty much first thing from board init. For multi-omap, this gets 690 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to 691 * detect the exact revision later on in omap2_detect_revision() once map_io 692 * is done. 693 */ 694void __init omap2_set_globals_tap(u32 class, void __iomem *tap) 695{ 696 omap_revision = class; 697 tap_base = tap; 698 699 /* XXX What is this intended to do? */ 700 if (cpu_is_omap34xx()) 701 tap_prod_id = 0x0210; 702 else 703 tap_prod_id = 0x0208; 704} 705 706#ifdef CONFIG_SOC_BUS 707 708static const char * const omap_types[] = { 709 [OMAP2_DEVICE_TYPE_TEST] = "TST", 710 [OMAP2_DEVICE_TYPE_EMU] = "EMU", 711 [OMAP2_DEVICE_TYPE_SEC] = "HS", 712 [OMAP2_DEVICE_TYPE_GP] = "GP", 713 [OMAP2_DEVICE_TYPE_BAD] = "BAD", 714}; 715 716static const char * __init omap_get_family(void) 717{ 718 if (cpu_is_omap24xx()) 719 return kasprintf(GFP_KERNEL, "OMAP2"); 720 else if (cpu_is_omap34xx()) 721 return kasprintf(GFP_KERNEL, "OMAP3"); 722 else if (cpu_is_omap44xx()) 723 return kasprintf(GFP_KERNEL, "OMAP4"); 724 else if (soc_is_omap54xx()) 725 return kasprintf(GFP_KERNEL, "OMAP5"); 726 else if (soc_is_am33xx() || soc_is_am335x()) 727 return kasprintf(GFP_KERNEL, "AM33xx"); 728 else if (soc_is_am43xx()) 729 return kasprintf(GFP_KERNEL, "AM43xx"); 730 else if (soc_is_dra7xx()) 731 return kasprintf(GFP_KERNEL, "DRA7"); 732 else 733 return kasprintf(GFP_KERNEL, "Unknown"); 734} 735 736static ssize_t omap_get_type(struct device *dev, 737 struct device_attribute *attr, 738 char *buf) 739{ 740 return sprintf(buf, "%s\n", omap_types[omap_type()]); 741} 742 743static struct device_attribute omap_soc_attr = 744 __ATTR(type, S_IRUGO, omap_get_type, NULL); 745 746void __init omap_soc_device_init(void) 747{ 748 struct device *parent; 749 struct soc_device *soc_dev; 750 struct soc_device_attribute *soc_dev_attr; 751 752 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 753 if (!soc_dev_attr) 754 return; 755 756 soc_dev_attr->machine = soc_name; 757 soc_dev_attr->family = omap_get_family(); 758 soc_dev_attr->revision = soc_rev; 759 760 soc_dev = soc_device_register(soc_dev_attr); 761 if (IS_ERR(soc_dev)) { 762 kfree(soc_dev_attr); 763 return; 764 } 765 766 parent = soc_device_to_device(soc_dev); 767 device_create_file(parent, &omap_soc_attr); 768} 769#endif /* CONFIG_SOC_BUS */ 770