1/*
2 *  linux/include/asm-arm/arch-pxa/balloon3.h
3 *
4 *  Authors:	Nick Bane and Wookey
5 *  Created:	Oct, 2005
6 *  Copyright:	Toby Churchill Ltd
7 *  Cribbed from mainstone.c, by Nicholas Pitre
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef ASM_ARCH_BALLOON3_H
15#define ASM_ARCH_BALLOON3_H
16
17#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
18
19enum balloon3_features {
20	BALLOON3_FEATURE_OHCI,
21	BALLOON3_FEATURE_MMC,
22	BALLOON3_FEATURE_CF,
23	BALLOON3_FEATURE_AUDIO,
24	BALLOON3_FEATURE_TOPPOLY,
25};
26
27#define BALLOON3_FPGA_PHYS	PXA_CS4_PHYS
28#define BALLOON3_FPGA_VIRT	IOMEM(0xf1000000)	/* as per balloon2 */
29#define BALLOON3_FPGA_LENGTH	0x01000000
30
31#define	BALLOON3_FPGA_SETnCLR		(0x1000)
32
33/* FPGA / CPLD registers for CF socket */
34#define	BALLOON3_CF_STATUS_REG		(BALLOON3_FPGA_VIRT + 0x00e00008)
35#define	BALLOON3_CF_CONTROL_REG		(BALLOON3_FPGA_VIRT + 0x00e00008)
36/* FPGA / CPLD version register */
37#define	BALLOON3_FPGA_VER		(BALLOON3_FPGA_VIRT + 0x00e0001c)
38/* FPGA / CPLD registers for NAND flash */
39#define	BALLOON3_NAND_BASE		(PXA_CS4_PHYS + 0x00e00000)
40#define	BALLOON3_NAND_IO_REG		(BALLOON3_FPGA_VIRT + 0x00e00000)
41#define	BALLOON3_NAND_CONTROL2_REG	(BALLOON3_FPGA_VIRT + 0x00e00010)
42#define	BALLOON3_NAND_STAT_REG		(BALLOON3_FPGA_VIRT + 0x00e00014)
43#define	BALLOON3_NAND_CONTROL_REG	(BALLOON3_FPGA_VIRT + 0x00e00014)
44
45/* fpga/cpld interrupt control register */
46#define BALLOON3_INT_CONTROL_REG	(BALLOON3_FPGA_VIRT + 0x00e0000C)
47#define BALLOON3_VERSION_REG		(BALLOON3_FPGA_VIRT + 0x00e0001c)
48
49#define BALLOON3_SAMOSA_ADDR_REG	(BALLOON3_FPGA_VIRT + 0x00c00000)
50#define BALLOON3_SAMOSA_DATA_REG	(BALLOON3_FPGA_VIRT + 0x00c00004)
51#define BALLOON3_SAMOSA_STATUS_REG	(BALLOON3_FPGA_VIRT + 0x00c0001c)
52
53/* CF Status Register bits (read-only) bits */
54#define BALLOON3_CF_nIRQ		(1 << 0)
55#define BALLOON3_CF_nSTSCHG_BVD1	(1 << 1)
56
57/* CF Control Set Register bits / CF Control Clear Register bits (write-only) */
58#define BALLOON3_CF_RESET		(1 << 0)
59#define BALLOON3_CF_ENABLE		(1 << 1)
60#define BALLOON3_CF_ADD_ENABLE		(1 << 2)
61
62/* CF Interrupt sources */
63#define BALLOON3_BP_CF_NRDY_IRQ		BALLOON3_IRQ(0)
64#define BALLOON3_BP_NSTSCHG_IRQ		BALLOON3_IRQ(1)
65
66/* NAND Control register */
67#define	BALLOON3_NAND_CONTROL_FLWP	(1 << 7)
68#define	BALLOON3_NAND_CONTROL_FLSE	(1 << 6)
69#define	BALLOON3_NAND_CONTROL_FLCE3	(1 << 5)
70#define	BALLOON3_NAND_CONTROL_FLCE2	(1 << 4)
71#define	BALLOON3_NAND_CONTROL_FLCE1	(1 << 3)
72#define	BALLOON3_NAND_CONTROL_FLCE0	(1 << 2)
73#define	BALLOON3_NAND_CONTROL_FLALE	(1 << 1)
74#define	BALLOON3_NAND_CONTROL_FLCLE	(1 << 0)
75
76/* NAND Status register */
77#define	BALLOON3_NAND_STAT_RNB		(1 << 0)
78
79/* NAND Control2 register */
80#define	BALLOON3_NAND_CONTROL2_16BIT	(1 << 0)
81
82/* GPIOs for irqs */
83#define BALLOON3_GPIO_AUX_NIRQ		(94)
84#define BALLOON3_GPIO_CODEC_IRQ		(95)
85
86/* Timer and Idle LED locations */
87#define BALLOON3_GPIO_LED_NAND		(9)
88#define BALLOON3_GPIO_LED_IDLE		(10)
89
90/* backlight control */
91#define BALLOON3_GPIO_RUN_BACKLIGHT	(99)
92
93#define BALLOON3_GPIO_S0_CD		(105)
94
95/* NAND */
96#define BALLOON3_GPIO_RUN_NAND		(102)
97
98/* PCF8574A Leds */
99#define	BALLOON3_PCF_GPIO_BASE		160
100#define	BALLOON3_PCF_GPIO_LED0		(BALLOON3_PCF_GPIO_BASE + 0)
101#define	BALLOON3_PCF_GPIO_LED1		(BALLOON3_PCF_GPIO_BASE + 1)
102#define	BALLOON3_PCF_GPIO_LED2		(BALLOON3_PCF_GPIO_BASE + 2)
103#define	BALLOON3_PCF_GPIO_LED3		(BALLOON3_PCF_GPIO_BASE + 3)
104#define	BALLOON3_PCF_GPIO_LED4		(BALLOON3_PCF_GPIO_BASE + 4)
105#define	BALLOON3_PCF_GPIO_LED5		(BALLOON3_PCF_GPIO_BASE + 5)
106#define	BALLOON3_PCF_GPIO_LED6		(BALLOON3_PCF_GPIO_BASE + 6)
107#define	BALLOON3_PCF_GPIO_LED7		(BALLOON3_PCF_GPIO_BASE + 7)
108
109/* FPGA Interrupt Mask/Acknowledge Register */
110#define BALLOON3_INT_S0_IRQ		(1 << 0)  /* PCMCIA 0 IRQ */
111#define BALLOON3_INT_S0_STSCHG		(1 << 1)  /* PCMCIA 0 status changed */
112
113/* CPLD (and FPGA) interface definitions */
114#define CPLD_LCD0_DATA_SET             0x00
115#define CPLD_LCD0_DATA_CLR             0x10
116#define CPLD_LCD0_COMMAND_SET          0x01
117#define CPLD_LCD0_COMMAND_CLR          0x11
118#define CPLD_LCD1_DATA_SET             0x02
119#define CPLD_LCD1_DATA_CLR             0x12
120#define CPLD_LCD1_COMMAND_SET          0x03
121#define CPLD_LCD1_COMMAND_CLR          0x13
122
123#define CPLD_MISC_SET                  0x07
124#define CPLD_MISC_CLR                  0x17
125#define CPLD_MISC_LOON_NRESET_BIT      0
126#define CPLD_MISC_LOON_UNSUSP_BIT      1
127#define CPLD_MISC_RUN_5V_BIT           2
128#define CPLD_MISC_CHG_D0_BIT           3
129#define CPLD_MISC_CHG_D1_BIT           4
130#define CPLD_MISC_DAC_NCS_BIT          5
131
132#define CPLD_LCD_SET                   0x08
133#define CPLD_LCD_CLR                   0x18
134#define CPLD_LCD_BACKLIGHT_EN_0_BIT    0
135#define CPLD_LCD_BACKLIGHT_EN_1_BIT    1
136#define CPLD_LCD_LED_RED_BIT           4
137#define CPLD_LCD_LED_GREEN_BIT         5
138#define CPLD_LCD_NRESET_BIT            7
139
140#define CPLD_LCD_RO_SET                0x09
141#define CPLD_LCD_RO_CLR                0x19
142#define CPLD_LCD_RO_LCD0_nWAIT_BIT     0
143#define CPLD_LCD_RO_LCD1_nWAIT_BIT     1
144
145#define CPLD_SERIAL_SET                0x0a
146#define CPLD_SERIAL_CLR                0x1a
147#define CPLD_SERIAL_GSM_RI_BIT         0
148#define CPLD_SERIAL_GSM_CTS_BIT        1
149#define CPLD_SERIAL_GSM_DTR_BIT        2
150#define CPLD_SERIAL_LPR_CTS_BIT        3
151#define CPLD_SERIAL_TC232_CTS_BIT      4
152#define CPLD_SERIAL_TC232_DSR_BIT      5
153
154#define CPLD_SROUTING_SET              0x0b
155#define CPLD_SROUTING_CLR              0x1b
156#define CPLD_SROUTING_MSP430_LPR       0
157#define CPLD_SROUTING_MSP430_TC232     1
158#define CPLD_SROUTING_MSP430_GSM       2
159#define CPLD_SROUTING_LOON_LPR         (0 << 4)
160#define CPLD_SROUTING_LOON_TC232       (1 << 4)
161#define CPLD_SROUTING_LOON_GSM         (2 << 4)
162
163#define CPLD_AROUTING_SET              0x0c
164#define CPLD_AROUTING_CLR              0x1c
165#define CPLD_AROUTING_MIC2PHONE_BIT    0
166#define CPLD_AROUTING_PHONE2INT_BIT    1
167#define CPLD_AROUTING_PHONE2EXT_BIT    2
168#define CPLD_AROUTING_LOONL2INT_BIT    3
169#define CPLD_AROUTING_LOONL2EXT_BIT    4
170#define CPLD_AROUTING_LOONR2PHONE_BIT  5
171#define CPLD_AROUTING_LOONR2INT_BIT    6
172#define CPLD_AROUTING_LOONR2EXT_BIT    7
173
174/* Balloon3 Interrupts */
175#define BALLOON3_IRQ(x)		(IRQ_BOARD_START + (x))
176
177#define BALLOON3_AUX_NIRQ	PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ)
178#define BALLOON3_CODEC_IRQ	PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ)
179
180#define BALLOON3_NR_IRQS	(IRQ_BOARD_START + 16)
181
182extern int balloon3_has(enum balloon3_features feature);
183
184#endif
185