1/* 2 * Copyright (C) 2012 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16#ifndef __ASM_PGTABLE_HWDEF_H 17#define __ASM_PGTABLE_HWDEF_H 18 19#define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3)) 20 21/* 22 * PMD_SHIFT determines the size a level 2 page table entry can map. 23 */ 24#if CONFIG_PGTABLE_LEVELS > 2 25#define PMD_SHIFT ((PAGE_SHIFT - 3) * 2 + 3) 26#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT) 27#define PMD_MASK (~(PMD_SIZE-1)) 28#define PTRS_PER_PMD PTRS_PER_PTE 29#endif 30 31/* 32 * PUD_SHIFT determines the size a level 1 page table entry can map. 33 */ 34#if CONFIG_PGTABLE_LEVELS > 3 35#define PUD_SHIFT ((PAGE_SHIFT - 3) * 3 + 3) 36#define PUD_SIZE (_AC(1, UL) << PUD_SHIFT) 37#define PUD_MASK (~(PUD_SIZE-1)) 38#define PTRS_PER_PUD PTRS_PER_PTE 39#endif 40 41/* 42 * PGDIR_SHIFT determines the size a top-level page table entry can map 43 * (depending on the configuration, this level can be 0, 1 or 2). 44 */ 45#define PGDIR_SHIFT ((PAGE_SHIFT - 3) * CONFIG_PGTABLE_LEVELS + 3) 46#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) 47#define PGDIR_MASK (~(PGDIR_SIZE-1)) 48#define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT)) 49 50/* 51 * Section address mask and size definitions. 52 */ 53#define SECTION_SHIFT PMD_SHIFT 54#define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT) 55#define SECTION_MASK (~(SECTION_SIZE-1)) 56 57/* 58 * Hardware page table definitions. 59 * 60 * Level 1 descriptor (PUD). 61 */ 62#define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0) 63#define PUD_TABLE_BIT (_AT(pgdval_t, 1) << 1) 64#define PUD_TYPE_MASK (_AT(pgdval_t, 3) << 0) 65#define PUD_TYPE_SECT (_AT(pgdval_t, 1) << 0) 66 67/* 68 * Level 2 descriptor (PMD). 69 */ 70#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 71#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 72#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 73#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 74#define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 75 76/* 77 * Section 78 */ 79#define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 80#define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 81#define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */ 82#define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 83#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 84#define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) 85#define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 86#define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) 87 88/* 89 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 90 */ 91#define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) 92#define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) 93 94/* 95 * Level 3 descriptor (PTE). 96 */ 97#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 98#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 99#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 100#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 101#define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 102#define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ 103#define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 104#define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 105#define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ 106#define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ 107#define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ 108 109/* 110 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 111 */ 112#define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) 113#define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) 114 115/* 116 * 2nd stage PTE definitions 117 */ 118#define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[2:1] */ 119#define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */ 120 121#define PMD_S2_RDONLY (_AT(pmdval_t, 1) << 6) /* HAP[2:1] */ 122#define PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */ 123 124/* 125 * Memory Attribute override for Stage-2 (MemAttr[3:0]) 126 */ 127#define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2) 128#define PTE_S2_MEMATTR_MASK (_AT(pteval_t, 0xf) << 2) 129 130/* 131 * EL2/HYP PTE/PMD definitions 132 */ 133#define PMD_HYP PMD_SECT_USER 134#define PTE_HYP PTE_USER 135 136/* 137 * Highest possible physical address supported. 138 */ 139#define PHYS_MASK_SHIFT (48) 140#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) 141 142/* 143 * TCR flags. 144 */ 145#define TCR_T0SZ_OFFSET 0 146#define TCR_T1SZ_OFFSET 16 147#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET) 148#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET) 149#define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x)) 150#define TCR_TxSZ_WIDTH 6 151#define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24)) 152#define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24)) 153#define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24)) 154#define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24)) 155#define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24)) 156#define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26)) 157#define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26)) 158#define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26)) 159#define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26)) 160#define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26)) 161#define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28)) 162#define TCR_TG0_4K (UL(0) << 14) 163#define TCR_TG0_64K (UL(1) << 14) 164#define TCR_TG0_16K (UL(2) << 14) 165#define TCR_TG1_16K (UL(1) << 30) 166#define TCR_TG1_4K (UL(2) << 30) 167#define TCR_TG1_64K (UL(3) << 30) 168#define TCR_ASID16 (UL(1) << 36) 169#define TCR_TBI0 (UL(1) << 37) 170 171#endif 172