1/* 2 * Copyright 2005-2010 Analog Devices Inc. 3 * 4 * Licensed under the GPL-2 or later 5 */ 6 7#ifndef _CDEF_BF532_H 8#define _CDEF_BF532_H 9 10/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ 11#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 12#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 13#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 14#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 15#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) 16#define bfin_read_CHIPID() bfin_read32(CHIPID) 17#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 18#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) 19#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 20 21/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ 22#define bfin_read_SWRST() bfin_read16(SWRST) 23#define bfin_write_SWRST(val) bfin_write16(SWRST,val) 24#define bfin_read_SYSCR() bfin_read16(SYSCR) 25#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) 26#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) 27#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) 28#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) 29#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) 30#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) 31#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) 32#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) 33#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val) 34#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) 35#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val) 36#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) 37#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val) 38#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) 39#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val) 40 41/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */ 42#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) 43#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val) 44#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) 45#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val) 46#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) 47#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val) 48 49/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */ 50#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) 51#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val) 52#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) 53#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val) 54#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) 55#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val) 56#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) 57#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val) 58#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) 59#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val) 60#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) 61#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val) 62#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) 63#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) 64 65/* DMA Traffic controls */ 66#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) 67#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val) 68#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) 69#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val) 70 71/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ 72#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) 73#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val) 74#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C) 75#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val) 76#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S) 77#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val) 78#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C) 79#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val) 80#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S) 81#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val) 82#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR) 83#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val) 84#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE) 85#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val) 86#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH) 87#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val) 88#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN) 89#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val) 90#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D) 91#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val) 92#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T) 93#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val) 94#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D) 95#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val) 96#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) 97#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) 98 99#if ANOMALY_05000311 100/* Keep at the CPP expansion to avoid circular header dependency loops */ 101#define BFIN_WRITE_FIO_FLAG(name, val) \ 102 do { \ 103 unsigned long __flags; \ 104 __flags = hard_local_irq_save(); \ 105 bfin_write16(FIO_FLAG_##name, val); \ 106 bfin_read_CHIPID(); \ 107 hard_local_irq_restore(__flags); \ 108 } while (0) 109#define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val) 110#define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val) 111#define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val) 112#define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val) 113 114#define BFIN_READ_FIO_FLAG(name) \ 115 ({ \ 116 unsigned long __flags; \ 117 u16 __ret; \ 118 __flags = hard_local_irq_save(); \ 119 __ret = bfin_read16(FIO_FLAG_##name); \ 120 bfin_read_CHIPID(); \ 121 hard_local_irq_restore(__flags); \ 122 __ret; \ 123 }) 124#define bfin_read_FIO_FLAG_D() BFIN_READ_FIO_FLAG(D) 125#define bfin_read_FIO_FLAG_C() BFIN_READ_FIO_FLAG(C) 126#define bfin_read_FIO_FLAG_S() BFIN_READ_FIO_FLAG(S) 127#define bfin_read_FIO_FLAG_T() BFIN_READ_FIO_FLAG(T) 128 129#else 130#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) 131#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) 132#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) 133#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) 134#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) 135#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) 136#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) 137#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) 138#endif 139 140/* DMA Controller */ 141#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) 142#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) 143#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) 144#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val) 145#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) 146#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val) 147#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) 148#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val) 149#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) 150#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val) 151#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) 152#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val) 153#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) 154#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val) 155#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) 156#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val) 157#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) 158#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val) 159#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) 160#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val) 161#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) 162#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val) 163#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) 164#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val) 165#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) 166#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val) 167 168#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) 169#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val) 170#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) 171#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val) 172#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) 173#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val) 174#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) 175#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val) 176#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) 177#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val) 178#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) 179#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val) 180#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) 181#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val) 182#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) 183#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val) 184#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) 185#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val) 186#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) 187#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val) 188#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) 189#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val) 190#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) 191#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val) 192#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) 193#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val) 194 195#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) 196#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val) 197#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) 198#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val) 199#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) 200#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val) 201#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) 202#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val) 203#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) 204#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val) 205#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) 206#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val) 207#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) 208#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val) 209#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) 210#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val) 211#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) 212#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val) 213#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) 214#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val) 215#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) 216#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val) 217#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) 218#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val) 219#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) 220#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val) 221 222#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) 223#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val) 224#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) 225#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val) 226#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) 227#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val) 228#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) 229#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val) 230#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) 231#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val) 232#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) 233#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val) 234#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) 235#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val) 236#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) 237#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val) 238#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) 239#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val) 240#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) 241#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val) 242#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) 243#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val) 244#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) 245#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val) 246#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) 247#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val) 248 249#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) 250#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val) 251#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) 252#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val) 253#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) 254#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val) 255#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) 256#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val) 257#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) 258#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val) 259#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) 260#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val) 261#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) 262#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val) 263#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) 264#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val) 265#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) 266#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val) 267#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) 268#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val) 269#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) 270#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val) 271#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) 272#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val) 273#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) 274#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val) 275 276#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) 277#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val) 278#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) 279#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val) 280#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) 281#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val) 282#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) 283#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val) 284#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 285#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val) 286#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) 287#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val) 288#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) 289#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val) 290#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) 291#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val) 292#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) 293#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val) 294#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) 295#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val) 296#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) 297#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val) 298#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) 299#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val) 300#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) 301#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val) 302 303#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) 304#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val) 305#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) 306#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val) 307#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) 308#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val) 309#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) 310#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val) 311#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) 312#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val) 313#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) 314#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val) 315#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) 316#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val) 317#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) 318#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val) 319#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) 320#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val) 321#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) 322#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val) 323#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) 324#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val) 325#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) 326#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val) 327#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) 328#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val) 329 330#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) 331#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val) 332#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) 333#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val) 334#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) 335#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val) 336#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) 337#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val) 338#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) 339#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val) 340#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) 341#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val) 342#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) 343#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val) 344#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) 345#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val) 346#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) 347#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val) 348#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) 349#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val) 350#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) 351#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val) 352#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) 353#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val) 354#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) 355#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val) 356 357#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) 358#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val) 359#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) 360#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val) 361#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) 362#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val) 363#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) 364#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val) 365#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) 366#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val) 367#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) 368#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val) 369#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) 370#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val) 371#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) 372#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val) 373#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) 374#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val) 375#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) 376#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val) 377#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) 378#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val) 379#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) 380#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val) 381#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) 382#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val) 383 384#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) 385#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val) 386#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) 387#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val) 388#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) 389#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val) 390#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) 391#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val) 392#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) 393#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val) 394#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) 395#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val) 396#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) 397#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val) 398#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) 399#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val) 400#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) 401#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val) 402#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) 403#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val) 404#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) 405#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val) 406#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) 407#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val) 408#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) 409#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val) 410 411#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) 412#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val) 413#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) 414#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val) 415#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) 416#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val) 417#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) 418#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val) 419#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) 420#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val) 421#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) 422#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val) 423#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) 424#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val) 425#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) 426#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val) 427#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) 428#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val) 429#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) 430#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val) 431#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) 432#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val) 433#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) 434#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val) 435#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) 436#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val) 437 438#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) 439#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val) 440#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) 441#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val) 442#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) 443#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val) 444#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) 445#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val) 446#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) 447#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val) 448#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) 449#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val) 450#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) 451#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val) 452#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) 453#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val) 454#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) 455#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val) 456#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) 457#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val) 458#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) 459#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val) 460#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) 461#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val) 462#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) 463#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val) 464 465/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */ 466#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) 467#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val) 468#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) 469#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val) 470#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) 471#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val) 472 473/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */ 474#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) 475#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val) 476#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) 477#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val) 478#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) 479#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) 480#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) 481#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val) 482 483/* UART Controller */ 484#define bfin_read_UART_THR() bfin_read16(UART_THR) 485#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val) 486#define bfin_read_UART_RBR() bfin_read16(UART_RBR) 487#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val) 488#define bfin_read_UART_DLL() bfin_read16(UART_DLL) 489#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val) 490#define bfin_read_UART_IER() bfin_read16(UART_IER) 491#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val) 492#define bfin_read_UART_DLH() bfin_read16(UART_DLH) 493#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val) 494#define bfin_read_UART_IIR() bfin_read16(UART_IIR) 495#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val) 496#define bfin_read_UART_LCR() bfin_read16(UART_LCR) 497#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val) 498#define bfin_read_UART_MCR() bfin_read16(UART_MCR) 499#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val) 500#define bfin_read_UART_LSR() bfin_read16(UART_LSR) 501#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val) 502/* 503#define UART_MSR 504*/ 505#define bfin_read_UART_SCR() bfin_read16(UART_SCR) 506#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val) 507#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) 508#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val) 509 510/* SPI Controller */ 511#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) 512#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val) 513#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) 514#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val) 515#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) 516#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val) 517#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) 518#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val) 519#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) 520#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val) 521#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) 522#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val) 523#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) 524#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val) 525 526/* TIMER 0, 1, 2 Registers */ 527#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) 528#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val) 529#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) 530#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val) 531#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) 532#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val) 533#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) 534#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val) 535 536#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) 537#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val) 538#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) 539#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val) 540#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) 541#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val) 542#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) 543#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val) 544 545#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) 546#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val) 547#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) 548#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val) 549#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) 550#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val) 551#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) 552#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val) 553 554#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) 555#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val) 556#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) 557#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val) 558#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS) 559#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val) 560 561/* SPORT0 Controller */ 562#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) 563#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val) 564#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) 565#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val) 566#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) 567#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val) 568#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) 569#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val) 570#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) 571#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val) 572#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) 573#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val) 574#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) 575#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val) 576#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) 577#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val) 578#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) 579#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val) 580#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) 581#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val) 582#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) 583#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val) 584#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) 585#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val) 586#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) 587#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val) 588#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) 589#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val) 590#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) 591#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val) 592#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) 593#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val) 594#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) 595#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val) 596#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) 597#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val) 598#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) 599#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val) 600#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) 601#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val) 602#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) 603#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val) 604#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) 605#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val) 606#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) 607#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val) 608#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) 609#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val) 610#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) 611#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val) 612#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) 613#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val) 614 615/* SPORT1 Controller */ 616#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) 617#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val) 618#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) 619#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val) 620#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) 621#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val) 622#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) 623#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val) 624#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) 625#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val) 626#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) 627#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val) 628#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) 629#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val) 630#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) 631#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val) 632#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) 633#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val) 634#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) 635#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val) 636#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) 637#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val) 638#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) 639#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val) 640#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) 641#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val) 642#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) 643#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val) 644#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) 645#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val) 646#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) 647#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val) 648#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) 649#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val) 650#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) 651#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val) 652#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) 653#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val) 654#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) 655#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val) 656#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) 657#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val) 658#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) 659#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val) 660#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) 661#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val) 662#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) 663#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val) 664#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) 665#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val) 666#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) 667#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val) 668 669/* Parallel Peripheral Interface (PPI) */ 670#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) 671#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val) 672#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) 673#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val) 674#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS() 675#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) 676#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val) 677#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) 678#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val) 679#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) 680#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) 681 682#endif /* _CDEF_BF532_H */ 683