1/*
2 * DO NOT EDIT THIS FILE
3 * This file is under version control at
4 *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE
7 *
8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the Clear BSD license.
10 */
11
12/* This file should be up to date with:
13 *  - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
14 *  - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
15 */
16
17#ifndef _MACH_ANOMALY_H_
18#define _MACH_ANOMALY_H_
19
20/* We do not support old silicon - sorry */
21#if __SILICON_REVISION__ < 4
22# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
23#endif
24
25#if defined(__ADSPBF538__)
26# define ANOMALY_BF538 1
27#else
28# define ANOMALY_BF538 0
29#endif
30#if defined(__ADSPBF539__)
31# define ANOMALY_BF539 1
32#else
33# define ANOMALY_BF539 0
34#endif
35
36/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
37#define ANOMALY_05000074 (1)
38/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
39#define ANOMALY_05000119 (1)
40/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
41#define ANOMALY_05000122 (1)
42/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
43#define ANOMALY_05000166 (1)
44/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
45#define ANOMALY_05000179 (1)
46/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
47#define ANOMALY_05000180 (1)
48/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
49#define ANOMALY_05000193 (1)
50/* Current DMA Address Shows Wrong Value During Carry Fix */
51#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
52/* NMI Event at Boot Time Results in Unpredictable State */
53#define ANOMALY_05000219 (1)
54/* SPI Slave Boot Mode Modifies Registers from Reset Value */
55#define ANOMALY_05000229 (1)
56/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
57#define ANOMALY_05000233 (1)
58/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
59#define ANOMALY_05000245 (1)
60/* Maximum External Clock Speed for Timers */
61#define ANOMALY_05000253 (1)
62/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
63#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
64/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
65#define ANOMALY_05000272 (ANOMALY_BF538)
66/* Writes to Synchronous SDRAM Memory May Be Lost */
67#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
68/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
69#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
70/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
71#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
72/* False Hardware Error when ISR Context Is Not Restored */
73#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
74/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
75#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
76/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
77#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
78/* SPORTs May Receive Bad Data If FIFOs Fill Up */
79#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
80/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
81#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
82/* Hibernate Leakage Current Is Higher Than Specified */
83#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
84/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
85#define ANOMALY_05000294 (1)
86/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
87#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
88/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
89#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
90/* SCKELOW Bit Does Not Maintain State Through Hibernate */
91#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
92/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
93#define ANOMALY_05000310 (1)
94/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
95#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
96/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
97#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
98/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
99#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
100/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
101#define ANOMALY_05000317 (__SILICON_REVISION__ < 4)	/* XXX: Same as 05000318 */
102/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
103#define ANOMALY_05000318 (__SILICON_REVISION__ < 4)	/* XXX: Same as 05000317 */
104/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
105#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
106/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
107#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
108/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
109#define ANOMALY_05000366 (1)
110/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
111#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
112/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
113#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
114/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
115#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
116/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
117#define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
118/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
119#define ANOMALY_05000403 (1)
120/* Speculative Fetches Can Cause Undesired External FIFO Operations */
121#define ANOMALY_05000416 (1)
122/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
123#define ANOMALY_05000425 (1)
124/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
125#define ANOMALY_05000426 (1)
126/* Specific GPIO Pins May Change State when Entering Hibernate */
127#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
128/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
129#define ANOMALY_05000443 (1)
130/* False Hardware Error when RETI Points to Invalid Memory */
131#define ANOMALY_05000461 (1)
132/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
133#define ANOMALY_05000462 (1)
134/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
135#define ANOMALY_05000473 (1)
136/* Possible Lockup Condition when Modifying PLL from External Memory */
137#define ANOMALY_05000475 (1)
138/* TESTSET Instruction Cannot Be Interrupted */
139#define ANOMALY_05000477 (1)
140/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
141#define ANOMALY_05000481 (1)
142/* PLL May Latch Incorrect Values Coming Out of Reset */
143#define ANOMALY_05000489 (1)
144/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
145#define ANOMALY_05000491 (1)
146/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
147#define ANOMALY_05000494 (1)
148/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
149#define ANOMALY_05000501 (1)
150
151/*
152 * These anomalies have been "phased" out of analog.com anomaly sheets and are
153 * here to show running on older silicon just isn't feasible.
154 */
155
156/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
157#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
158/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
159#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
160
161/* Anomalies that don't exist on this proc */
162#define ANOMALY_05000099 (0)
163#define ANOMALY_05000120 (0)
164#define ANOMALY_05000125 (0)
165#define ANOMALY_05000149 (0)
166#define ANOMALY_05000158 (0)
167#define ANOMALY_05000171 (0)
168#define ANOMALY_05000182 (0)
169#define ANOMALY_05000189 (0)
170#define ANOMALY_05000198 (0)
171#define ANOMALY_05000202 (0)
172#define ANOMALY_05000215 (0)
173#define ANOMALY_05000220 (0)
174#define ANOMALY_05000227 (0)
175#define ANOMALY_05000230 (0)
176#define ANOMALY_05000231 (0)
177#define ANOMALY_05000234 (0)
178#define ANOMALY_05000242 (0)
179#define ANOMALY_05000248 (0)
180#define ANOMALY_05000250 (0)
181#define ANOMALY_05000254 (0)
182#define ANOMALY_05000257 (0)
183#define ANOMALY_05000263 (0)
184#define ANOMALY_05000266 (0)
185#define ANOMALY_05000274 (0)
186#define ANOMALY_05000287 (0)
187#define ANOMALY_05000305 (0)
188#define ANOMALY_05000311 (0)
189#define ANOMALY_05000323 (0)
190#define ANOMALY_05000353 (1)
191#define ANOMALY_05000362 (1)
192#define ANOMALY_05000363 (0)
193#define ANOMALY_05000364 (0)
194#define ANOMALY_05000380 (0)
195#define ANOMALY_05000383 (0)
196#define ANOMALY_05000386 (1)
197#define ANOMALY_05000389 (0)
198#define ANOMALY_05000400 (0)
199#define ANOMALY_05000412 (0)
200#define ANOMALY_05000430 (0)
201#define ANOMALY_05000432 (0)
202#define ANOMALY_05000435 (0)
203#define ANOMALY_05000440 (0)
204#define ANOMALY_05000447 (0)
205#define ANOMALY_05000448 (0)
206#define ANOMALY_05000456 (0)
207#define ANOMALY_05000450 (0)
208#define ANOMALY_05000465 (0)
209#define ANOMALY_05000467 (0)
210#define ANOMALY_05000474 (0)
211#define ANOMALY_05000480 (0)
212#define ANOMALY_05000485 (0)
213#define ANOMALY_16000030 (0)
214
215#endif
216