1#ifndef BCM63XX_CPU_H_ 2#define BCM63XX_CPU_H_ 3 4#include <linux/types.h> 5#include <linux/init.h> 6 7/* 8 * Macro to fetch bcm63xx cpu id and revision, should be optimized at 9 * compile time if only one CPU support is enabled (idea stolen from 10 * arm mach-types) 11 */ 12#define BCM3368_CPU_ID 0x3368 13#define BCM6328_CPU_ID 0x6328 14#define BCM6338_CPU_ID 0x6338 15#define BCM6345_CPU_ID 0x6345 16#define BCM6348_CPU_ID 0x6348 17#define BCM6358_CPU_ID 0x6358 18#define BCM6362_CPU_ID 0x6362 19#define BCM6368_CPU_ID 0x6368 20 21void __init bcm63xx_cpu_init(void); 22u8 bcm63xx_get_cpu_rev(void); 23unsigned int bcm63xx_get_cpu_freq(void); 24 25static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id) 26{ 27 switch (cpu_id) { 28#ifdef CONFIG_BCM63XX_CPU_3368 29 case BCM3368_CPU_ID: 30#endif 31 32#ifdef CONFIG_BCM63XX_CPU_6328 33 case BCM6328_CPU_ID: 34#endif 35 36#ifdef CONFIG_BCM63XX_CPU_6338 37 case BCM6338_CPU_ID: 38#endif 39 40#ifdef CONFIG_BCM63XX_CPU_6345 41 case BCM6345_CPU_ID: 42#endif 43 44#ifdef CONFIG_BCM63XX_CPU_6348 45 case BCM6348_CPU_ID: 46#endif 47 48#ifdef CONFIG_BCM63XX_CPU_6358 49 case BCM6358_CPU_ID: 50#endif 51 52#ifdef CONFIG_BCM63XX_CPU_6362 53 case BCM6362_CPU_ID: 54#endif 55 56#ifdef CONFIG_BCM63XX_CPU_6368 57 case BCM6368_CPU_ID: 58#endif 59 break; 60 default: 61 unreachable(); 62 } 63 64 return cpu_id; 65} 66 67extern u16 bcm63xx_cpu_id; 68 69static inline u16 __pure bcm63xx_get_cpu_id(void) 70{ 71 const u16 cpu_id = bcm63xx_cpu_id; 72 73 return __bcm63xx_get_cpu_id(cpu_id); 74} 75 76#define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID) 77#define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID) 78#define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) 79#define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) 80#define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID) 81#define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) 82#define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) 83#define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) 84 85/* 86 * While registers sets are (mostly) the same across 63xx CPU, base 87 * address of these sets do change. 88 */ 89enum bcm63xx_regs_set { 90 RSET_DSL_LMEM = 0, 91 RSET_PERF, 92 RSET_TIMER, 93 RSET_WDT, 94 RSET_UART0, 95 RSET_UART1, 96 RSET_GPIO, 97 RSET_SPI, 98 RSET_HSSPI, 99 RSET_UDC0, 100 RSET_OHCI0, 101 RSET_OHCI_PRIV, 102 RSET_USBH_PRIV, 103 RSET_USBD, 104 RSET_USBDMA, 105 RSET_MPI, 106 RSET_PCMCIA, 107 RSET_PCIE, 108 RSET_DSL, 109 RSET_ENET0, 110 RSET_ENET1, 111 RSET_ENETDMA, 112 RSET_ENETDMAC, 113 RSET_ENETDMAS, 114 RSET_ENETSW, 115 RSET_EHCI0, 116 RSET_SDRAM, 117 RSET_MEMC, 118 RSET_DDR, 119 RSET_M2M, 120 RSET_ATM, 121 RSET_XTM, 122 RSET_XTMDMA, 123 RSET_XTMDMAC, 124 RSET_XTMDMAS, 125 RSET_PCM, 126 RSET_PCMDMA, 127 RSET_PCMDMAC, 128 RSET_PCMDMAS, 129 RSET_RNG, 130 RSET_MISC 131}; 132 133#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 134#define RSET_DSL_SIZE 4096 135#define RSET_WDT_SIZE 12 136#define BCM_6338_RSET_SPI_SIZE 64 137#define BCM_6348_RSET_SPI_SIZE 64 138#define BCM_6358_RSET_SPI_SIZE 1804 139#define BCM_6368_RSET_SPI_SIZE 1804 140#define RSET_ENET_SIZE 2048 141#define RSET_ENETDMA_SIZE 256 142#define RSET_6345_ENETDMA_SIZE 64 143#define RSET_ENETDMAC_SIZE(chans) (16 * (chans)) 144#define RSET_ENETDMAS_SIZE(chans) (16 * (chans)) 145#define RSET_ENETSW_SIZE 65536 146#define RSET_UART_SIZE 24 147#define RSET_HSSPI_SIZE 1536 148#define RSET_UDC_SIZE 256 149#define RSET_OHCI_SIZE 256 150#define RSET_EHCI_SIZE 256 151#define RSET_USBD_SIZE 256 152#define RSET_USBDMA_SIZE 1280 153#define RSET_PCMCIA_SIZE 12 154#define RSET_M2M_SIZE 256 155#define RSET_ATM_SIZE 4096 156#define RSET_XTM_SIZE 10240 157#define RSET_XTMDMA_SIZE 256 158#define RSET_XTMDMAC_SIZE(chans) (16 * (chans)) 159#define RSET_XTMDMAS_SIZE(chans) (16 * (chans)) 160#define RSET_RNG_SIZE 20 161 162/* 163 * 3368 register sets base address 164 */ 165#define BCM_3368_DSL_LMEM_BASE (0xdeadbeef) 166#define BCM_3368_PERF_BASE (0xfff8c000) 167#define BCM_3368_TIMER_BASE (0xfff8c040) 168#define BCM_3368_WDT_BASE (0xfff8c080) 169#define BCM_3368_UART0_BASE (0xfff8c100) 170#define BCM_3368_UART1_BASE (0xfff8c120) 171#define BCM_3368_GPIO_BASE (0xfff8c080) 172#define BCM_3368_SPI_BASE (0xfff8c800) 173#define BCM_3368_HSSPI_BASE (0xdeadbeef) 174#define BCM_3368_UDC0_BASE (0xdeadbeef) 175#define BCM_3368_USBDMA_BASE (0xdeadbeef) 176#define BCM_3368_OHCI0_BASE (0xdeadbeef) 177#define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef) 178#define BCM_3368_USBH_PRIV_BASE (0xdeadbeef) 179#define BCM_3368_USBD_BASE (0xdeadbeef) 180#define BCM_3368_MPI_BASE (0xfff80000) 181#define BCM_3368_PCMCIA_BASE (0xfff80054) 182#define BCM_3368_PCIE_BASE (0xdeadbeef) 183#define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef) 184#define BCM_3368_DSL_BASE (0xdeadbeef) 185#define BCM_3368_UBUS_BASE (0xdeadbeef) 186#define BCM_3368_ENET0_BASE (0xfff98000) 187#define BCM_3368_ENET1_BASE (0xfff98800) 188#define BCM_3368_ENETDMA_BASE (0xfff99800) 189#define BCM_3368_ENETDMAC_BASE (0xfff99900) 190#define BCM_3368_ENETDMAS_BASE (0xfff99a00) 191#define BCM_3368_ENETSW_BASE (0xdeadbeef) 192#define BCM_3368_EHCI0_BASE (0xdeadbeef) 193#define BCM_3368_SDRAM_BASE (0xdeadbeef) 194#define BCM_3368_MEMC_BASE (0xfff84000) 195#define BCM_3368_DDR_BASE (0xdeadbeef) 196#define BCM_3368_M2M_BASE (0xdeadbeef) 197#define BCM_3368_ATM_BASE (0xdeadbeef) 198#define BCM_3368_XTM_BASE (0xdeadbeef) 199#define BCM_3368_XTMDMA_BASE (0xdeadbeef) 200#define BCM_3368_XTMDMAC_BASE (0xdeadbeef) 201#define BCM_3368_XTMDMAS_BASE (0xdeadbeef) 202#define BCM_3368_PCM_BASE (0xfff9c200) 203#define BCM_3368_PCMDMA_BASE (0xdeadbeef) 204#define BCM_3368_PCMDMAC_BASE (0xdeadbeef) 205#define BCM_3368_PCMDMAS_BASE (0xdeadbeef) 206#define BCM_3368_RNG_BASE (0xdeadbeef) 207#define BCM_3368_MISC_BASE (0xdeadbeef) 208 209/* 210 * 6328 register sets base address 211 */ 212#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) 213#define BCM_6328_PERF_BASE (0xb0000000) 214#define BCM_6328_TIMER_BASE (0xb0000040) 215#define BCM_6328_WDT_BASE (0xb000005c) 216#define BCM_6328_UART0_BASE (0xb0000100) 217#define BCM_6328_UART1_BASE (0xb0000120) 218#define BCM_6328_GPIO_BASE (0xb0000080) 219#define BCM_6328_SPI_BASE (0xdeadbeef) 220#define BCM_6328_HSSPI_BASE (0xb0001000) 221#define BCM_6328_UDC0_BASE (0xdeadbeef) 222#define BCM_6328_USBDMA_BASE (0xb000c000) 223#define BCM_6328_OHCI0_BASE (0xb0002600) 224#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef) 225#define BCM_6328_USBH_PRIV_BASE (0xb0002700) 226#define BCM_6328_USBD_BASE (0xb0002400) 227#define BCM_6328_MPI_BASE (0xdeadbeef) 228#define BCM_6328_PCMCIA_BASE (0xdeadbeef) 229#define BCM_6328_PCIE_BASE (0xb0e40000) 230#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef) 231#define BCM_6328_DSL_BASE (0xb0001900) 232#define BCM_6328_UBUS_BASE (0xdeadbeef) 233#define BCM_6328_ENET0_BASE (0xdeadbeef) 234#define BCM_6328_ENET1_BASE (0xdeadbeef) 235#define BCM_6328_ENETDMA_BASE (0xb000d800) 236#define BCM_6328_ENETDMAC_BASE (0xb000da00) 237#define BCM_6328_ENETDMAS_BASE (0xb000dc00) 238#define BCM_6328_ENETSW_BASE (0xb0e00000) 239#define BCM_6328_EHCI0_BASE (0xb0002500) 240#define BCM_6328_SDRAM_BASE (0xdeadbeef) 241#define BCM_6328_MEMC_BASE (0xdeadbeef) 242#define BCM_6328_DDR_BASE (0xb0003000) 243#define BCM_6328_M2M_BASE (0xdeadbeef) 244#define BCM_6328_ATM_BASE (0xdeadbeef) 245#define BCM_6328_XTM_BASE (0xdeadbeef) 246#define BCM_6328_XTMDMA_BASE (0xb000b800) 247#define BCM_6328_XTMDMAC_BASE (0xdeadbeef) 248#define BCM_6328_XTMDMAS_BASE (0xdeadbeef) 249#define BCM_6328_PCM_BASE (0xb000a800) 250#define BCM_6328_PCMDMA_BASE (0xdeadbeef) 251#define BCM_6328_PCMDMAC_BASE (0xdeadbeef) 252#define BCM_6328_PCMDMAS_BASE (0xdeadbeef) 253#define BCM_6328_RNG_BASE (0xdeadbeef) 254#define BCM_6328_MISC_BASE (0xb0001800) 255#define BCM_6328_OTP_BASE (0xb0000600) 256 257/* 258 * 6338 register sets base address 259 */ 260#define BCM_6338_DSL_LMEM_BASE (0xfff00000) 261#define BCM_6338_PERF_BASE (0xfffe0000) 262#define BCM_6338_BB_BASE (0xfffe0100) 263#define BCM_6338_TIMER_BASE (0xfffe0200) 264#define BCM_6338_WDT_BASE (0xfffe021c) 265#define BCM_6338_UART0_BASE (0xfffe0300) 266#define BCM_6338_UART1_BASE (0xdeadbeef) 267#define BCM_6338_GPIO_BASE (0xfffe0400) 268#define BCM_6338_SPI_BASE (0xfffe0c00) 269#define BCM_6338_HSSPI_BASE (0xdeadbeef) 270#define BCM_6338_UDC0_BASE (0xdeadbeef) 271#define BCM_6338_USBDMA_BASE (0xfffe2400) 272#define BCM_6338_OHCI0_BASE (0xdeadbeef) 273#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) 274#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) 275#define BCM_6338_USBD_BASE (0xdeadbeef) 276#define BCM_6338_MPI_BASE (0xfffe3160) 277#define BCM_6338_PCMCIA_BASE (0xdeadbeef) 278#define BCM_6338_PCIE_BASE (0xdeadbeef) 279#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 280#define BCM_6338_DSL_BASE (0xfffe1000) 281#define BCM_6338_UBUS_BASE (0xdeadbeef) 282#define BCM_6338_ENET0_BASE (0xfffe2800) 283#define BCM_6338_ENET1_BASE (0xdeadbeef) 284#define BCM_6338_ENETDMA_BASE (0xfffe2400) 285#define BCM_6338_ENETDMAC_BASE (0xfffe2500) 286#define BCM_6338_ENETDMAS_BASE (0xfffe2600) 287#define BCM_6338_ENETSW_BASE (0xdeadbeef) 288#define BCM_6338_EHCI0_BASE (0xdeadbeef) 289#define BCM_6338_SDRAM_BASE (0xfffe3100) 290#define BCM_6338_MEMC_BASE (0xdeadbeef) 291#define BCM_6338_DDR_BASE (0xdeadbeef) 292#define BCM_6338_M2M_BASE (0xdeadbeef) 293#define BCM_6338_ATM_BASE (0xfffe2000) 294#define BCM_6338_XTM_BASE (0xdeadbeef) 295#define BCM_6338_XTMDMA_BASE (0xdeadbeef) 296#define BCM_6338_XTMDMAC_BASE (0xdeadbeef) 297#define BCM_6338_XTMDMAS_BASE (0xdeadbeef) 298#define BCM_6338_PCM_BASE (0xdeadbeef) 299#define BCM_6338_PCMDMA_BASE (0xdeadbeef) 300#define BCM_6338_PCMDMAC_BASE (0xdeadbeef) 301#define BCM_6338_PCMDMAS_BASE (0xdeadbeef) 302#define BCM_6338_RNG_BASE (0xdeadbeef) 303#define BCM_6338_MISC_BASE (0xdeadbeef) 304 305/* 306 * 6345 register sets base address 307 */ 308#define BCM_6345_DSL_LMEM_BASE (0xfff00000) 309#define BCM_6345_PERF_BASE (0xfffe0000) 310#define BCM_6345_BB_BASE (0xfffe0100) 311#define BCM_6345_TIMER_BASE (0xfffe0200) 312#define BCM_6345_WDT_BASE (0xfffe021c) 313#define BCM_6345_UART0_BASE (0xfffe0300) 314#define BCM_6345_UART1_BASE (0xdeadbeef) 315#define BCM_6345_GPIO_BASE (0xfffe0400) 316#define BCM_6345_SPI_BASE (0xdeadbeef) 317#define BCM_6345_HSSPI_BASE (0xdeadbeef) 318#define BCM_6345_UDC0_BASE (0xdeadbeef) 319#define BCM_6345_USBDMA_BASE (0xfffe2800) 320#define BCM_6345_ENET0_BASE (0xfffe1800) 321#define BCM_6345_ENETDMA_BASE (0xfffe2800) 322#define BCM_6345_ENETDMAC_BASE (0xfffe2840) 323#define BCM_6345_ENETDMAS_BASE (0xfffe2a00) 324#define BCM_6345_ENETSW_BASE (0xdeadbeef) 325#define BCM_6345_PCMCIA_BASE (0xfffe2028) 326#define BCM_6345_MPI_BASE (0xfffe2000) 327#define BCM_6345_PCIE_BASE (0xdeadbeef) 328#define BCM_6345_OHCI0_BASE (0xfffe2100) 329#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 330#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 331#define BCM_6345_USBD_BASE (0xdeadbeef) 332#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) 333#define BCM_6345_DSL_BASE (0xdeadbeef) 334#define BCM_6345_UBUS_BASE (0xdeadbeef) 335#define BCM_6345_ENET1_BASE (0xdeadbeef) 336#define BCM_6345_EHCI0_BASE (0xdeadbeef) 337#define BCM_6345_SDRAM_BASE (0xfffe2300) 338#define BCM_6345_MEMC_BASE (0xdeadbeef) 339#define BCM_6345_DDR_BASE (0xdeadbeef) 340#define BCM_6345_M2M_BASE (0xdeadbeef) 341#define BCM_6345_ATM_BASE (0xfffe4000) 342#define BCM_6345_XTM_BASE (0xdeadbeef) 343#define BCM_6345_XTMDMA_BASE (0xdeadbeef) 344#define BCM_6345_XTMDMAC_BASE (0xdeadbeef) 345#define BCM_6345_XTMDMAS_BASE (0xdeadbeef) 346#define BCM_6345_PCM_BASE (0xdeadbeef) 347#define BCM_6345_PCMDMA_BASE (0xdeadbeef) 348#define BCM_6345_PCMDMAC_BASE (0xdeadbeef) 349#define BCM_6345_PCMDMAS_BASE (0xdeadbeef) 350#define BCM_6345_RNG_BASE (0xdeadbeef) 351#define BCM_6345_MISC_BASE (0xdeadbeef) 352 353/* 354 * 6348 register sets base address 355 */ 356#define BCM_6348_DSL_LMEM_BASE (0xfff00000) 357#define BCM_6348_PERF_BASE (0xfffe0000) 358#define BCM_6348_TIMER_BASE (0xfffe0200) 359#define BCM_6348_WDT_BASE (0xfffe021c) 360#define BCM_6348_UART0_BASE (0xfffe0300) 361#define BCM_6348_UART1_BASE (0xdeadbeef) 362#define BCM_6348_GPIO_BASE (0xfffe0400) 363#define BCM_6348_SPI_BASE (0xfffe0c00) 364#define BCM_6348_HSSPI_BASE (0xdeadbeef) 365#define BCM_6348_UDC0_BASE (0xfffe1000) 366#define BCM_6348_USBDMA_BASE (0xdeadbeef) 367#define BCM_6348_OHCI0_BASE (0xfffe1b00) 368#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 369#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) 370#define BCM_6348_USBD_BASE (0xdeadbeef) 371#define BCM_6348_MPI_BASE (0xfffe2000) 372#define BCM_6348_PCMCIA_BASE (0xfffe2054) 373#define BCM_6348_PCIE_BASE (0xdeadbeef) 374#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 375#define BCM_6348_M2M_BASE (0xfffe2800) 376#define BCM_6348_DSL_BASE (0xfffe3000) 377#define BCM_6348_ENET0_BASE (0xfffe6000) 378#define BCM_6348_ENET1_BASE (0xfffe6800) 379#define BCM_6348_ENETDMA_BASE (0xfffe7000) 380#define BCM_6348_ENETDMAC_BASE (0xfffe7100) 381#define BCM_6348_ENETDMAS_BASE (0xfffe7200) 382#define BCM_6348_ENETSW_BASE (0xdeadbeef) 383#define BCM_6348_EHCI0_BASE (0xdeadbeef) 384#define BCM_6348_SDRAM_BASE (0xfffe2300) 385#define BCM_6348_MEMC_BASE (0xdeadbeef) 386#define BCM_6348_DDR_BASE (0xdeadbeef) 387#define BCM_6348_ATM_BASE (0xfffe4000) 388#define BCM_6348_XTM_BASE (0xdeadbeef) 389#define BCM_6348_XTMDMA_BASE (0xdeadbeef) 390#define BCM_6348_XTMDMAC_BASE (0xdeadbeef) 391#define BCM_6348_XTMDMAS_BASE (0xdeadbeef) 392#define BCM_6348_PCM_BASE (0xdeadbeef) 393#define BCM_6348_PCMDMA_BASE (0xdeadbeef) 394#define BCM_6348_PCMDMAC_BASE (0xdeadbeef) 395#define BCM_6348_PCMDMAS_BASE (0xdeadbeef) 396#define BCM_6348_RNG_BASE (0xdeadbeef) 397#define BCM_6348_MISC_BASE (0xdeadbeef) 398 399/* 400 * 6358 register sets base address 401 */ 402#define BCM_6358_DSL_LMEM_BASE (0xfff00000) 403#define BCM_6358_PERF_BASE (0xfffe0000) 404#define BCM_6358_TIMER_BASE (0xfffe0040) 405#define BCM_6358_WDT_BASE (0xfffe005c) 406#define BCM_6358_UART0_BASE (0xfffe0100) 407#define BCM_6358_UART1_BASE (0xfffe0120) 408#define BCM_6358_GPIO_BASE (0xfffe0080) 409#define BCM_6358_SPI_BASE (0xfffe0800) 410#define BCM_6358_HSSPI_BASE (0xdeadbeef) 411#define BCM_6358_UDC0_BASE (0xfffe0800) 412#define BCM_6358_USBDMA_BASE (0xdeadbeef) 413#define BCM_6358_OHCI0_BASE (0xfffe1400) 414#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 415#define BCM_6358_USBH_PRIV_BASE (0xfffe1500) 416#define BCM_6358_USBD_BASE (0xdeadbeef) 417#define BCM_6358_MPI_BASE (0xfffe1000) 418#define BCM_6358_PCMCIA_BASE (0xfffe1054) 419#define BCM_6358_PCIE_BASE (0xdeadbeef) 420#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 421#define BCM_6358_M2M_BASE (0xdeadbeef) 422#define BCM_6358_DSL_BASE (0xfffe3000) 423#define BCM_6358_ENET0_BASE (0xfffe4000) 424#define BCM_6358_ENET1_BASE (0xfffe4800) 425#define BCM_6358_ENETDMA_BASE (0xfffe5000) 426#define BCM_6358_ENETDMAC_BASE (0xfffe5100) 427#define BCM_6358_ENETDMAS_BASE (0xfffe5200) 428#define BCM_6358_ENETSW_BASE (0xdeadbeef) 429#define BCM_6358_EHCI0_BASE (0xfffe1300) 430#define BCM_6358_SDRAM_BASE (0xdeadbeef) 431#define BCM_6358_MEMC_BASE (0xfffe1200) 432#define BCM_6358_DDR_BASE (0xfffe12a0) 433#define BCM_6358_ATM_BASE (0xfffe2000) 434#define BCM_6358_XTM_BASE (0xdeadbeef) 435#define BCM_6358_XTMDMA_BASE (0xdeadbeef) 436#define BCM_6358_XTMDMAC_BASE (0xdeadbeef) 437#define BCM_6358_XTMDMAS_BASE (0xdeadbeef) 438#define BCM_6358_PCM_BASE (0xfffe1600) 439#define BCM_6358_PCMDMA_BASE (0xfffe1800) 440#define BCM_6358_PCMDMAC_BASE (0xfffe1900) 441#define BCM_6358_PCMDMAS_BASE (0xfffe1a00) 442#define BCM_6358_RNG_BASE (0xdeadbeef) 443#define BCM_6358_MISC_BASE (0xdeadbeef) 444 445 446/* 447 * 6362 register sets base address 448 */ 449#define BCM_6362_DSL_LMEM_BASE (0xdeadbeef) 450#define BCM_6362_PERF_BASE (0xb0000000) 451#define BCM_6362_TIMER_BASE (0xb0000040) 452#define BCM_6362_WDT_BASE (0xb000005c) 453#define BCM_6362_UART0_BASE (0xb0000100) 454#define BCM_6362_UART1_BASE (0xb0000120) 455#define BCM_6362_GPIO_BASE (0xb0000080) 456#define BCM_6362_SPI_BASE (0xb0000800) 457#define BCM_6362_HSSPI_BASE (0xb0001000) 458#define BCM_6362_UDC0_BASE (0xdeadbeef) 459#define BCM_6362_USBDMA_BASE (0xb000c000) 460#define BCM_6362_OHCI0_BASE (0xb0002600) 461#define BCM_6362_OHCI_PRIV_BASE (0xdeadbeef) 462#define BCM_6362_USBH_PRIV_BASE (0xb0002700) 463#define BCM_6362_USBD_BASE (0xb0002400) 464#define BCM_6362_MPI_BASE (0xdeadbeef) 465#define BCM_6362_PCMCIA_BASE (0xdeadbeef) 466#define BCM_6362_PCIE_BASE (0xb0e40000) 467#define BCM_6362_SDRAM_REGS_BASE (0xdeadbeef) 468#define BCM_6362_DSL_BASE (0xdeadbeef) 469#define BCM_6362_UBUS_BASE (0xdeadbeef) 470#define BCM_6362_ENET0_BASE (0xdeadbeef) 471#define BCM_6362_ENET1_BASE (0xdeadbeef) 472#define BCM_6362_ENETDMA_BASE (0xb000d800) 473#define BCM_6362_ENETDMAC_BASE (0xb000da00) 474#define BCM_6362_ENETDMAS_BASE (0xb000dc00) 475#define BCM_6362_ENETSW_BASE (0xb0e00000) 476#define BCM_6362_EHCI0_BASE (0xb0002500) 477#define BCM_6362_SDRAM_BASE (0xdeadbeef) 478#define BCM_6362_MEMC_BASE (0xdeadbeef) 479#define BCM_6362_DDR_BASE (0xb0003000) 480#define BCM_6362_M2M_BASE (0xdeadbeef) 481#define BCM_6362_ATM_BASE (0xdeadbeef) 482#define BCM_6362_XTM_BASE (0xb0007800) 483#define BCM_6362_XTMDMA_BASE (0xb000b800) 484#define BCM_6362_XTMDMAC_BASE (0xdeadbeef) 485#define BCM_6362_XTMDMAS_BASE (0xdeadbeef) 486#define BCM_6362_PCM_BASE (0xb000a800) 487#define BCM_6362_PCMDMA_BASE (0xdeadbeef) 488#define BCM_6362_PCMDMAC_BASE (0xdeadbeef) 489#define BCM_6362_PCMDMAS_BASE (0xdeadbeef) 490#define BCM_6362_RNG_BASE (0xdeadbeef) 491#define BCM_6362_MISC_BASE (0xb0001800) 492 493#define BCM_6362_NAND_REG_BASE (0xb0000200) 494#define BCM_6362_NAND_CACHE_BASE (0xb0000600) 495#define BCM_6362_LED_BASE (0xb0001900) 496#define BCM_6362_IPSEC_BASE (0xb0002800) 497#define BCM_6362_IPSEC_DMA_BASE (0xb000d000) 498#define BCM_6362_WLAN_CHIPCOMMON_BASE (0xb0004000) 499#define BCM_6362_WLAN_D11_BASE (0xb0005000) 500#define BCM_6362_WLAN_SHIM_BASE (0xb0007000) 501 502/* 503 * 6368 register sets base address 504 */ 505#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef) 506#define BCM_6368_PERF_BASE (0xb0000000) 507#define BCM_6368_TIMER_BASE (0xb0000040) 508#define BCM_6368_WDT_BASE (0xb000005c) 509#define BCM_6368_UART0_BASE (0xb0000100) 510#define BCM_6368_UART1_BASE (0xb0000120) 511#define BCM_6368_GPIO_BASE (0xb0000080) 512#define BCM_6368_SPI_BASE (0xb0000800) 513#define BCM_6368_HSSPI_BASE (0xdeadbeef) 514#define BCM_6368_UDC0_BASE (0xdeadbeef) 515#define BCM_6368_USBDMA_BASE (0xb0004800) 516#define BCM_6368_OHCI0_BASE (0xb0001600) 517#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) 518#define BCM_6368_USBH_PRIV_BASE (0xb0001700) 519#define BCM_6368_USBD_BASE (0xb0001400) 520#define BCM_6368_MPI_BASE (0xb0001000) 521#define BCM_6368_PCMCIA_BASE (0xb0001054) 522#define BCM_6368_PCIE_BASE (0xdeadbeef) 523#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef) 524#define BCM_6368_M2M_BASE (0xdeadbeef) 525#define BCM_6368_DSL_BASE (0xdeadbeef) 526#define BCM_6368_ENET0_BASE (0xdeadbeef) 527#define BCM_6368_ENET1_BASE (0xdeadbeef) 528#define BCM_6368_ENETDMA_BASE (0xb0006800) 529#define BCM_6368_ENETDMAC_BASE (0xb0006a00) 530#define BCM_6368_ENETDMAS_BASE (0xb0006c00) 531#define BCM_6368_ENETSW_BASE (0xb0f00000) 532#define BCM_6368_EHCI0_BASE (0xb0001500) 533#define BCM_6368_SDRAM_BASE (0xdeadbeef) 534#define BCM_6368_MEMC_BASE (0xb0001200) 535#define BCM_6368_DDR_BASE (0xb0001280) 536#define BCM_6368_ATM_BASE (0xdeadbeef) 537#define BCM_6368_XTM_BASE (0xb0001800) 538#define BCM_6368_XTMDMA_BASE (0xb0005000) 539#define BCM_6368_XTMDMAC_BASE (0xb0005200) 540#define BCM_6368_XTMDMAS_BASE (0xb0005400) 541#define BCM_6368_PCM_BASE (0xb0004000) 542#define BCM_6368_PCMDMA_BASE (0xb0005800) 543#define BCM_6368_PCMDMAC_BASE (0xb0005a00) 544#define BCM_6368_PCMDMAS_BASE (0xb0005c00) 545#define BCM_6368_RNG_BASE (0xb0004180) 546#define BCM_6368_MISC_BASE (0xdeadbeef) 547 548 549extern const unsigned long *bcm63xx_regs_base; 550 551#define __GEN_CPU_REGS_TABLE(__cpu) \ 552 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \ 553 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \ 554 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \ 555 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \ 556 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \ 557 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ 558 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ 559 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ 560 [RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \ 561 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ 562 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ 563 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ 564 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ 565 [RSET_USBD] = BCM_## __cpu ##_USBD_BASE, \ 566 [RSET_USBDMA] = BCM_## __cpu ##_USBDMA_BASE, \ 567 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ 568 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ 569 [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \ 570 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \ 571 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \ 572 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \ 573 [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \ 574 [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \ 575 [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \ 576 [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \ 577 [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \ 578 [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \ 579 [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \ 580 [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \ 581 [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \ 582 [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \ 583 [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \ 584 [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \ 585 [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \ 586 [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \ 587 [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \ 588 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \ 589 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \ 590 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ 591 [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \ 592 [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \ 593 594 595static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 596{ 597 return bcm63xx_regs_base[set]; 598} 599 600/* 601 * IRQ number changes across CPU too 602 */ 603enum bcm63xx_irq { 604 IRQ_TIMER = 0, 605 IRQ_SPI, 606 IRQ_UART0, 607 IRQ_UART1, 608 IRQ_DSL, 609 IRQ_ENET0, 610 IRQ_ENET1, 611 IRQ_ENET_PHY, 612 IRQ_HSSPI, 613 IRQ_OHCI0, 614 IRQ_EHCI0, 615 IRQ_USBD, 616 IRQ_USBD_RXDMA0, 617 IRQ_USBD_TXDMA0, 618 IRQ_USBD_RXDMA1, 619 IRQ_USBD_TXDMA1, 620 IRQ_USBD_RXDMA2, 621 IRQ_USBD_TXDMA2, 622 IRQ_ENET0_RXDMA, 623 IRQ_ENET0_TXDMA, 624 IRQ_ENET1_RXDMA, 625 IRQ_ENET1_TXDMA, 626 IRQ_PCI, 627 IRQ_PCMCIA, 628 IRQ_ATM, 629 IRQ_ENETSW_RXDMA0, 630 IRQ_ENETSW_RXDMA1, 631 IRQ_ENETSW_RXDMA2, 632 IRQ_ENETSW_RXDMA3, 633 IRQ_ENETSW_TXDMA0, 634 IRQ_ENETSW_TXDMA1, 635 IRQ_ENETSW_TXDMA2, 636 IRQ_ENETSW_TXDMA3, 637 IRQ_XTM, 638 IRQ_XTM_DMA0, 639}; 640 641/* 642 * 3368 irqs 643 */ 644#define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 645#define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 646#define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 647#define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 648#define BCM_3368_DSL_IRQ 0 649#define BCM_3368_UDC0_IRQ 0 650#define BCM_3368_OHCI0_IRQ 0 651#define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 652#define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 653#define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 654#define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 655#define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 656#define BCM_3368_HSSPI_IRQ 0 657#define BCM_3368_EHCI0_IRQ 0 658#define BCM_3368_USBD_IRQ 0 659#define BCM_3368_USBD_RXDMA0_IRQ 0 660#define BCM_3368_USBD_TXDMA0_IRQ 0 661#define BCM_3368_USBD_RXDMA1_IRQ 0 662#define BCM_3368_USBD_TXDMA1_IRQ 0 663#define BCM_3368_USBD_RXDMA2_IRQ 0 664#define BCM_3368_USBD_TXDMA2_IRQ 0 665#define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 666#define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 667#define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 668#define BCM_3368_PCMCIA_IRQ 0 669#define BCM_3368_ATM_IRQ 0 670#define BCM_3368_ENETSW_RXDMA0_IRQ 0 671#define BCM_3368_ENETSW_RXDMA1_IRQ 0 672#define BCM_3368_ENETSW_RXDMA2_IRQ 0 673#define BCM_3368_ENETSW_RXDMA3_IRQ 0 674#define BCM_3368_ENETSW_TXDMA0_IRQ 0 675#define BCM_3368_ENETSW_TXDMA1_IRQ 0 676#define BCM_3368_ENETSW_TXDMA2_IRQ 0 677#define BCM_3368_ENETSW_TXDMA3_IRQ 0 678#define BCM_3368_XTM_IRQ 0 679#define BCM_3368_XTM_DMA0_IRQ 0 680 681#define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25) 682#define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) 683#define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) 684#define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) 685 686 687/* 688 * 6328 irqs 689 */ 690#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 691 692#define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31) 693#define BCM_6328_SPI_IRQ 0 694#define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28) 695#define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7) 696#define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 697#define BCM_6328_UDC0_IRQ 0 698#define BCM_6328_ENET0_IRQ 0 699#define BCM_6328_ENET1_IRQ 0 700#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 701#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29) 702#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) 703#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) 704#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4) 705#define BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5) 706#define BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6) 707#define BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7) 708#define BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8) 709#define BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9) 710#define BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10) 711#define BCM_6328_PCMCIA_IRQ 0 712#define BCM_6328_ENET0_RXDMA_IRQ 0 713#define BCM_6328_ENET0_TXDMA_IRQ 0 714#define BCM_6328_ENET1_RXDMA_IRQ 0 715#define BCM_6328_ENET1_TXDMA_IRQ 0 716#define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23) 717#define BCM_6328_ATM_IRQ 0 718#define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0) 719#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1) 720#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2) 721#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3) 722#define BCM_6328_ENETSW_TXDMA0_IRQ 0 723#define BCM_6328_ENETSW_TXDMA1_IRQ 0 724#define BCM_6328_ENETSW_TXDMA2_IRQ 0 725#define BCM_6328_ENETSW_TXDMA3_IRQ 0 726#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31) 727#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11) 728 729#define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2) 730#define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3) 731#define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24) 732#define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25) 733#define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26) 734#define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27) 735 736/* 737 * 6338 irqs 738 */ 739#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 740#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 741#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 742#define BCM_6338_UART1_IRQ 0 743#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 744#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 745#define BCM_6338_ENET1_IRQ 0 746#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 747#define BCM_6338_HSSPI_IRQ 0 748#define BCM_6338_OHCI0_IRQ 0 749#define BCM_6338_EHCI0_IRQ 0 750#define BCM_6338_USBD_IRQ 0 751#define BCM_6338_USBD_RXDMA0_IRQ 0 752#define BCM_6338_USBD_TXDMA0_IRQ 0 753#define BCM_6338_USBD_RXDMA1_IRQ 0 754#define BCM_6338_USBD_TXDMA1_IRQ 0 755#define BCM_6338_USBD_RXDMA2_IRQ 0 756#define BCM_6338_USBD_TXDMA2_IRQ 0 757#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 758#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 759#define BCM_6338_ENET1_RXDMA_IRQ 0 760#define BCM_6338_ENET1_TXDMA_IRQ 0 761#define BCM_6338_PCI_IRQ 0 762#define BCM_6338_PCMCIA_IRQ 0 763#define BCM_6338_ATM_IRQ 0 764#define BCM_6338_ENETSW_RXDMA0_IRQ 0 765#define BCM_6338_ENETSW_RXDMA1_IRQ 0 766#define BCM_6338_ENETSW_RXDMA2_IRQ 0 767#define BCM_6338_ENETSW_RXDMA3_IRQ 0 768#define BCM_6338_ENETSW_TXDMA0_IRQ 0 769#define BCM_6338_ENETSW_TXDMA1_IRQ 0 770#define BCM_6338_ENETSW_TXDMA2_IRQ 0 771#define BCM_6338_ENETSW_TXDMA3_IRQ 0 772#define BCM_6338_XTM_IRQ 0 773#define BCM_6338_XTM_DMA0_IRQ 0 774 775/* 776 * 6345 irqs 777 */ 778#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 779#define BCM_6345_SPI_IRQ 0 780#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 781#define BCM_6345_UART1_IRQ 0 782#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 783#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 784#define BCM_6345_ENET1_IRQ 0 785#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 786#define BCM_6345_HSSPI_IRQ 0 787#define BCM_6345_OHCI0_IRQ 0 788#define BCM_6345_EHCI0_IRQ 0 789#define BCM_6345_USBD_IRQ 0 790#define BCM_6345_USBD_RXDMA0_IRQ 0 791#define BCM_6345_USBD_TXDMA0_IRQ 0 792#define BCM_6345_USBD_RXDMA1_IRQ 0 793#define BCM_6345_USBD_TXDMA1_IRQ 0 794#define BCM_6345_USBD_RXDMA2_IRQ 0 795#define BCM_6345_USBD_TXDMA2_IRQ 0 796#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) 797#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) 798#define BCM_6345_ENET1_RXDMA_IRQ 0 799#define BCM_6345_ENET1_TXDMA_IRQ 0 800#define BCM_6345_PCI_IRQ 0 801#define BCM_6345_PCMCIA_IRQ 0 802#define BCM_6345_ATM_IRQ 0 803#define BCM_6345_ENETSW_RXDMA0_IRQ 0 804#define BCM_6345_ENETSW_RXDMA1_IRQ 0 805#define BCM_6345_ENETSW_RXDMA2_IRQ 0 806#define BCM_6345_ENETSW_RXDMA3_IRQ 0 807#define BCM_6345_ENETSW_TXDMA0_IRQ 0 808#define BCM_6345_ENETSW_TXDMA1_IRQ 0 809#define BCM_6345_ENETSW_TXDMA2_IRQ 0 810#define BCM_6345_ENETSW_TXDMA3_IRQ 0 811#define BCM_6345_XTM_IRQ 0 812#define BCM_6345_XTM_DMA0_IRQ 0 813 814/* 815 * 6348 irqs 816 */ 817#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 818#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 819#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 820#define BCM_6348_UART1_IRQ 0 821#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 822#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 823#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) 824#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 825#define BCM_6348_HSSPI_IRQ 0 826#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 827#define BCM_6348_EHCI0_IRQ 0 828#define BCM_6348_USBD_IRQ 0 829#define BCM_6348_USBD_RXDMA0_IRQ 0 830#define BCM_6348_USBD_TXDMA0_IRQ 0 831#define BCM_6348_USBD_RXDMA1_IRQ 0 832#define BCM_6348_USBD_TXDMA1_IRQ 0 833#define BCM_6348_USBD_RXDMA2_IRQ 0 834#define BCM_6348_USBD_TXDMA2_IRQ 0 835#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) 836#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) 837#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) 838#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) 839#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) 840#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 841#define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5) 842#define BCM_6348_ENETSW_RXDMA0_IRQ 0 843#define BCM_6348_ENETSW_RXDMA1_IRQ 0 844#define BCM_6348_ENETSW_RXDMA2_IRQ 0 845#define BCM_6348_ENETSW_RXDMA3_IRQ 0 846#define BCM_6348_ENETSW_TXDMA0_IRQ 0 847#define BCM_6348_ENETSW_TXDMA1_IRQ 0 848#define BCM_6348_ENETSW_TXDMA2_IRQ 0 849#define BCM_6348_ENETSW_TXDMA3_IRQ 0 850#define BCM_6348_XTM_IRQ 0 851#define BCM_6348_XTM_DMA0_IRQ 0 852 853/* 854 * 6358 irqs 855 */ 856#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 857#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 858#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 859#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 860#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) 861#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 862#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 863#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 864#define BCM_6358_HSSPI_IRQ 0 865#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 866#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 867#define BCM_6358_USBD_IRQ 0 868#define BCM_6358_USBD_RXDMA0_IRQ 0 869#define BCM_6358_USBD_TXDMA0_IRQ 0 870#define BCM_6358_USBD_RXDMA1_IRQ 0 871#define BCM_6358_USBD_TXDMA1_IRQ 0 872#define BCM_6358_USBD_RXDMA2_IRQ 0 873#define BCM_6358_USBD_TXDMA2_IRQ 0 874#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 875#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 876#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 877#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 878#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 879#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 880#define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19) 881#define BCM_6358_ENETSW_RXDMA0_IRQ 0 882#define BCM_6358_ENETSW_RXDMA1_IRQ 0 883#define BCM_6358_ENETSW_RXDMA2_IRQ 0 884#define BCM_6358_ENETSW_RXDMA3_IRQ 0 885#define BCM_6358_ENETSW_TXDMA0_IRQ 0 886#define BCM_6358_ENETSW_TXDMA1_IRQ 0 887#define BCM_6358_ENETSW_TXDMA2_IRQ 0 888#define BCM_6358_ENETSW_TXDMA3_IRQ 0 889#define BCM_6358_XTM_IRQ 0 890#define BCM_6358_XTM_DMA0_IRQ 0 891 892#define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23) 893#define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24) 894#define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25) 895#define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) 896#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) 897#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) 898 899/* 900 * 6362 irqs 901 */ 902#define BCM_6362_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 903 904#define BCM_6362_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 905#define BCM_6362_SPI_IRQ (IRQ_INTERNAL_BASE + 2) 906#define BCM_6362_UART0_IRQ (IRQ_INTERNAL_BASE + 3) 907#define BCM_6362_UART1_IRQ (IRQ_INTERNAL_BASE + 4) 908#define BCM_6362_DSL_IRQ (IRQ_INTERNAL_BASE + 28) 909#define BCM_6362_UDC0_IRQ 0 910#define BCM_6362_ENET0_IRQ 0 911#define BCM_6362_ENET1_IRQ 0 912#define BCM_6362_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 14) 913#define BCM_6362_HSSPI_IRQ (IRQ_INTERNAL_BASE + 5) 914#define BCM_6362_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) 915#define BCM_6362_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 916#define BCM_6362_USBD_IRQ (IRQ_INTERNAL_BASE + 11) 917#define BCM_6362_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 20) 918#define BCM_6362_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 21) 919#define BCM_6362_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 22) 920#define BCM_6362_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 23) 921#define BCM_6362_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 24) 922#define BCM_6362_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 25) 923#define BCM_6362_PCMCIA_IRQ 0 924#define BCM_6362_ENET0_RXDMA_IRQ 0 925#define BCM_6362_ENET0_TXDMA_IRQ 0 926#define BCM_6362_ENET1_RXDMA_IRQ 0 927#define BCM_6362_ENET1_TXDMA_IRQ 0 928#define BCM_6362_PCI_IRQ (IRQ_INTERNAL_BASE + 30) 929#define BCM_6362_ATM_IRQ 0 930#define BCM_6362_ENETSW_RXDMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 0) 931#define BCM_6362_ENETSW_RXDMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 1) 932#define BCM_6362_ENETSW_RXDMA2_IRQ (BCM_6362_HIGH_IRQ_BASE + 2) 933#define BCM_6362_ENETSW_RXDMA3_IRQ (BCM_6362_HIGH_IRQ_BASE + 3) 934#define BCM_6362_ENETSW_TXDMA0_IRQ 0 935#define BCM_6362_ENETSW_TXDMA1_IRQ 0 936#define BCM_6362_ENETSW_TXDMA2_IRQ 0 937#define BCM_6362_ENETSW_TXDMA3_IRQ 0 938#define BCM_6362_XTM_IRQ 0 939#define BCM_6362_XTM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 12) 940 941#define BCM_6362_RING_OSC_IRQ (IRQ_INTERNAL_BASE + 1) 942#define BCM_6362_WLAN_GPIO_IRQ (IRQ_INTERNAL_BASE + 6) 943#define BCM_6362_WLAN_IRQ (IRQ_INTERNAL_BASE + 7) 944#define BCM_6362_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8) 945#define BCM_6362_NAND_IRQ (IRQ_INTERNAL_BASE + 12) 946#define BCM_6362_PCM_IRQ (IRQ_INTERNAL_BASE + 13) 947#define BCM_6362_DG_IRQ (IRQ_INTERNAL_BASE + 15) 948#define BCM_6362_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16) 949#define BCM_6362_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17) 950#define BCM_6362_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18) 951#define BCM_6362_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19) 952#define BCM_6362_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 26) 953#define BCM_6362_IPSEC_DMA1_IRQ (IRQ_INTERNAL_BASE + 27) 954#define BCM_6362_FAP0_IRQ (IRQ_INTERNAL_BASE + 29) 955#define BCM_6362_PCM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 4) 956#define BCM_6362_PCM_DMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 5) 957#define BCM_6362_DECT0_IRQ (BCM_6362_HIGH_IRQ_BASE + 6) 958#define BCM_6362_DECT1_IRQ (BCM_6362_HIGH_IRQ_BASE + 7) 959#define BCM_6362_EXT_IRQ0 (BCM_6362_HIGH_IRQ_BASE + 8) 960#define BCM_6362_EXT_IRQ1 (BCM_6362_HIGH_IRQ_BASE + 9) 961#define BCM_6362_EXT_IRQ2 (BCM_6362_HIGH_IRQ_BASE + 10) 962#define BCM_6362_EXT_IRQ3 (BCM_6362_HIGH_IRQ_BASE + 11) 963 964/* 965 * 6368 irqs 966 */ 967#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 968 969#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 970#define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 971#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 972#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 973#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 974#define BCM_6368_ENET0_IRQ 0 975#define BCM_6368_ENET1_IRQ 0 976#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) 977#define BCM_6368_HSSPI_IRQ 0 978#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 979#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) 980#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8) 981#define BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26) 982#define BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27) 983#define BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28) 984#define BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29) 985#define BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30) 986#define BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31) 987#define BCM_6368_PCMCIA_IRQ 0 988#define BCM_6368_ENET0_RXDMA_IRQ 0 989#define BCM_6368_ENET0_TXDMA_IRQ 0 990#define BCM_6368_ENET1_RXDMA_IRQ 0 991#define BCM_6368_ENET1_TXDMA_IRQ 0 992#define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13) 993#define BCM_6368_ATM_IRQ 0 994#define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0) 995#define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1) 996#define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2) 997#define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3) 998#define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4) 999#define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5) 1000#define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6) 1001#define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7) 1002#define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11) 1003#define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8) 1004 1005#define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30) 1006#define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31) 1007#define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20) 1008#define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21) 1009#define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22) 1010#define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23) 1011#define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24) 1012#define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25) 1013 1014extern const int *bcm63xx_irqs; 1015 1016#define __GEN_CPU_IRQ_TABLE(__cpu) \ 1017 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \ 1018 [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \ 1019 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \ 1020 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \ 1021 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \ 1022 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \ 1023 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \ 1024 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ 1025 [IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \ 1026 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ 1027 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ 1028 [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \ 1029 [IRQ_USBD_RXDMA0] = BCM_## __cpu ##_USBD_RXDMA0_IRQ, \ 1030 [IRQ_USBD_TXDMA0] = BCM_## __cpu ##_USBD_TXDMA0_IRQ, \ 1031 [IRQ_USBD_RXDMA1] = BCM_## __cpu ##_USBD_RXDMA1_IRQ, \ 1032 [IRQ_USBD_TXDMA1] = BCM_## __cpu ##_USBD_TXDMA1_IRQ, \ 1033 [IRQ_USBD_RXDMA2] = BCM_## __cpu ##_USBD_RXDMA2_IRQ, \ 1034 [IRQ_USBD_TXDMA2] = BCM_## __cpu ##_USBD_TXDMA2_IRQ, \ 1035 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \ 1036 [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \ 1037 [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \ 1038 [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \ 1039 [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \ 1040 [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \ 1041 [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \ 1042 [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \ 1043 [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \ 1044 [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \ 1045 [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \ 1046 [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \ 1047 [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \ 1048 [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \ 1049 [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \ 1050 [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \ 1051 [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \ 1052 1053static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) 1054{ 1055 return bcm63xx_irqs[irq]; 1056} 1057 1058/* 1059 * return installed memory size 1060 */ 1061unsigned int bcm63xx_get_memory_size(void); 1062 1063void bcm63xx_machine_halt(void); 1064 1065void bcm63xx_machine_reboot(void); 1066 1067#endif /* !BCM63XX_CPU_H_ */ 1068