1/*
2 * Cobalt Qube/Raq PCI support
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License.  See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
10 */
11#include <linux/types.h>
12#include <linux/pci.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15
16#include <asm/pci.h>
17#include <asm/io.h>
18#include <asm/gt64120.h>
19
20#include <cobalt.h>
21#include <irq.h>
22
23/*
24 * PCI slot numbers
25 */
26#define COBALT_PCICONF_CPU	0x06
27#define COBALT_PCICONF_ETH0	0x07
28#define COBALT_PCICONF_RAQSCSI	0x08
29#define COBALT_PCICONF_VIA	0x09
30#define COBALT_PCICONF_PCISLOT	0x0A
31#define COBALT_PCICONF_ETH1	0x0C
32
33/*
34 * The Cobalt board ID information.  The boards have an ID number wired
35 * into the VIA that is available in the high nibble of register 94.
36 */
37#define VIA_COBALT_BRD_ID_REG  0x94
38#define VIA_COBALT_BRD_REG_to_ID(reg)	((unsigned char)(reg) >> 4)
39
40static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
41{
42	if (dev->devfn == PCI_DEVFN(0, 0) &&
43		(dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
44
45		dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
46
47		printk(KERN_INFO "Galileo: fixed bridge class\n");
48	}
49}
50
51DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
52	 qube_raq_galileo_early_fixup);
53
54static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
55{
56	unsigned short cfgword;
57	unsigned char lt;
58
59	/* Enable Bus Mastering and fast back to back. */
60	pci_read_config_word(dev, PCI_COMMAND, &cfgword);
61	cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
62	pci_write_config_word(dev, PCI_COMMAND, cfgword);
63
64	/* Enable both ide interfaces. ROM only enables primary one.  */
65	pci_write_config_byte(dev, 0x40, 0xb);
66
67	/* Set latency timer to reasonable value. */
68	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
69	if (lt < 64)
70		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
71	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
72}
73
74DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
75	 qube_raq_via_bmIDE_fixup);
76
77static void qube_raq_galileo_fixup(struct pci_dev *dev)
78{
79	if (dev->devfn != PCI_DEVFN(0, 0))
80		return;
81
82	/* Fix PCI latency-timer and cache-line-size values in Galileo
83	 * host bridge.
84	 */
85	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
86	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
87
88	/*
89	 * The code described by the comment below has been removed
90	 * as it causes bus mastering by the Ethernet controllers
91	 * to break under any kind of network load. We always set
92	 * the retry timeouts to their maximum.
93	 *
94	 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
95	 *
96	 * On all machines prior to Q2, we had the STOP line disconnected
97	 * from Galileo to VIA on PCI.	The new Galileo does not function
98	 * correctly unless we have it connected.
99	 *
100	 * Therefore we must set the disconnect/retry cycle values to
101	 * something sensible when using the new Galileo.
102	 */
103
104	printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
105
106#if 0
107	if (dev->revision >= 0x10) {
108		/* New Galileo, assumes PCI stop line to VIA is connected. */
109		GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
110	} else if (dev->revision == 0x1 || dev->revision == 0x2)
111#endif
112	{
113		signed int timeo;
114		/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
115		timeo = GT_READ(GT_PCI0_TOR_OFS);
116		/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
117		GT_WRITE(GT_PCI0_TOR_OFS,
118			(0xff << 16) |		/* retry count */
119			(0xff << 8) |		/* timeout 1   */
120			0xff);			/* timeout 0   */
121
122		/* enable PCI retry exceeded interrupt */
123		GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
124	}
125}
126
127DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
128	 qube_raq_galileo_fixup);
129
130int cobalt_board_id;
131
132static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
133{
134	u8 id;
135	int retval;
136
137	retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
138	if (retval) {
139		panic("Cannot read board ID");
140		return;
141	}
142
143	cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);
144
145	printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
146}
147
148DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
149	 qube_raq_via_board_id_fixup);
150
151static char irq_tab_qube1[] __initdata = {
152  [COBALT_PCICONF_CPU]	   = 0,
153  [COBALT_PCICONF_ETH0]	   = QUBE1_ETH0_IRQ,
154  [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
155  [COBALT_PCICONF_VIA]	   = 0,
156  [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
157  [COBALT_PCICONF_ETH1]	   = 0
158};
159
160static char irq_tab_cobalt[] __initdata = {
161  [COBALT_PCICONF_CPU]	   = 0,
162  [COBALT_PCICONF_ETH0]	   = ETH0_IRQ,
163  [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
164  [COBALT_PCICONF_VIA]	   = 0,
165  [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
166  [COBALT_PCICONF_ETH1]	   = ETH1_IRQ
167};
168
169static char irq_tab_raq2[] __initdata = {
170  [COBALT_PCICONF_CPU]	   = 0,
171  [COBALT_PCICONF_ETH0]	   = ETH0_IRQ,
172  [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
173  [COBALT_PCICONF_VIA]	   = 0,
174  [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
175  [COBALT_PCICONF_ETH1]	   = ETH1_IRQ
176};
177
178int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
179{
180	if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
181		return irq_tab_qube1[slot];
182
183	if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
184		return irq_tab_raq2[slot];
185
186	return irq_tab_cobalt[slot];
187}
188
189/* Do platform specific device initialization at pci_enable_device() time */
190int pcibios_plat_dev_init(struct pci_dev *dev)
191{
192	return 0;
193}
194