1/*
2 * This program is free software; you can redistribute	it and/or modify it
3 * under  the terms of	the GNU General	 Public License as published by the
4 * Free Software Foundation;  either version 2 of the  License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 2011 Wind River Systems,
9 *   written by Ralf Baechle (ralf@linux-mips.org)
10 */
11#include <linux/bug.h>
12#include <linux/kernel.h>
13#include <linux/mm.h>
14#include <linux/bootmem.h>
15#include <linux/export.h>
16#include <linux/init.h>
17#include <linux/types.h>
18#include <linux/pci.h>
19#include <linux/of_address.h>
20
21#include <asm/cpu-info.h>
22
23/*
24 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
25 * assignments.
26 */
27
28/*
29 * The PCI controller list.
30 */
31
32static struct pci_controller *hose_head, **hose_tail = &hose_head;
33
34unsigned long PCIBIOS_MIN_IO;
35unsigned long PCIBIOS_MIN_MEM;
36
37static int pci_initialized;
38
39/*
40 * We need to avoid collisions with `mirrored' VGA ports
41 * and other strange ISA hardware, so we always want the
42 * addresses to be allocated in the 0x000-0x0ff region
43 * modulo 0x400.
44 *
45 * Why? Because some silly external IO cards only decode
46 * the low 10 bits of the IO address. The 0x00-0xff region
47 * is reserved for motherboard devices that decode all 16
48 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
49 * but we want to try to avoid allocating at 0x2900-0x2bff
50 * which might have be mirrored at 0x0100-0x03ff..
51 */
52resource_size_t
53pcibios_align_resource(void *data, const struct resource *res,
54		       resource_size_t size, resource_size_t align)
55{
56	struct pci_dev *dev = data;
57	struct pci_controller *hose = dev->sysdata;
58	resource_size_t start = res->start;
59
60	if (res->flags & IORESOURCE_IO) {
61		/* Make sure we start at our min on all hoses */
62		if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
63			start = PCIBIOS_MIN_IO + hose->io_resource->start;
64
65		/*
66		 * Put everything into 0x00-0xff region modulo 0x400
67		 */
68		if (start & 0x300)
69			start = (start + 0x3ff) & ~0x3ff;
70	} else if (res->flags & IORESOURCE_MEM) {
71		/* Make sure we start at our min on all hoses */
72		if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
73			start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
74	}
75
76	return start;
77}
78
79static void pcibios_scanbus(struct pci_controller *hose)
80{
81	static int next_busno;
82	static int need_domain_info;
83	LIST_HEAD(resources);
84	struct pci_bus *bus;
85
86	if (!hose->iommu)
87		PCI_DMA_BUS_IS_PHYS = 1;
88
89	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
90		next_busno = (*hose->get_busno)();
91
92	pci_add_resource_offset(&resources,
93				hose->mem_resource, hose->mem_offset);
94	pci_add_resource_offset(&resources,
95				hose->io_resource, hose->io_offset);
96	pci_add_resource_offset(&resources,
97				hose->busn_resource, hose->busn_offset);
98	bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
99				&resources);
100	hose->bus = bus;
101
102	need_domain_info = need_domain_info || hose->index;
103	hose->need_domain_info = need_domain_info;
104
105	if (!bus) {
106		pci_free_resource_list(&resources);
107		return;
108	}
109
110	next_busno = bus->busn_res.end + 1;
111	/* Don't allow 8-bit bus number overflow inside the hose -
112	   reserve some space for bridges. */
113	if (next_busno > 224) {
114		next_busno = 0;
115		need_domain_info = 1;
116	}
117
118	if (!pci_has_flag(PCI_PROBE_ONLY)) {
119		pci_bus_size_bridges(bus);
120		pci_bus_assign_resources(bus);
121	}
122	pci_bus_add_devices(bus);
123}
124
125#ifdef CONFIG_OF
126void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
127{
128	struct of_pci_range range;
129	struct of_pci_range_parser parser;
130
131	pr_info("PCI host bridge %s ranges:\n", node->full_name);
132	hose->of_node = node;
133
134	if (of_pci_range_parser_init(&parser, node))
135		return;
136
137	for_each_of_pci_range(&parser, &range) {
138		struct resource *res = NULL;
139
140		switch (range.flags & IORESOURCE_TYPE_BITS) {
141		case IORESOURCE_IO:
142			pr_info("  IO 0x%016llx..0x%016llx\n",
143				range.cpu_addr,
144				range.cpu_addr + range.size - 1);
145			hose->io_map_base =
146				(unsigned long)ioremap(range.cpu_addr,
147						       range.size);
148			res = hose->io_resource;
149			break;
150		case IORESOURCE_MEM:
151			pr_info(" MEM 0x%016llx..0x%016llx\n",
152				range.cpu_addr,
153				range.cpu_addr + range.size - 1);
154			res = hose->mem_resource;
155			break;
156		}
157		if (res != NULL)
158			of_pci_range_to_resource(&range, node, res);
159	}
160}
161
162struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
163{
164	struct pci_controller *hose = bus->sysdata;
165
166	return of_node_get(hose->of_node);
167}
168#endif
169
170static DEFINE_MUTEX(pci_scan_mutex);
171
172void register_pci_controller(struct pci_controller *hose)
173{
174	struct resource *parent;
175
176	parent = hose->mem_resource->parent;
177	if (!parent)
178		parent = &iomem_resource;
179
180	if (request_resource(parent, hose->mem_resource) < 0)
181		goto out;
182
183	parent = hose->io_resource->parent;
184	if (!parent)
185		parent = &ioport_resource;
186
187	if (request_resource(parent, hose->io_resource) < 0) {
188		release_resource(hose->mem_resource);
189		goto out;
190	}
191
192	*hose_tail = hose;
193	hose_tail = &hose->next;
194
195	/*
196	 * Do not panic here but later - this might happen before console init.
197	 */
198	if (!hose->io_map_base) {
199		printk(KERN_WARNING
200		       "registering PCI controller with io_map_base unset\n");
201	}
202
203	/*
204	 * Scan the bus if it is register after the PCI subsystem
205	 * initialization.
206	 */
207	if (pci_initialized) {
208		mutex_lock(&pci_scan_mutex);
209		pcibios_scanbus(hose);
210		mutex_unlock(&pci_scan_mutex);
211	}
212
213	return;
214
215out:
216	printk(KERN_WARNING
217	       "Skipping PCI bus scan due to resource conflict\n");
218}
219
220static void __init pcibios_set_cache_line_size(void)
221{
222	struct cpuinfo_mips *c = &current_cpu_data;
223	unsigned int lsize;
224
225	/*
226	 * Set PCI cacheline size to that of the highest level in the
227	 * cache hierarchy.
228	 */
229	lsize = c->dcache.linesz;
230	lsize = c->scache.linesz ? : lsize;
231	lsize = c->tcache.linesz ? : lsize;
232
233	BUG_ON(!lsize);
234
235	pci_dfl_cache_line_size = lsize >> 2;
236
237	pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
238}
239
240static int __init pcibios_init(void)
241{
242	struct pci_controller *hose;
243
244	pcibios_set_cache_line_size();
245
246	/* Scan all of the recorded PCI controllers.  */
247	for (hose = hose_head; hose; hose = hose->next)
248		pcibios_scanbus(hose);
249
250	pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
251
252	pci_initialized = 1;
253
254	return 0;
255}
256
257subsys_initcall(pcibios_init);
258
259static int pcibios_enable_resources(struct pci_dev *dev, int mask)
260{
261	u16 cmd, old_cmd;
262	int idx;
263	struct resource *r;
264
265	pci_read_config_word(dev, PCI_COMMAND, &cmd);
266	old_cmd = cmd;
267	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
268		/* Only set up the requested stuff */
269		if (!(mask & (1<<idx)))
270			continue;
271
272		r = &dev->resource[idx];
273		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
274			continue;
275		if ((idx == PCI_ROM_RESOURCE) &&
276				(!(r->flags & IORESOURCE_ROM_ENABLE)))
277			continue;
278		if (!r->start && r->end) {
279			printk(KERN_ERR "PCI: Device %s not available "
280			       "because of resource collisions\n",
281			       pci_name(dev));
282			return -EINVAL;
283		}
284		if (r->flags & IORESOURCE_IO)
285			cmd |= PCI_COMMAND_IO;
286		if (r->flags & IORESOURCE_MEM)
287			cmd |= PCI_COMMAND_MEMORY;
288	}
289	if (cmd != old_cmd) {
290		printk("PCI: Enabling device %s (%04x -> %04x)\n",
291		       pci_name(dev), old_cmd, cmd);
292		pci_write_config_word(dev, PCI_COMMAND, cmd);
293	}
294	return 0;
295}
296
297unsigned int pcibios_assign_all_busses(void)
298{
299	return 1;
300}
301
302int pcibios_enable_device(struct pci_dev *dev, int mask)
303{
304	int err;
305
306	if ((err = pcibios_enable_resources(dev, mask)) < 0)
307		return err;
308
309	return pcibios_plat_dev_init(dev);
310}
311
312void pcibios_fixup_bus(struct pci_bus *bus)
313{
314	struct pci_dev *dev = bus->self;
315
316	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
317	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
318		pci_read_bridge_bases(bus);
319	}
320}
321
322EXPORT_SYMBOL(PCIBIOS_MIN_IO);
323EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
324
325int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
326			enum pci_mmap_state mmap_state, int write_combine)
327{
328	unsigned long prot;
329
330	/*
331	 * I/O space can be accessed via normal processor loads and stores on
332	 * this platform but for now we elect not to do this and portable
333	 * drivers should not do this anyway.
334	 */
335	if (mmap_state == pci_mmap_io)
336		return -EINVAL;
337
338	/*
339	 * Ignore write-combine; for now only return uncached mappings.
340	 */
341	prot = pgprot_val(vma->vm_page_prot);
342	prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
343	vma->vm_page_prot = __pgprot(prot);
344
345	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
346		vma->vm_end - vma->vm_start, vma->vm_page_prot);
347}
348
349char * (*pcibios_plat_setup)(char *str) __initdata;
350
351char *__init pcibios_setup(char *str)
352{
353	if (pcibios_plat_setup)
354		return pcibios_plat_setup(str);
355	return str;
356}
357