1#ifndef __ASM_POWERPC_PCI_H
2#define __ASM_POWERPC_PCI_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/types.h>
13#include <linux/slab.h>
14#include <linux/string.h>
15#include <linux/dma-mapping.h>
16
17#include <asm/machdep.h>
18#include <asm/scatterlist.h>
19#include <asm/io.h>
20#include <asm/prom.h>
21#include <asm/pci-bridge.h>
22
23#include <asm-generic/pci-dma-compat.h>
24
25/* Return values for pci_controller_ops.probe_mode function */
26#define PCI_PROBE_NONE		-1	/* Don't look at this bus at all */
27#define PCI_PROBE_NORMAL	0	/* Do normal PCI probing */
28#define PCI_PROBE_DEVTREE	1	/* Instantiate from device tree */
29
30#define PCIBIOS_MIN_IO		0x1000
31#define PCIBIOS_MIN_MEM		0x10000000
32
33struct pci_dev;
34
35/* Values for the `which' argument to sys_pciconfig_iobase syscall.  */
36#define IOBASE_BRIDGE_NUMBER	0
37#define IOBASE_MEMORY		1
38#define IOBASE_IO		2
39#define IOBASE_ISA_IO		3
40#define IOBASE_ISA_MEM		4
41
42/*
43 * Set this to 1 if you want the kernel to re-assign all PCI
44 * bus numbers (don't do that on ppc64 yet !)
45 */
46#define pcibios_assign_all_busses() \
47	(pci_has_flag(PCI_REASSIGN_ALL_BUS))
48
49#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
50static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
51{
52	if (ppc_md.pci_get_legacy_ide_irq)
53		return ppc_md.pci_get_legacy_ide_irq(dev, channel);
54	return channel ? 15 : 14;
55}
56
57#ifdef CONFIG_PCI
58extern void set_pci_dma_ops(struct dma_map_ops *dma_ops);
59extern struct dma_map_ops *get_pci_dma_ops(void);
60#else	/* CONFIG_PCI */
61#define set_pci_dma_ops(d)
62#define get_pci_dma_ops()	NULL
63#endif
64
65#ifdef CONFIG_PPC64
66
67/*
68 * We want to avoid touching the cacheline size or MWI bit.
69 * pSeries firmware sets the cacheline size (which is not the cpu cacheline
70 * size in all cases) and hardware treats MWI the same as memory write.
71 */
72#define PCI_DISABLE_MWI
73
74#ifdef CONFIG_PCI
75static inline void pci_dma_burst_advice(struct pci_dev *pdev,
76					enum pci_dma_burst_strategy *strat,
77					unsigned long *strategy_parameter)
78{
79	unsigned long cacheline_size;
80	u8 byte;
81
82	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
83	if (byte == 0)
84		cacheline_size = 1024;
85	else
86		cacheline_size = (int) byte * 4;
87
88	*strat = PCI_DMA_BURST_MULTIPLE;
89	*strategy_parameter = cacheline_size;
90}
91#endif
92
93#else /* 32-bit */
94
95#ifdef CONFIG_PCI
96static inline void pci_dma_burst_advice(struct pci_dev *pdev,
97					enum pci_dma_burst_strategy *strat,
98					unsigned long *strategy_parameter)
99{
100	*strat = PCI_DMA_BURST_INFINITY;
101	*strategy_parameter = ~0UL;
102}
103#endif
104#endif /* CONFIG_PPC64 */
105
106extern int pci_domain_nr(struct pci_bus *bus);
107
108/* Decide whether to display the domain number in /proc */
109extern int pci_proc_domain(struct pci_bus *bus);
110
111struct vm_area_struct;
112/* Map a range of PCI memory or I/O space for a device into user space */
113int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
114			enum pci_mmap_state mmap_state, int write_combine);
115
116/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
117#define HAVE_PCI_MMAP	1
118
119extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
120			   size_t count);
121extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
122			   size_t count);
123extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
124				      struct vm_area_struct *vma,
125				      enum pci_mmap_state mmap_state);
126
127#define HAVE_PCI_LEGACY	1
128
129#ifdef CONFIG_PPC64
130
131/* The PCI address space does not equal the physical memory address
132 * space (we have an IOMMU).  The IDE and SCSI device layers use
133 * this boolean for bounce buffer decisions.
134 */
135#define PCI_DMA_BUS_IS_PHYS	(0)
136
137#else /* 32-bit */
138
139/* The PCI address space does equal the physical memory
140 * address space (no IOMMU).  The IDE and SCSI device layers use
141 * this boolean for bounce buffer decisions.
142 */
143#define PCI_DMA_BUS_IS_PHYS     (1)
144
145#endif /* CONFIG_PPC64 */
146
147extern void pcibios_claim_one_bus(struct pci_bus *b);
148
149extern void pcibios_finish_adding_to_bus(struct pci_bus *bus);
150
151extern void pcibios_resource_survey(void);
152
153extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
154extern int remove_phb_dynamic(struct pci_controller *phb);
155
156extern struct pci_dev *of_create_pci_dev(struct device_node *node,
157					struct pci_bus *bus, int devfn);
158
159extern void of_scan_pci_bridge(struct pci_dev *dev);
160
161extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
162extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
163
164struct file;
165extern pgprot_t	pci_phys_mem_access_prot(struct file *file,
166					 unsigned long pfn,
167					 unsigned long size,
168					 pgprot_t prot);
169
170#define HAVE_ARCH_PCI_RESOURCE_TO_USER
171extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
172				 const struct resource *rsrc,
173				 resource_size_t *start, resource_size_t *end);
174
175extern resource_size_t pcibios_io_space_offset(struct pci_controller *hose);
176extern void pcibios_setup_bus_devices(struct pci_bus *bus);
177extern void pcibios_setup_bus_self(struct pci_bus *bus);
178extern void pcibios_setup_phb_io_space(struct pci_controller *hose);
179extern void pcibios_scan_phb(struct pci_controller *hose);
180
181#endif	/* __KERNEL__ */
182#endif /* __ASM_POWERPC_PCI_H */
183