1/*
2 * Copyright 2007, Olof Johansson, PA Semi
3 *
4 * Based on arch/powerpc/sysdev/mpic_u3msi.c:
5 *
6 * Copyright 2006, Segher Boessenkool, IBM Corporation.
7 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 */
15
16#undef DEBUG
17
18#include <linux/irq.h>
19#include <linux/msi.h>
20#include <asm/mpic.h>
21#include <asm/prom.h>
22#include <asm/hw_irq.h>
23#include <asm/ppc-pci.h>
24#include <asm/msi_bitmap.h>
25
26#include "mpic.h"
27
28/* Allocate 16 interrupts per device, to give an alignment of 16,
29 * since that's the size of the grouping w.r.t. affinity. If someone
30 * needs more than 32 MSI's down the road we'll have to rethink this,
31 * but it should be OK for now.
32 */
33#define ALLOC_CHUNK 16
34
35#define PASEMI_MSI_ADDR 0xfc080000
36
37/* A bit ugly, can we get this from the pci_dev somehow? */
38static struct mpic *msi_mpic;
39
40
41static void mpic_pasemi_msi_mask_irq(struct irq_data *data)
42{
43	pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq);
44	pci_msi_mask_irq(data);
45	mpic_mask_irq(data);
46}
47
48static void mpic_pasemi_msi_unmask_irq(struct irq_data *data)
49{
50	pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq);
51	mpic_unmask_irq(data);
52	pci_msi_unmask_irq(data);
53}
54
55static struct irq_chip mpic_pasemi_msi_chip = {
56	.irq_shutdown		= mpic_pasemi_msi_mask_irq,
57	.irq_mask		= mpic_pasemi_msi_mask_irq,
58	.irq_unmask		= mpic_pasemi_msi_unmask_irq,
59	.irq_eoi		= mpic_end_irq,
60	.irq_set_type		= mpic_set_irq_type,
61	.irq_set_affinity	= mpic_set_affinity,
62	.name			= "PASEMI-MSI",
63};
64
65static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev)
66{
67	struct msi_desc *entry;
68	irq_hw_number_t hwirq;
69
70	pr_debug("pasemi_msi_teardown_msi_irqs, pdev %p\n", pdev);
71
72	list_for_each_entry(entry, &pdev->msi_list, list) {
73		if (entry->irq == NO_IRQ)
74			continue;
75
76		hwirq = virq_to_hw(entry->irq);
77		irq_set_msi_desc(entry->irq, NULL);
78		irq_dispose_mapping(entry->irq);
79		msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap,
80				       hwirq, ALLOC_CHUNK);
81	}
82
83	return;
84}
85
86static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
87{
88	unsigned int virq;
89	struct msi_desc *entry;
90	struct msi_msg msg;
91	int hwirq;
92
93	if (type == PCI_CAP_ID_MSIX)
94		pr_debug("pasemi_msi: MSI-X untested, trying anyway\n");
95	pr_debug("pasemi_msi_setup_msi_irqs, pdev %p nvec %d type %d\n",
96		 pdev, nvec, type);
97
98	msg.address_hi = 0;
99	msg.address_lo = PASEMI_MSI_ADDR;
100
101	list_for_each_entry(entry, &pdev->msi_list, list) {
102		/* Allocate 16 interrupts for now, since that's the grouping for
103		 * affinity. This can be changed later if it turns out 32 is too
104		 * few MSIs for someone, but restrictions will apply to how the
105		 * sources can be changed independently.
106		 */
107		hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap,
108						ALLOC_CHUNK);
109		if (hwirq < 0) {
110			pr_debug("pasemi_msi: failed allocating hwirq\n");
111			return hwirq;
112		}
113
114		virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
115		if (virq == NO_IRQ) {
116			pr_debug("pasemi_msi: failed mapping hwirq 0x%x\n",
117				  hwirq);
118			msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq,
119					       ALLOC_CHUNK);
120			return -ENOSPC;
121		}
122
123		/* Vector on MSI is really an offset, the hardware adds
124		 * it to the value written at the magic address. So set
125		 * it to 0 to remain sane.
126		 */
127		mpic_set_vector(virq, 0);
128
129		irq_set_msi_desc(virq, entry);
130		irq_set_chip(virq, &mpic_pasemi_msi_chip);
131		irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
132
133		pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \
134			 "addr 0x%x\n", virq, hwirq, msg.address_lo);
135
136		/* Likewise, the device writes [0...511] into the target
137		 * register to generate MSI [512...1023]
138		 */
139		msg.data = hwirq-0x200;
140		pci_write_msi_msg(virq, &msg);
141	}
142
143	return 0;
144}
145
146int mpic_pasemi_msi_init(struct mpic *mpic)
147{
148	int rc;
149
150	if (!mpic->irqhost->of_node ||
151	    !of_device_is_compatible(mpic->irqhost->of_node,
152				     "pasemi,pwrficient-openpic"))
153		return -ENODEV;
154
155	rc = mpic_msi_init_allocator(mpic);
156	if (rc) {
157		pr_debug("pasemi_msi: Error allocating bitmap!\n");
158		return rc;
159	}
160
161	pr_debug("pasemi_msi: Registering PA Semi MPIC MSI callbacks\n");
162
163	msi_mpic = mpic;
164	WARN_ON(ppc_md.setup_msi_irqs);
165	ppc_md.setup_msi_irqs = pasemi_msi_setup_msi_irqs;
166	ppc_md.teardown_msi_irqs = pasemi_msi_teardown_msi_irqs;
167
168	return 0;
169}
170