1#ifndef _ASM_X86_MCE_H 2#define _ASM_X86_MCE_H 3 4#include <uapi/asm/mce.h> 5 6/* 7 * Machine Check support for x86 8 */ 9 10/* MCG_CAP register defines */ 11#define MCG_BANKCNT_MASK 0xff /* Number of Banks */ 12#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ 13#define MCG_EXT_P (1ULL<<9) /* Extended registers available */ 14#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ 15#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ 16#define MCG_EXT_CNT_SHIFT 16 17#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) 18#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 19#define MCG_ELOG_P (1ULL<<26) /* Extended error log supported */ 20 21/* MCG_STATUS register defines */ 22#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 23#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 24#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 25 26/* MCi_STATUS register defines */ 27#define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 28#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 29#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 30#define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 31#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 32#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 33#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 34#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 35#define MCI_STATUS_AR (1ULL<<55) /* Action required */ 36 37/* AMD-specific bits */ 38#define MCI_STATUS_DEFERRED (1ULL<<44) /* declare an uncorrected error */ 39#define MCI_STATUS_POISON (1ULL<<43) /* access poisonous data */ 40 41/* 42 * Note that the full MCACOD field of IA32_MCi_STATUS MSR is 43 * bits 15:0. But bit 12 is the 'F' bit, defined for corrected 44 * errors to indicate that errors are being filtered by hardware. 45 * We should mask out bit 12 when looking for specific signatures 46 * of uncorrected errors - so the F bit is deliberately skipped 47 * in this #define. 48 */ 49#define MCACOD 0xefff /* MCA Error Code */ 50 51/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */ 52#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */ 53#define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */ 54#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */ 55#define MCACOD_DATA 0x0134 /* Data Load */ 56#define MCACOD_INSTR 0x0150 /* Instruction Fetch */ 57 58/* MCi_MISC register defines */ 59#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f) 60#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7) 61#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */ 62#define MCI_MISC_ADDR_LINEAR 1 /* linear address */ 63#define MCI_MISC_ADDR_PHYS 2 /* physical address */ 64#define MCI_MISC_ADDR_MEM 3 /* memory address */ 65#define MCI_MISC_ADDR_GENERIC 7 /* generic */ 66 67/* CTL2 register defines */ 68#define MCI_CTL2_CMCI_EN (1ULL << 30) 69#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL 70 71#define MCJ_CTX_MASK 3 72#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) 73#define MCJ_CTX_RANDOM 0 /* inject context: random */ 74#define MCJ_CTX_PROCESS 0x1 /* inject context: process */ 75#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */ 76#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */ 77#define MCJ_EXCEPTION 0x8 /* raise as exception */ 78#define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */ 79 80#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ 81 82/* Software defined banks */ 83#define MCE_EXTENDED_BANK 128 84#define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0) 85 86#define MCE_LOG_LEN 32 87#define MCE_LOG_SIGNATURE "MACHINECHECK" 88 89/* 90 * This structure contains all data related to the MCE log. Also 91 * carries a signature to make it easier to find from external 92 * debugging tools. Each entry is only valid when its finished flag 93 * is set. 94 */ 95struct mce_log { 96 char signature[12]; /* "MACHINECHECK" */ 97 unsigned len; /* = MCE_LOG_LEN */ 98 unsigned next; 99 unsigned flags; 100 unsigned recordlen; /* length of struct mce */ 101 struct mce entry[MCE_LOG_LEN]; 102}; 103 104struct mca_config { 105 bool dont_log_ce; 106 bool cmci_disabled; 107 bool ignore_ce; 108 bool disabled; 109 bool ser; 110 bool bios_cmci_threshold; 111 u8 banks; 112 s8 bootlog; 113 int tolerant; 114 int monarch_timeout; 115 int panic_timeout; 116 u32 rip_msr; 117}; 118 119struct mce_vendor_flags { 120 __u64 overflow_recov : 1, /* cpuid_ebx(80000007) */ 121 __reserved_0 : 63; 122}; 123extern struct mce_vendor_flags mce_flags; 124 125extern struct mca_config mca_cfg; 126extern void mce_register_decode_chain(struct notifier_block *nb); 127extern void mce_unregister_decode_chain(struct notifier_block *nb); 128 129#include <linux/percpu.h> 130#include <linux/atomic.h> 131 132extern int mce_p5_enabled; 133 134#ifdef CONFIG_X86_MCE 135int mcheck_init(void); 136void mcheck_cpu_init(struct cpuinfo_x86 *c); 137void mcheck_vendor_init_severity(void); 138#else 139static inline int mcheck_init(void) { return 0; } 140static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} 141static inline void mcheck_vendor_init_severity(void) {} 142#endif 143 144#ifdef CONFIG_X86_ANCIENT_MCE 145void intel_p5_mcheck_init(struct cpuinfo_x86 *c); 146void winchip_mcheck_init(struct cpuinfo_x86 *c); 147static inline void enable_p5_mce(void) { mce_p5_enabled = 1; } 148#else 149static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {} 150static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {} 151static inline void enable_p5_mce(void) {} 152#endif 153 154void mce_setup(struct mce *m); 155void mce_log(struct mce *m); 156DECLARE_PER_CPU(struct device *, mce_device); 157 158/* 159 * Maximum banks number. 160 * This is the limit of the current register layout on 161 * Intel CPUs. 162 */ 163#define MAX_NR_BANKS 32 164 165#ifdef CONFIG_X86_MCE_INTEL 166void mce_intel_feature_init(struct cpuinfo_x86 *c); 167void cmci_clear(void); 168void cmci_reenable(void); 169void cmci_rediscover(void); 170void cmci_recheck(void); 171#else 172static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } 173static inline void cmci_clear(void) {} 174static inline void cmci_reenable(void) {} 175static inline void cmci_rediscover(void) {} 176static inline void cmci_recheck(void) {} 177#endif 178 179#ifdef CONFIG_X86_MCE_AMD 180void mce_amd_feature_init(struct cpuinfo_x86 *c); 181#else 182static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } 183#endif 184 185int mce_available(struct cpuinfo_x86 *c); 186 187DECLARE_PER_CPU(unsigned, mce_exception_count); 188DECLARE_PER_CPU(unsigned, mce_poll_count); 189 190typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); 191DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); 192 193enum mcp_flags { 194 MCP_TIMESTAMP = BIT(0), /* log time stamp */ 195 MCP_UC = BIT(1), /* log uncorrected errors */ 196 MCP_DONTLOG = BIT(2), /* only clear, don't log */ 197}; 198bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b); 199 200int mce_notify_irq(void); 201 202DECLARE_PER_CPU(struct mce, injectm); 203 204extern void register_mce_write_callback(ssize_t (*)(struct file *filp, 205 const char __user *ubuf, 206 size_t usize, loff_t *off)); 207 208/* Disable CMCI/polling for MCA bank claimed by firmware */ 209extern void mce_disable_bank(int bank); 210 211/* 212 * Exception handler 213 */ 214 215/* Call the installed machine check handler for this CPU setup. */ 216extern void (*machine_check_vector)(struct pt_regs *, long error_code); 217void do_machine_check(struct pt_regs *, long); 218 219/* 220 * Threshold handler 221 */ 222 223extern void (*mce_threshold_vector)(void); 224extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); 225 226/* 227 * Thermal handler 228 */ 229 230void intel_init_thermal(struct cpuinfo_x86 *c); 231 232void mce_log_therm_throt_event(__u64 status); 233 234/* Interrupt Handler for core thermal thresholds */ 235extern int (*platform_thermal_notify)(__u64 msr_val); 236 237/* Interrupt Handler for package thermal thresholds */ 238extern int (*platform_thermal_package_notify)(__u64 msr_val); 239 240/* Callback support of rate control, return true, if 241 * callback has rate control */ 242extern bool (*platform_thermal_package_rate_control)(void); 243 244#ifdef CONFIG_X86_THERMAL_VECTOR 245extern void mcheck_intel_therm_init(void); 246#else 247static inline void mcheck_intel_therm_init(void) { } 248#endif 249 250/* 251 * Used by APEI to report memory error via /dev/mcelog 252 */ 253 254struct cper_sec_mem_err; 255extern void apei_mce_report_mem_error(int corrected, 256 struct cper_sec_mem_err *mem_err); 257 258#endif /* _ASM_X86_MCE_H */ 259