1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV Broadcast Assist Unit definitions 7 * 8 * Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11#ifndef _ASM_X86_UV_UV_BAU_H 12#define _ASM_X86_UV_UV_BAU_H 13 14#include <linux/bitmap.h> 15#define BITSPERBYTE 8 16 17/* 18 * Broadcast Assist Unit messaging structures 19 * 20 * Selective Broadcast activations are induced by software action 21 * specifying a particular 8-descriptor "set" via a 6-bit index written 22 * to an MMR. 23 * Thus there are 64 unique 512-byte sets of SB descriptors - one set for 24 * each 6-bit index value. These descriptor sets are mapped in sequence 25 * starting with set 0 located at the address specified in the 26 * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512, 27 * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on. 28 * 29 * We will use one set for sending BAU messages from each of the 30 * cpu's on the uvhub. 31 * 32 * TLB shootdown will use the first of the 8 descriptors of each set. 33 * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set). 34 */ 35 36#define MAX_CPUS_PER_UVHUB 128 37#define MAX_CPUS_PER_SOCKET 64 38#define ADP_SZ 64 /* hardware-provided max. */ 39#define UV_CPUS_PER_AS 32 /* hardware-provided max. */ 40#define ITEMS_PER_DESC 8 41/* the 'throttle' to prevent the hardware stay-busy bug */ 42#define MAX_BAU_CONCURRENT 3 43#define UV_ACT_STATUS_MASK 0x3 44#define UV_ACT_STATUS_SIZE 2 45#define UV_DISTRIBUTION_SIZE 256 46#define UV_SW_ACK_NPENDING 8 47#define UV1_NET_ENDPOINT_INTD 0x38 48#define UV2_NET_ENDPOINT_INTD 0x28 49#define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \ 50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD) 51#define UV_DESC_PSHIFT 49 52#define UV_PAYLOADQ_PNODE_SHIFT 49 53#define UV_PTC_BASENAME "sgi_uv/ptc_statistics" 54#define UV_BAU_BASENAME "sgi_uv/bau_tunables" 55#define UV_BAU_TUNABLES_DIR "sgi_uv" 56#define UV_BAU_TUNABLES_FILE "bau_tunables" 57#define WHITESPACE " \t\n" 58#define uv_mmask ((1UL << uv_hub_info->m_val) - 1) 59#define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask)) 60#define cpubit_isset(cpu, bau_local_cpumask) \ 61 test_bit((cpu), (bau_local_cpumask).bits) 62 63/* [19:16] SOFT_ACK timeout period 19: 1 is urgency 7 17:16 1 is multiplier */ 64/* 65 * UV2: Bit 19 selects between 66 * (0): 10 microsecond timebase and 67 * (1): 80 microseconds 68 * we're using 560us, similar to UV1: 65 units of 10us 69 */ 70#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL) 71#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL) 72 73#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \ 74 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \ 75 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD) 76/* assuming UV3 is the same */ 77 78#define BAU_MISC_CONTROL_MULT_MASK 3 79 80#define UVH_AGING_PRESCALE_SEL 0x000000b000UL 81/* [30:28] URGENCY_7 an index into a table of times */ 82#define BAU_URGENCY_7_SHIFT 28 83#define BAU_URGENCY_7_MASK 7 84 85#define UVH_TRANSACTION_TIMEOUT 0x000000b200UL 86/* [45:40] BAU - BAU transaction timeout select - a multiplier */ 87#define BAU_TRANS_SHIFT 40 88#define BAU_TRANS_MASK 0x3f 89 90/* 91 * shorten some awkward names 92 */ 93#define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 94#define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 95#define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 96#define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD 97#define PREFETCH_HINT_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT 98#define SB_STATUS_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 99#define write_gmmr uv_write_global_mmr64 100#define write_lmmr uv_write_local_mmr 101#define read_lmmr uv_read_local_mmr 102#define read_gmmr uv_read_global_mmr64 103 104/* 105 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1 106 */ 107#define DS_IDLE 0 108#define DS_ACTIVE 1 109#define DS_DESTINATION_TIMEOUT 2 110#define DS_SOURCE_TIMEOUT 3 111/* 112 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2 113 * values 1 and 3 will not occur 114 * Decoded meaning ERROR BUSY AUX ERR 115 * ------------------------------- ---- ----- ------- 116 * IDLE 0 0 0 117 * BUSY (active) 0 1 0 118 * SW Ack Timeout (destination) 1 0 0 119 * SW Ack INTD rejected (strong NACK) 1 0 1 120 * Source Side Time Out Detected 1 1 0 121 * Destination Side PUT Failed 1 1 1 122 */ 123#define UV2H_DESC_IDLE 0 124#define UV2H_DESC_BUSY 2 125#define UV2H_DESC_DEST_TIMEOUT 4 126#define UV2H_DESC_DEST_STRONG_NACK 5 127#define UV2H_DESC_SOURCE_TIMEOUT 6 128#define UV2H_DESC_DEST_PUT_ERR 7 129 130/* 131 * delay for 'plugged' timeout retries, in microseconds 132 */ 133#define PLUGGED_DELAY 10 134 135/* 136 * threshholds at which to use IPI to free resources 137 */ 138/* after this # consecutive 'plugged' timeouts, use IPI to release resources */ 139#define PLUGSB4RESET 100 140/* after this many consecutive timeouts, use IPI to release resources */ 141#define TIMEOUTSB4RESET 1 142/* at this number uses of IPI to release resources, giveup the request */ 143#define IPI_RESET_LIMIT 1 144/* after this # consecutive successes, bump up the throttle if it was lowered */ 145#define COMPLETE_THRESHOLD 5 146/* after this # of giveups (fall back to kernel IPI's) disable the use of 147 the BAU for a period of time */ 148#define GIVEUP_LIMIT 100 149 150#define UV_LB_SUBNODEID 0x10 151 152/* these two are the same for UV1 and UV2: */ 153#define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 154#define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 155/* 4 bits of software ack period */ 156#define UV2_ACK_MASK 0x7UL 157#define UV2_ACK_UNITS_SHFT 3 158#define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 159 160/* 161 * number of entries in the destination side payload queue 162 */ 163#define DEST_Q_SIZE 20 164/* 165 * number of destination side software ack resources 166 */ 167#define DEST_NUM_RESOURCES 8 168/* 169 * completion statuses for sending a TLB flush message 170 */ 171#define FLUSH_RETRY_PLUGGED 1 172#define FLUSH_RETRY_TIMEOUT 2 173#define FLUSH_GIVEUP 3 174#define FLUSH_COMPLETE 4 175 176/* 177 * tuning the action when the numalink network is extremely delayed 178 */ 179#define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in 180 microseconds */ 181#define CONGESTED_REPS 10 /* long delays averaged over 182 this many broadcasts */ 183#define DISABLED_PERIOD 10 /* time for the bau to be 184 disabled, in seconds */ 185/* see msg_type: */ 186#define MSG_NOOP 0 187#define MSG_REGULAR 1 188#define MSG_RETRY 2 189 190/* 191 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor) 192 * If the 'multilevel' flag in the header portion of the descriptor 193 * has been set to 0, then endpoint multi-unicast mode is selected. 194 * The distribution specification (32 bytes) is interpreted as a 256-bit 195 * distribution vector. Adjacent bits correspond to consecutive even numbered 196 * nodeIDs. The result of adding the index of a given bit to the 15-bit 197 * 'base_dest_nasid' field of the header corresponds to the 198 * destination nodeID associated with that specified bit. 199 */ 200struct pnmask { 201 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)]; 202}; 203 204/* 205 * mask of cpu's on a uvhub 206 * (during initialization we need to check that unsigned long has 207 * enough bits for max. cpu's per uvhub) 208 */ 209struct bau_local_cpumask { 210 unsigned long bits; 211}; 212 213/* 214 * Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor) 215 * only 12 bytes (96 bits) of the payload area are usable. 216 * An additional 3 bytes (bits 27:4) of the header address are carried 217 * to the next bytes of the destination payload queue. 218 * And an additional 2 bytes of the header Suppl_A field are also 219 * carried to the destination payload queue. 220 * But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte) 221 * of the destination payload queue, which is written by the hardware 222 * with the s/w ack resource bit vector. 223 * [ effective message contents (16 bytes (128 bits) maximum), not counting 224 * the s/w ack bit vector ] 225 */ 226 227/* 228 * The payload is software-defined for INTD transactions 229 */ 230struct bau_msg_payload { 231 unsigned long address; /* signifies a page or all 232 TLB's of the cpu */ 233 /* 64 bits */ 234 unsigned short sending_cpu; /* filled in by sender */ 235 /* 16 bits */ 236 unsigned short acknowledge_count; /* filled in by destination */ 237 /* 16 bits */ 238 unsigned int reserved1:32; /* not usable */ 239}; 240 241 242/* 243 * UV1 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor) 244 * see table 4.2.3.0.1 in broacast_assist spec. 245 */ 246struct uv1_bau_msg_header { 247 unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */ 248 /* bits 5:0 */ 249 unsigned int base_dest_nasid:15; /* nasid of the first bit */ 250 /* bits 20:6 */ /* in uvhub map */ 251 unsigned int command:8; /* message type */ 252 /* bits 28:21 */ 253 /* 0x38: SN3net EndPoint Message */ 254 unsigned int rsvd_1:3; /* must be zero */ 255 /* bits 31:29 */ 256 /* int will align on 32 bits */ 257 unsigned int rsvd_2:9; /* must be zero */ 258 /* bits 40:32 */ 259 /* Suppl_A is 56-41 */ 260 unsigned int sequence:16; /* message sequence number */ 261 /* bits 56:41 */ /* becomes bytes 16-17 of msg */ 262 /* Address field (96:57) is 263 never used as an address 264 (these are address bits 265 42:3) */ 266 267 unsigned int rsvd_3:1; /* must be zero */ 268 /* bit 57 */ 269 /* address bits 27:4 are payload */ 270 /* these next 24 (58-81) bits become bytes 12-14 of msg */ 271 /* bits 65:58 land in byte 12 */ 272 unsigned int replied_to:1; /* sent as 0 by the source to 273 byte 12 */ 274 /* bit 58 */ 275 unsigned int msg_type:3; /* software type of the 276 message */ 277 /* bits 61:59 */ 278 unsigned int canceled:1; /* message canceled, resource 279 is to be freed*/ 280 /* bit 62 */ 281 unsigned int payload_1a:1; /* not currently used */ 282 /* bit 63 */ 283 unsigned int payload_1b:2; /* not currently used */ 284 /* bits 65:64 */ 285 286 /* bits 73:66 land in byte 13 */ 287 unsigned int payload_1ca:6; /* not currently used */ 288 /* bits 71:66 */ 289 unsigned int payload_1c:2; /* not currently used */ 290 /* bits 73:72 */ 291 292 /* bits 81:74 land in byte 14 */ 293 unsigned int payload_1d:6; /* not currently used */ 294 /* bits 79:74 */ 295 unsigned int payload_1e:2; /* not currently used */ 296 /* bits 81:80 */ 297 298 unsigned int rsvd_4:7; /* must be zero */ 299 /* bits 88:82 */ 300 unsigned int swack_flag:1; /* software acknowledge flag */ 301 /* bit 89 */ 302 /* INTD trasactions at 303 destination are to wait for 304 software acknowledge */ 305 unsigned int rsvd_5:6; /* must be zero */ 306 /* bits 95:90 */ 307 unsigned int rsvd_6:5; /* must be zero */ 308 /* bits 100:96 */ 309 unsigned int int_both:1; /* if 1, interrupt both sockets 310 on the uvhub */ 311 /* bit 101*/ 312 unsigned int fairness:3; /* usually zero */ 313 /* bits 104:102 */ 314 unsigned int multilevel:1; /* multi-level multicast 315 format */ 316 /* bit 105 */ 317 /* 0 for TLB: endpoint multi-unicast messages */ 318 unsigned int chaining:1; /* next descriptor is part of 319 this activation*/ 320 /* bit 106 */ 321 unsigned int rsvd_7:21; /* must be zero */ 322 /* bits 127:107 */ 323}; 324 325/* 326 * UV2 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor) 327 * see figure 9-2 of harp_sys.pdf 328 * assuming UV3 is the same 329 */ 330struct uv2_3_bau_msg_header { 331 unsigned int base_dest_nasid:15; /* nasid of the first bit */ 332 /* bits 14:0 */ /* in uvhub map */ 333 unsigned int dest_subnodeid:5; /* must be 0x10, for the LB */ 334 /* bits 19:15 */ 335 unsigned int rsvd_1:1; /* must be zero */ 336 /* bit 20 */ 337 /* Address bits 59:21 */ 338 /* bits 25:2 of address (44:21) are payload */ 339 /* these next 24 bits become bytes 12-14 of msg */ 340 /* bits 28:21 land in byte 12 */ 341 unsigned int replied_to:1; /* sent as 0 by the source to 342 byte 12 */ 343 /* bit 21 */ 344 unsigned int msg_type:3; /* software type of the 345 message */ 346 /* bits 24:22 */ 347 unsigned int canceled:1; /* message canceled, resource 348 is to be freed*/ 349 /* bit 25 */ 350 unsigned int payload_1:3; /* not currently used */ 351 /* bits 28:26 */ 352 353 /* bits 36:29 land in byte 13 */ 354 unsigned int payload_2a:3; /* not currently used */ 355 unsigned int payload_2b:5; /* not currently used */ 356 /* bits 36:29 */ 357 358 /* bits 44:37 land in byte 14 */ 359 unsigned int payload_3:8; /* not currently used */ 360 /* bits 44:37 */ 361 362 unsigned int rsvd_2:7; /* reserved */ 363 /* bits 51:45 */ 364 unsigned int swack_flag:1; /* software acknowledge flag */ 365 /* bit 52 */ 366 unsigned int rsvd_3a:3; /* must be zero */ 367 unsigned int rsvd_3b:8; /* must be zero */ 368 unsigned int rsvd_3c:8; /* must be zero */ 369 unsigned int rsvd_3d:3; /* must be zero */ 370 /* bits 74:53 */ 371 unsigned int fairness:3; /* usually zero */ 372 /* bits 77:75 */ 373 374 unsigned int sequence:16; /* message sequence number */ 375 /* bits 93:78 Suppl_A */ 376 unsigned int chaining:1; /* next descriptor is part of 377 this activation*/ 378 /* bit 94 */ 379 unsigned int multilevel:1; /* multi-level multicast 380 format */ 381 /* bit 95 */ 382 unsigned int rsvd_4:24; /* ordered / source node / 383 source subnode / aging 384 must be zero */ 385 /* bits 119:96 */ 386 unsigned int command:8; /* message type */ 387 /* bits 127:120 */ 388}; 389 390/* 391 * The activation descriptor: 392 * The format of the message to send, plus all accompanying control 393 * Should be 64 bytes 394 */ 395struct bau_desc { 396 struct pnmask distribution; 397 /* 398 * message template, consisting of header and payload: 399 */ 400 union bau_msg_header { 401 struct uv1_bau_msg_header uv1_hdr; 402 struct uv2_3_bau_msg_header uv2_3_hdr; 403 } header; 404 405 struct bau_msg_payload payload; 406}; 407/* UV1: 408 * -payload-- ---------header------ 409 * bytes 0-11 bits 41-56 bits 58-81 410 * A B (2) C (3) 411 * 412 * A/B/C are moved to: 413 * A C B 414 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector) 415 * ------------payload queue----------- 416 */ 417/* UV2: 418 * -payload-- ---------header------ 419 * bytes 0-11 bits 70-78 bits 21-44 420 * A B (2) C (3) 421 * 422 * A/B/C are moved to: 423 * A C B 424 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector) 425 * ------------payload queue----------- 426 */ 427 428/* 429 * The payload queue on the destination side is an array of these. 430 * With BAU_MISC_CONTROL set for software acknowledge mode, the messages 431 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17 432 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120) 433 * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from 434 * swack_vec and payload_2) 435 * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software 436 * Acknowledge Processing) also selects 32 byte (17 bytes usable) payload 437 * operation." 438 */ 439struct bau_pq_entry { 440 unsigned long address; /* signifies a page or all TLB's 441 of the cpu */ 442 /* 64 bits, bytes 0-7 */ 443 unsigned short sending_cpu; /* cpu that sent the message */ 444 /* 16 bits, bytes 8-9 */ 445 unsigned short acknowledge_count; /* filled in by destination */ 446 /* 16 bits, bytes 10-11 */ 447 /* these next 3 bytes come from bits 58-81 of the message header */ 448 unsigned short replied_to:1; /* sent as 0 by the source */ 449 unsigned short msg_type:3; /* software message type */ 450 unsigned short canceled:1; /* sent as 0 by the source */ 451 unsigned short unused1:3; /* not currently using */ 452 /* byte 12 */ 453 unsigned char unused2a; /* not currently using */ 454 /* byte 13 */ 455 unsigned char unused2; /* not currently using */ 456 /* byte 14 */ 457 unsigned char swack_vec; /* filled in by the hardware */ 458 /* byte 15 (bits 127:120) */ 459 unsigned short sequence; /* message sequence number */ 460 /* bytes 16-17 */ 461 unsigned char unused4[2]; /* not currently using bytes 18-19 */ 462 /* bytes 18-19 */ 463 int number_of_cpus; /* filled in at destination */ 464 /* 32 bits, bytes 20-23 (aligned) */ 465 unsigned char unused5[8]; /* not using */ 466 /* bytes 24-31 */ 467}; 468 469struct msg_desc { 470 struct bau_pq_entry *msg; 471 int msg_slot; 472 struct bau_pq_entry *queue_first; 473 struct bau_pq_entry *queue_last; 474}; 475 476struct reset_args { 477 int sender; 478}; 479 480/* 481 * This structure is allocated per_cpu for UV TLB shootdown statistics. 482 */ 483struct ptc_stats { 484 /* sender statistics */ 485 unsigned long s_giveup; /* number of fall backs to 486 IPI-style flushes */ 487 unsigned long s_requestor; /* number of shootdown 488 requests */ 489 unsigned long s_stimeout; /* source side timeouts */ 490 unsigned long s_dtimeout; /* destination side timeouts */ 491 unsigned long s_strongnacks; /* number of strong nack's */ 492 unsigned long s_time; /* time spent in sending side */ 493 unsigned long s_retriesok; /* successful retries */ 494 unsigned long s_ntargcpu; /* total number of cpu's 495 targeted */ 496 unsigned long s_ntargself; /* times the sending cpu was 497 targeted */ 498 unsigned long s_ntarglocals; /* targets of cpus on the local 499 blade */ 500 unsigned long s_ntargremotes; /* targets of cpus on remote 501 blades */ 502 unsigned long s_ntarglocaluvhub; /* targets of the local hub */ 503 unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */ 504 unsigned long s_ntarguvhub; /* total number of uvhubs 505 targeted */ 506 unsigned long s_ntarguvhub16; /* number of times target 507 hubs >= 16*/ 508 unsigned long s_ntarguvhub8; /* number of times target 509 hubs >= 8 */ 510 unsigned long s_ntarguvhub4; /* number of times target 511 hubs >= 4 */ 512 unsigned long s_ntarguvhub2; /* number of times target 513 hubs >= 2 */ 514 unsigned long s_ntarguvhub1; /* number of times target 515 hubs == 1 */ 516 unsigned long s_resets_plug; /* ipi-style resets from plug 517 state */ 518 unsigned long s_resets_timeout; /* ipi-style resets from 519 timeouts */ 520 unsigned long s_busy; /* status stayed busy past 521 s/w timer */ 522 unsigned long s_throttles; /* waits in throttle */ 523 unsigned long s_retry_messages; /* retry broadcasts */ 524 unsigned long s_bau_reenabled; /* for bau enable/disable */ 525 unsigned long s_bau_disabled; /* for bau enable/disable */ 526 unsigned long s_uv2_wars; /* uv2 workaround, perm. busy */ 527 unsigned long s_uv2_wars_hw; /* uv2 workaround, hiwater */ 528 unsigned long s_uv2_war_waits; /* uv2 workaround, long waits */ 529 unsigned long s_overipilimit; /* over the ipi reset limit */ 530 unsigned long s_giveuplimit; /* disables, over giveup limit*/ 531 unsigned long s_enters; /* entries to the driver */ 532 unsigned long s_ipifordisabled; /* fall back to IPI; disabled */ 533 unsigned long s_plugged; /* plugged by h/w bug*/ 534 unsigned long s_congested; /* giveup on long wait */ 535 /* destination statistics */ 536 unsigned long d_alltlb; /* times all tlb's on this 537 cpu were flushed */ 538 unsigned long d_onetlb; /* times just one tlb on this 539 cpu was flushed */ 540 unsigned long d_multmsg; /* interrupts with multiple 541 messages */ 542 unsigned long d_nomsg; /* interrupts with no message */ 543 unsigned long d_time; /* time spent on destination 544 side */ 545 unsigned long d_requestee; /* number of messages 546 processed */ 547 unsigned long d_retries; /* number of retry messages 548 processed */ 549 unsigned long d_canceled; /* number of messages canceled 550 by retries */ 551 unsigned long d_nocanceled; /* retries that found nothing 552 to cancel */ 553 unsigned long d_resets; /* number of ipi-style requests 554 processed */ 555 unsigned long d_rcanceled; /* number of messages canceled 556 by resets */ 557}; 558 559struct tunables { 560 int *tunp; 561 int deflt; 562}; 563 564struct hub_and_pnode { 565 short uvhub; 566 short pnode; 567}; 568 569struct socket_desc { 570 short num_cpus; 571 short cpu_number[MAX_CPUS_PER_SOCKET]; 572}; 573 574struct uvhub_desc { 575 unsigned short socket_mask; 576 short num_cpus; 577 short uvhub; 578 short pnode; 579 struct socket_desc socket[2]; 580}; 581 582/* 583 * one per-cpu; to locate the software tables 584 */ 585struct bau_control { 586 struct bau_desc *descriptor_base; 587 struct bau_pq_entry *queue_first; 588 struct bau_pq_entry *queue_last; 589 struct bau_pq_entry *bau_msg_head; 590 struct bau_control *uvhub_master; 591 struct bau_control *socket_master; 592 struct ptc_stats *statp; 593 cpumask_t *cpumask; 594 unsigned long timeout_interval; 595 unsigned long set_bau_on_time; 596 atomic_t active_descriptor_count; 597 int plugged_tries; 598 int timeout_tries; 599 int ipi_attempts; 600 int conseccompletes; 601 short nobau; 602 short baudisabled; 603 short cpu; 604 short osnode; 605 short uvhub_cpu; 606 short uvhub; 607 short uvhub_version; 608 short cpus_in_socket; 609 short cpus_in_uvhub; 610 short partition_base_pnode; 611 short busy; /* all were busy (war) */ 612 unsigned short message_number; 613 unsigned short uvhub_quiesce; 614 short socket_acknowledge_count[DEST_Q_SIZE]; 615 cycles_t send_message; 616 cycles_t period_end; 617 cycles_t period_time; 618 spinlock_t uvhub_lock; 619 spinlock_t queue_lock; 620 spinlock_t disable_lock; 621 /* tunables */ 622 int max_concurr; 623 int max_concurr_const; 624 int plugged_delay; 625 int plugsb4reset; 626 int timeoutsb4reset; 627 int ipi_reset_limit; 628 int complete_threshold; 629 int cong_response_us; 630 int cong_reps; 631 cycles_t disabled_period; 632 int period_giveups; 633 int giveup_limit; 634 long period_requests; 635 struct hub_and_pnode *thp; 636}; 637 638static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image) 639{ 640 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image); 641} 642 643static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image) 644{ 645 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image); 646} 647 648static inline void write_mmr_activation(unsigned long index) 649{ 650 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index); 651} 652 653static inline void write_gmmr_activation(int pnode, unsigned long mmr_image) 654{ 655 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image); 656} 657 658static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image) 659{ 660 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image); 661} 662 663static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image) 664{ 665 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image); 666} 667 668static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image) 669{ 670 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image); 671} 672 673static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image) 674{ 675 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image); 676} 677 678static inline unsigned long read_mmr_misc_control(int pnode) 679{ 680 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL); 681} 682 683static inline void write_mmr_sw_ack(unsigned long mr) 684{ 685 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr); 686} 687 688static inline void write_gmmr_sw_ack(int pnode, unsigned long mr) 689{ 690 write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr); 691} 692 693static inline unsigned long read_mmr_sw_ack(void) 694{ 695 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); 696} 697 698static inline unsigned long read_gmmr_sw_ack(int pnode) 699{ 700 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); 701} 702 703static inline void write_mmr_data_config(int pnode, unsigned long mr) 704{ 705 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr); 706} 707 708static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp) 709{ 710 return constant_test_bit(uvhub, &dstp->bits[0]); 711} 712static inline void bau_uvhub_set(int pnode, struct pnmask *dstp) 713{ 714 __set_bit(pnode, &dstp->bits[0]); 715} 716static inline void bau_uvhubs_clear(struct pnmask *dstp, 717 int nbits) 718{ 719 bitmap_zero(&dstp->bits[0], nbits); 720} 721static inline int bau_uvhub_weight(struct pnmask *dstp) 722{ 723 return bitmap_weight((unsigned long *)&dstp->bits[0], 724 UV_DISTRIBUTION_SIZE); 725} 726 727static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits) 728{ 729 bitmap_zero(&dstp->bits, nbits); 730} 731 732extern void uv_bau_message_intr1(void); 733#ifdef CONFIG_TRACING 734#define trace_uv_bau_message_intr1 uv_bau_message_intr1 735#endif 736extern void uv_bau_timeout_intr1(void); 737 738struct atomic_short { 739 short counter; 740}; 741 742/* 743 * atomic_read_short - read a short atomic variable 744 * @v: pointer of type atomic_short 745 * 746 * Atomically reads the value of @v. 747 */ 748static inline int atomic_read_short(const struct atomic_short *v) 749{ 750 return v->counter; 751} 752 753/* 754 * atom_asr - add and return a short int 755 * @i: short value to add 756 * @v: pointer of type atomic_short 757 * 758 * Atomically adds @i to @v and returns @i + @v 759 */ 760static inline int atom_asr(short i, struct atomic_short *v) 761{ 762 short __i = i; 763 asm volatile(LOCK_PREFIX "xaddw %0, %1" 764 : "+r" (i), "+m" (v->counter) 765 : : "memory"); 766 return i + __i; 767} 768 769/* 770 * conditionally add 1 to *v, unless *v is >= u 771 * return 0 if we cannot add 1 to *v because it is >= u 772 * return 1 if we can add 1 to *v because it is < u 773 * the add is atomic 774 * 775 * This is close to atomic_add_unless(), but this allows the 'u' value 776 * to be lowered below the current 'v'. atomic_add_unless can only stop 777 * on equal. 778 */ 779static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u) 780{ 781 spin_lock(lock); 782 if (atomic_read(v) >= u) { 783 spin_unlock(lock); 784 return 0; 785 } 786 atomic_inc(v); 787 spin_unlock(lock); 788 return 1; 789} 790 791#endif /* _ASM_X86_UV_UV_BAU_H */ 792