1#ifndef _UAPI_ASM_X86_PROCESSOR_FLAGS_H 2#define _UAPI_ASM_X86_PROCESSOR_FLAGS_H 3/* Various flags defined: can be included from assembler. */ 4 5#include <linux/const.h> 6 7/* 8 * EFLAGS bits 9 */ 10#define X86_EFLAGS_CF_BIT 0 /* Carry Flag */ 11#define X86_EFLAGS_CF _BITUL(X86_EFLAGS_CF_BIT) 12#define X86_EFLAGS_FIXED_BIT 1 /* Bit 1 - always on */ 13#define X86_EFLAGS_FIXED _BITUL(X86_EFLAGS_FIXED_BIT) 14#define X86_EFLAGS_PF_BIT 2 /* Parity Flag */ 15#define X86_EFLAGS_PF _BITUL(X86_EFLAGS_PF_BIT) 16#define X86_EFLAGS_AF_BIT 4 /* Auxiliary carry Flag */ 17#define X86_EFLAGS_AF _BITUL(X86_EFLAGS_AF_BIT) 18#define X86_EFLAGS_ZF_BIT 6 /* Zero Flag */ 19#define X86_EFLAGS_ZF _BITUL(X86_EFLAGS_ZF_BIT) 20#define X86_EFLAGS_SF_BIT 7 /* Sign Flag */ 21#define X86_EFLAGS_SF _BITUL(X86_EFLAGS_SF_BIT) 22#define X86_EFLAGS_TF_BIT 8 /* Trap Flag */ 23#define X86_EFLAGS_TF _BITUL(X86_EFLAGS_TF_BIT) 24#define X86_EFLAGS_IF_BIT 9 /* Interrupt Flag */ 25#define X86_EFLAGS_IF _BITUL(X86_EFLAGS_IF_BIT) 26#define X86_EFLAGS_DF_BIT 10 /* Direction Flag */ 27#define X86_EFLAGS_DF _BITUL(X86_EFLAGS_DF_BIT) 28#define X86_EFLAGS_OF_BIT 11 /* Overflow Flag */ 29#define X86_EFLAGS_OF _BITUL(X86_EFLAGS_OF_BIT) 30#define X86_EFLAGS_IOPL_BIT 12 /* I/O Privilege Level (2 bits) */ 31#define X86_EFLAGS_IOPL (_AC(3,UL) << X86_EFLAGS_IOPL_BIT) 32#define X86_EFLAGS_NT_BIT 14 /* Nested Task */ 33#define X86_EFLAGS_NT _BITUL(X86_EFLAGS_NT_BIT) 34#define X86_EFLAGS_RF_BIT 16 /* Resume Flag */ 35#define X86_EFLAGS_RF _BITUL(X86_EFLAGS_RF_BIT) 36#define X86_EFLAGS_VM_BIT 17 /* Virtual Mode */ 37#define X86_EFLAGS_VM _BITUL(X86_EFLAGS_VM_BIT) 38#define X86_EFLAGS_AC_BIT 18 /* Alignment Check/Access Control */ 39#define X86_EFLAGS_AC _BITUL(X86_EFLAGS_AC_BIT) 40#define X86_EFLAGS_AC_BIT 18 /* Alignment Check/Access Control */ 41#define X86_EFLAGS_AC _BITUL(X86_EFLAGS_AC_BIT) 42#define X86_EFLAGS_VIF_BIT 19 /* Virtual Interrupt Flag */ 43#define X86_EFLAGS_VIF _BITUL(X86_EFLAGS_VIF_BIT) 44#define X86_EFLAGS_VIP_BIT 20 /* Virtual Interrupt Pending */ 45#define X86_EFLAGS_VIP _BITUL(X86_EFLAGS_VIP_BIT) 46#define X86_EFLAGS_ID_BIT 21 /* CPUID detection */ 47#define X86_EFLAGS_ID _BITUL(X86_EFLAGS_ID_BIT) 48 49/* 50 * Basic CPU control in CR0 51 */ 52#define X86_CR0_PE_BIT 0 /* Protection Enable */ 53#define X86_CR0_PE _BITUL(X86_CR0_PE_BIT) 54#define X86_CR0_MP_BIT 1 /* Monitor Coprocessor */ 55#define X86_CR0_MP _BITUL(X86_CR0_MP_BIT) 56#define X86_CR0_EM_BIT 2 /* Emulation */ 57#define X86_CR0_EM _BITUL(X86_CR0_EM_BIT) 58#define X86_CR0_TS_BIT 3 /* Task Switched */ 59#define X86_CR0_TS _BITUL(X86_CR0_TS_BIT) 60#define X86_CR0_ET_BIT 4 /* Extension Type */ 61#define X86_CR0_ET _BITUL(X86_CR0_ET_BIT) 62#define X86_CR0_NE_BIT 5 /* Numeric Error */ 63#define X86_CR0_NE _BITUL(X86_CR0_NE_BIT) 64#define X86_CR0_WP_BIT 16 /* Write Protect */ 65#define X86_CR0_WP _BITUL(X86_CR0_WP_BIT) 66#define X86_CR0_AM_BIT 18 /* Alignment Mask */ 67#define X86_CR0_AM _BITUL(X86_CR0_AM_BIT) 68#define X86_CR0_NW_BIT 29 /* Not Write-through */ 69#define X86_CR0_NW _BITUL(X86_CR0_NW_BIT) 70#define X86_CR0_CD_BIT 30 /* Cache Disable */ 71#define X86_CR0_CD _BITUL(X86_CR0_CD_BIT) 72#define X86_CR0_PG_BIT 31 /* Paging */ 73#define X86_CR0_PG _BITUL(X86_CR0_PG_BIT) 74 75/* 76 * Paging options in CR3 77 */ 78#define X86_CR3_PWT_BIT 3 /* Page Write Through */ 79#define X86_CR3_PWT _BITUL(X86_CR3_PWT_BIT) 80#define X86_CR3_PCD_BIT 4 /* Page Cache Disable */ 81#define X86_CR3_PCD _BITUL(X86_CR3_PCD_BIT) 82#define X86_CR3_PCID_MASK _AC(0x00000fff,UL) /* PCID Mask */ 83 84/* 85 * Intel CPU features in CR4 86 */ 87#define X86_CR4_VME_BIT 0 /* enable vm86 extensions */ 88#define X86_CR4_VME _BITUL(X86_CR4_VME_BIT) 89#define X86_CR4_PVI_BIT 1 /* virtual interrupts flag enable */ 90#define X86_CR4_PVI _BITUL(X86_CR4_PVI_BIT) 91#define X86_CR4_TSD_BIT 2 /* disable time stamp at ipl 3 */ 92#define X86_CR4_TSD _BITUL(X86_CR4_TSD_BIT) 93#define X86_CR4_DE_BIT 3 /* enable debugging extensions */ 94#define X86_CR4_DE _BITUL(X86_CR4_DE_BIT) 95#define X86_CR4_PSE_BIT 4 /* enable page size extensions */ 96#define X86_CR4_PSE _BITUL(X86_CR4_PSE_BIT) 97#define X86_CR4_PAE_BIT 5 /* enable physical address extensions */ 98#define X86_CR4_PAE _BITUL(X86_CR4_PAE_BIT) 99#define X86_CR4_MCE_BIT 6 /* Machine check enable */ 100#define X86_CR4_MCE _BITUL(X86_CR4_MCE_BIT) 101#define X86_CR4_PGE_BIT 7 /* enable global pages */ 102#define X86_CR4_PGE _BITUL(X86_CR4_PGE_BIT) 103#define X86_CR4_PCE_BIT 8 /* enable performance counters at ipl 3 */ 104#define X86_CR4_PCE _BITUL(X86_CR4_PCE_BIT) 105#define X86_CR4_OSFXSR_BIT 9 /* enable fast FPU save and restore */ 106#define X86_CR4_OSFXSR _BITUL(X86_CR4_OSFXSR_BIT) 107#define X86_CR4_OSXMMEXCPT_BIT 10 /* enable unmasked SSE exceptions */ 108#define X86_CR4_OSXMMEXCPT _BITUL(X86_CR4_OSXMMEXCPT_BIT) 109#define X86_CR4_VMXE_BIT 13 /* enable VMX virtualization */ 110#define X86_CR4_VMXE _BITUL(X86_CR4_VMXE_BIT) 111#define X86_CR4_SMXE_BIT 14 /* enable safer mode (TXT) */ 112#define X86_CR4_SMXE _BITUL(X86_CR4_SMXE_BIT) 113#define X86_CR4_FSGSBASE_BIT 16 /* enable RDWRFSGS support */ 114#define X86_CR4_FSGSBASE _BITUL(X86_CR4_FSGSBASE_BIT) 115#define X86_CR4_PCIDE_BIT 17 /* enable PCID support */ 116#define X86_CR4_PCIDE _BITUL(X86_CR4_PCIDE_BIT) 117#define X86_CR4_OSXSAVE_BIT 18 /* enable xsave and xrestore */ 118#define X86_CR4_OSXSAVE _BITUL(X86_CR4_OSXSAVE_BIT) 119#define X86_CR4_SMEP_BIT 20 /* enable SMEP support */ 120#define X86_CR4_SMEP _BITUL(X86_CR4_SMEP_BIT) 121#define X86_CR4_SMAP_BIT 21 /* enable SMAP support */ 122#define X86_CR4_SMAP _BITUL(X86_CR4_SMAP_BIT) 123 124/* 125 * x86-64 Task Priority Register, CR8 126 */ 127#define X86_CR8_TPR _AC(0x0000000f,UL) /* task priority register */ 128 129/* 130 * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h> 131 */ 132 133/* 134 * NSC/Cyrix CPU configuration register indexes 135 */ 136#define CX86_PCR0 0x20 137#define CX86_GCR 0xb8 138#define CX86_CCR0 0xc0 139#define CX86_CCR1 0xc1 140#define CX86_CCR2 0xc2 141#define CX86_CCR3 0xc3 142#define CX86_CCR4 0xe8 143#define CX86_CCR5 0xe9 144#define CX86_CCR6 0xea 145#define CX86_CCR7 0xeb 146#define CX86_PCR1 0xf0 147#define CX86_DIR0 0xfe 148#define CX86_DIR1 0xff 149#define CX86_ARR_BASE 0xc4 150#define CX86_RCR_BASE 0xdc 151 152 153#endif /* _UAPI_ASM_X86_PROCESSOR_FLAGS_H */ 154