1/* 2 * pata_cmd64x.c - CMD64x PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * Alan Cox <alan@lxorguk.ukuu.org.uk> 5 * (C) 2009-2010 Bartlomiej Zolnierkiewicz 6 * (C) 2012 MontaVista Software, LLC <source@mvista.com> 7 * 8 * Based upon 9 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002 10 * 11 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. 12 * Note, this driver is not used at all on other systems because 13 * there the "BIOS" has done all of the following already. 14 * Due to massive hardware bugs, UltraDMA is only supported 15 * on the 646U2 and not on the 646U. 16 * 17 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 18 * Copyright (C) 1998 David S. Miller (davem@redhat.com) 19 * 20 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 21 * 22 * TODO 23 * Testing work 24 */ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/pci.h> 29#include <linux/blkdev.h> 30#include <linux/delay.h> 31#include <scsi/scsi_host.h> 32#include <linux/libata.h> 33 34#define DRV_NAME "pata_cmd64x" 35#define DRV_VERSION "0.2.18" 36 37/* 38 * CMD64x specific registers definition. 39 */ 40 41enum { 42 CFR = 0x50, 43 CFR_INTR_CH0 = 0x04, 44 CNTRL = 0x51, 45 CNTRL_CH0 = 0x04, 46 CNTRL_CH1 = 0x08, 47 CMDTIM = 0x52, 48 ARTTIM0 = 0x53, 49 DRWTIM0 = 0x54, 50 ARTTIM1 = 0x55, 51 DRWTIM1 = 0x56, 52 ARTTIM23 = 0x57, 53 ARTTIM23_DIS_RA2 = 0x04, 54 ARTTIM23_DIS_RA3 = 0x08, 55 ARTTIM23_INTR_CH1 = 0x10, 56 DRWTIM2 = 0x58, 57 BRST = 0x59, 58 DRWTIM3 = 0x5b, 59 BMIDECR0 = 0x70, 60 MRDMODE = 0x71, 61 MRDMODE_INTR_CH0 = 0x04, 62 MRDMODE_INTR_CH1 = 0x08, 63 BMIDESR0 = 0x72, 64 UDIDETCR0 = 0x73, 65 DTPR0 = 0x74, 66 BMIDECR1 = 0x78, 67 BMIDECSR = 0x79, 68 UDIDETCR1 = 0x7B, 69 DTPR1 = 0x7C 70}; 71 72static int cmd648_cable_detect(struct ata_port *ap) 73{ 74 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 75 u8 r; 76 77 /* Check cable detect bits */ 78 pci_read_config_byte(pdev, BMIDECSR, &r); 79 if (r & (1 << ap->port_no)) 80 return ATA_CBL_PATA80; 81 return ATA_CBL_PATA40; 82} 83 84/** 85 * cmd64x_set_timing - set PIO and MWDMA timing 86 * @ap: ATA interface 87 * @adev: ATA device 88 * @mode: mode 89 * 90 * Called to do the PIO and MWDMA mode setup. 91 */ 92 93static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode) 94{ 95 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 96 struct ata_timing t; 97 const unsigned long T = 1000000 / 33; 98 const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; 99 100 u8 reg; 101 102 /* Port layout is not logical so use a table */ 103 const u8 arttim_port[2][2] = { 104 { ARTTIM0, ARTTIM1 }, 105 { ARTTIM23, ARTTIM23 } 106 }; 107 const u8 drwtim_port[2][2] = { 108 { DRWTIM0, DRWTIM1 }, 109 { DRWTIM2, DRWTIM3 } 110 }; 111 112 int arttim = arttim_port[ap->port_no][adev->devno]; 113 int drwtim = drwtim_port[ap->port_no][adev->devno]; 114 115 /* ata_timing_compute is smart and will produce timings for MWDMA 116 that don't violate the drives PIO capabilities. */ 117 if (ata_timing_compute(adev, mode, &t, T, 0) < 0) { 118 printk(KERN_ERR DRV_NAME ": mode computation failed.\n"); 119 return; 120 } 121 if (ap->port_no) { 122 /* Slave has shared address setup */ 123 struct ata_device *pair = ata_dev_pair(adev); 124 125 if (pair) { 126 struct ata_timing tp; 127 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0); 128 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 129 } 130 } 131 132 printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n", 133 t.active, t.recover, t.setup); 134 if (t.recover > 16) { 135 t.active += t.recover - 16; 136 t.recover = 16; 137 } 138 if (t.active > 16) 139 t.active = 16; 140 141 /* Now convert the clocks into values we can actually stuff into 142 the chip */ 143 144 if (t.recover == 16) 145 t.recover = 0; 146 else if (t.recover > 1) 147 t.recover--; 148 else 149 t.recover = 15; 150 151 if (t.setup > 4) 152 t.setup = 0xC0; 153 else 154 t.setup = setup_data[t.setup]; 155 156 t.active &= 0x0F; /* 0 = 16 */ 157 158 /* Load setup timing */ 159 pci_read_config_byte(pdev, arttim, ®); 160 reg &= 0x3F; 161 reg |= t.setup; 162 pci_write_config_byte(pdev, arttim, reg); 163 164 /* Load active/recovery */ 165 pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover); 166} 167 168/** 169 * cmd64x_set_piomode - set initial PIO mode data 170 * @ap: ATA interface 171 * @adev: ATA device 172 * 173 * Used when configuring the devices ot set the PIO timings. All the 174 * actual work is done by the PIO/MWDMA setting helper 175 */ 176 177static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) 178{ 179 cmd64x_set_timing(ap, adev, adev->pio_mode); 180} 181 182/** 183 * cmd64x_set_dmamode - set initial DMA mode data 184 * @ap: ATA interface 185 * @adev: ATA device 186 * 187 * Called to do the DMA mode setup. 188 */ 189 190static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev) 191{ 192 static const u8 udma_data[] = { 193 0x30, 0x20, 0x10, 0x20, 0x10, 0x00 194 }; 195 196 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 197 u8 regU, regD; 198 199 int pciU = UDIDETCR0 + 8 * ap->port_no; 200 int pciD = BMIDESR0 + 8 * ap->port_no; 201 int shift = 2 * adev->devno; 202 203 pci_read_config_byte(pdev, pciD, ®D); 204 pci_read_config_byte(pdev, pciU, ®U); 205 206 /* DMA bits off */ 207 regD &= ~(0x20 << adev->devno); 208 /* DMA control bits */ 209 regU &= ~(0x30 << shift); 210 /* DMA timing bits */ 211 regU &= ~(0x05 << adev->devno); 212 213 if (adev->dma_mode >= XFER_UDMA_0) { 214 /* Merge the timing value */ 215 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift; 216 /* Merge the control bits */ 217 regU |= 1 << adev->devno; /* UDMA on */ 218 if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */ 219 regU |= 4 << adev->devno; 220 } else { 221 regU &= ~ (1 << adev->devno); /* UDMA off */ 222 cmd64x_set_timing(ap, adev, adev->dma_mode); 223 } 224 225 regD |= 0x20 << adev->devno; 226 227 pci_write_config_byte(pdev, pciU, regU); 228 pci_write_config_byte(pdev, pciD, regD); 229} 230 231/** 232 * cmd64x_sff_irq_check - check IDE interrupt 233 * @ap: ATA interface 234 * 235 * Check IDE interrupt in CFR/ARTTIM23 registers. 236 */ 237 238static bool cmd64x_sff_irq_check(struct ata_port *ap) 239{ 240 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 241 int irq_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0; 242 int irq_reg = ap->port_no ? ARTTIM23 : CFR; 243 u8 irq_stat; 244 245 /* NOTE: reading the register should clear the interrupt */ 246 pci_read_config_byte(pdev, irq_reg, &irq_stat); 247 248 return irq_stat & irq_mask; 249} 250 251/** 252 * cmd64x_sff_irq_clear - clear IDE interrupt 253 * @ap: ATA interface 254 * 255 * Clear IDE interrupt in CFR/ARTTIM23 and DMA status registers. 256 */ 257 258static void cmd64x_sff_irq_clear(struct ata_port *ap) 259{ 260 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 261 int irq_reg = ap->port_no ? ARTTIM23 : CFR; 262 u8 irq_stat; 263 264 ata_bmdma_irq_clear(ap); 265 266 /* Reading the register should be enough to clear the interrupt */ 267 pci_read_config_byte(pdev, irq_reg, &irq_stat); 268} 269 270/** 271 * cmd648_sff_irq_check - check IDE interrupt 272 * @ap: ATA interface 273 * 274 * Check IDE interrupt in MRDMODE register. 275 */ 276 277static bool cmd648_sff_irq_check(struct ata_port *ap) 278{ 279 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 280 unsigned long base = pci_resource_start(pdev, 4); 281 int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0; 282 u8 mrdmode = inb(base + 1); 283 284 return mrdmode & irq_mask; 285} 286 287/** 288 * cmd648_sff_irq_clear - clear IDE interrupt 289 * @ap: ATA interface 290 * 291 * Clear IDE interrupt in MRDMODE and DMA status registers. 292 */ 293 294static void cmd648_sff_irq_clear(struct ata_port *ap) 295{ 296 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 297 unsigned long base = pci_resource_start(pdev, 4); 298 int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0; 299 u8 mrdmode; 300 301 ata_bmdma_irq_clear(ap); 302 303 /* Clear this port's interrupt bit (leaving the other port alone) */ 304 mrdmode = inb(base + 1); 305 mrdmode &= ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1); 306 outb(mrdmode | irq_mask, base + 1); 307} 308 309/** 310 * cmd646r1_bmdma_stop - DMA stop callback 311 * @qc: Command in progress 312 * 313 * Stub for now while investigating the r1 quirk in the old driver. 314 */ 315 316static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc) 317{ 318 ata_bmdma_stop(qc); 319} 320 321static struct scsi_host_template cmd64x_sht = { 322 ATA_BMDMA_SHT(DRV_NAME), 323}; 324 325static const struct ata_port_operations cmd64x_base_ops = { 326 .inherits = &ata_bmdma_port_ops, 327 .set_piomode = cmd64x_set_piomode, 328 .set_dmamode = cmd64x_set_dmamode, 329}; 330 331static struct ata_port_operations cmd64x_port_ops = { 332 .inherits = &cmd64x_base_ops, 333 .sff_irq_check = cmd64x_sff_irq_check, 334 .sff_irq_clear = cmd64x_sff_irq_clear, 335 .cable_detect = ata_cable_40wire, 336}; 337 338static struct ata_port_operations cmd646r1_port_ops = { 339 .inherits = &cmd64x_base_ops, 340 .sff_irq_check = cmd64x_sff_irq_check, 341 .sff_irq_clear = cmd64x_sff_irq_clear, 342 .bmdma_stop = cmd646r1_bmdma_stop, 343 .cable_detect = ata_cable_40wire, 344}; 345 346static struct ata_port_operations cmd646r3_port_ops = { 347 .inherits = &cmd64x_base_ops, 348 .sff_irq_check = cmd648_sff_irq_check, 349 .sff_irq_clear = cmd648_sff_irq_clear, 350 .cable_detect = ata_cable_40wire, 351}; 352 353static struct ata_port_operations cmd648_port_ops = { 354 .inherits = &cmd64x_base_ops, 355 .sff_irq_check = cmd648_sff_irq_check, 356 .sff_irq_clear = cmd648_sff_irq_clear, 357 .cable_detect = cmd648_cable_detect, 358}; 359 360static void cmd64x_fixup(struct pci_dev *pdev) 361{ 362 u8 mrdmode; 363 364 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); 365 pci_read_config_byte(pdev, MRDMODE, &mrdmode); 366 mrdmode &= ~0x30; /* IRQ set up */ 367 mrdmode |= 0x02; /* Memory read line enable */ 368 pci_write_config_byte(pdev, MRDMODE, mrdmode); 369 370 /* PPC specific fixup copied from old driver */ 371#ifdef CONFIG_PPC 372 pci_write_config_byte(pdev, UDIDETCR0, 0xF0); 373#endif 374} 375 376static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 377{ 378 static const struct ata_port_info cmd_info[7] = { 379 { /* CMD 643 - no UDMA */ 380 .flags = ATA_FLAG_SLAVE_POSS, 381 .pio_mask = ATA_PIO4, 382 .mwdma_mask = ATA_MWDMA2, 383 .port_ops = &cmd64x_port_ops 384 }, 385 { /* CMD 646 with broken UDMA */ 386 .flags = ATA_FLAG_SLAVE_POSS, 387 .pio_mask = ATA_PIO4, 388 .mwdma_mask = ATA_MWDMA2, 389 .port_ops = &cmd64x_port_ops 390 }, 391 { /* CMD 646U with broken UDMA */ 392 .flags = ATA_FLAG_SLAVE_POSS, 393 .pio_mask = ATA_PIO4, 394 .mwdma_mask = ATA_MWDMA2, 395 .port_ops = &cmd646r3_port_ops 396 }, 397 { /* CMD 646U2 with working UDMA */ 398 .flags = ATA_FLAG_SLAVE_POSS, 399 .pio_mask = ATA_PIO4, 400 .mwdma_mask = ATA_MWDMA2, 401 .udma_mask = ATA_UDMA2, 402 .port_ops = &cmd646r3_port_ops 403 }, 404 { /* CMD 646 rev 1 */ 405 .flags = ATA_FLAG_SLAVE_POSS, 406 .pio_mask = ATA_PIO4, 407 .mwdma_mask = ATA_MWDMA2, 408 .port_ops = &cmd646r1_port_ops 409 }, 410 { /* CMD 648 */ 411 .flags = ATA_FLAG_SLAVE_POSS, 412 .pio_mask = ATA_PIO4, 413 .mwdma_mask = ATA_MWDMA2, 414 .udma_mask = ATA_UDMA4, 415 .port_ops = &cmd648_port_ops 416 }, 417 { /* CMD 649 */ 418 .flags = ATA_FLAG_SLAVE_POSS, 419 .pio_mask = ATA_PIO4, 420 .mwdma_mask = ATA_MWDMA2, 421 .udma_mask = ATA_UDMA5, 422 .port_ops = &cmd648_port_ops 423 } 424 }; 425 const struct ata_port_info *ppi[] = { 426 &cmd_info[id->driver_data], 427 &cmd_info[id->driver_data], 428 NULL 429 }; 430 u8 reg; 431 int rc; 432 struct pci_dev *bridge = pdev->bus->self; 433 /* mobility split bridges don't report enabled ports correctly */ 434 int port_ok = !(bridge && bridge->vendor == 435 PCI_VENDOR_ID_MOBILITY_ELECTRONICS); 436 /* all (with exceptions below) apart from 643 have CNTRL_CH0 bit */ 437 int cntrl_ch0_ok = (id->driver_data != 0); 438 439 rc = pcim_enable_device(pdev); 440 if (rc) 441 return rc; 442 443 if (id->driver_data == 0) /* 643 */ 444 ata_pci_bmdma_clear_simplex(pdev); 445 446 if (pdev->device == PCI_DEVICE_ID_CMD_646) 447 switch (pdev->revision) { 448 /* UDMA works since rev 5 */ 449 default: 450 ppi[0] = &cmd_info[3]; 451 ppi[1] = &cmd_info[3]; 452 break; 453 /* Interrupts in MRDMODE since rev 3 */ 454 case 3: 455 case 4: 456 ppi[0] = &cmd_info[2]; 457 ppi[1] = &cmd_info[2]; 458 break; 459 /* Rev 1 with other problems? */ 460 case 1: 461 ppi[0] = &cmd_info[4]; 462 ppi[1] = &cmd_info[4]; 463 /* FALL THRU */ 464 /* Early revs have no CNTRL_CH0 */ 465 case 2: 466 case 0: 467 cntrl_ch0_ok = 0; 468 break; 469 } 470 471 cmd64x_fixup(pdev); 472 473 /* check for enabled ports */ 474 pci_read_config_byte(pdev, CNTRL, ®); 475 if (!port_ok) 476 dev_notice(&pdev->dev, "Mobility Bridge detected, ignoring CNTRL port enable/disable\n"); 477 if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) { 478 dev_notice(&pdev->dev, "Primary port is disabled\n"); 479 ppi[0] = &ata_dummy_port_info; 480 481 } 482 if (port_ok && !(reg & CNTRL_CH1)) { 483 dev_notice(&pdev->dev, "Secondary port is disabled\n"); 484 ppi[1] = &ata_dummy_port_info; 485 } 486 487 return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0); 488} 489 490#ifdef CONFIG_PM_SLEEP 491static int cmd64x_reinit_one(struct pci_dev *pdev) 492{ 493 struct ata_host *host = pci_get_drvdata(pdev); 494 int rc; 495 496 rc = ata_pci_device_do_resume(pdev); 497 if (rc) 498 return rc; 499 500 cmd64x_fixup(pdev); 501 502 ata_host_resume(host); 503 return 0; 504} 505#endif 506 507static const struct pci_device_id cmd64x[] = { 508 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 }, 509 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 }, 510 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 5 }, 511 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 6 }, 512 513 { }, 514}; 515 516static struct pci_driver cmd64x_pci_driver = { 517 .name = DRV_NAME, 518 .id_table = cmd64x, 519 .probe = cmd64x_init_one, 520 .remove = ata_pci_remove_one, 521#ifdef CONFIG_PM_SLEEP 522 .suspend = ata_pci_device_suspend, 523 .resume = cmd64x_reinit_one, 524#endif 525}; 526 527module_pci_driver(cmd64x_pci_driver); 528 529MODULE_AUTHOR("Alan Cox"); 530MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers"); 531MODULE_LICENSE("GPL"); 532MODULE_DEVICE_TABLE(pci, cmd64x); 533MODULE_VERSION(DRV_VERSION); 534