1/* 2 * pxa168 clock framework source file 3 * 4 * Copyright (C) 2012 Marvell 5 * Chao Xie <xiechao.mail@gmail.com> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12#include <linux/module.h> 13#include <linux/kernel.h> 14#include <linux/spinlock.h> 15#include <linux/io.h> 16#include <linux/delay.h> 17#include <linux/err.h> 18#include <linux/of_address.h> 19 20#include <dt-bindings/clock/marvell,pxa168.h> 21 22#include "clk.h" 23#include "reset.h" 24 25#define APBC_RTC 0x28 26#define APBC_TWSI0 0x2c 27#define APBC_KPC 0x30 28#define APBC_UART0 0x0 29#define APBC_UART1 0x4 30#define APBC_GPIO 0x8 31#define APBC_PWM0 0xc 32#define APBC_PWM1 0x10 33#define APBC_PWM2 0x14 34#define APBC_PWM3 0x18 35#define APBC_SSP0 0x81c 36#define APBC_SSP1 0x820 37#define APBC_SSP2 0x84c 38#define APBC_SSP3 0x858 39#define APBC_SSP4 0x85c 40#define APBC_TWSI1 0x6c 41#define APBC_UART2 0x70 42#define APMU_SDH0 0x54 43#define APMU_SDH1 0x58 44#define APMU_USB 0x5c 45#define APMU_DISP0 0x4c 46#define APMU_CCIC0 0x50 47#define APMU_DFC 0x60 48#define MPMU_UART_PLL 0x14 49 50struct pxa168_clk_unit { 51 struct mmp_clk_unit unit; 52 void __iomem *mpmu_base; 53 void __iomem *apmu_base; 54 void __iomem *apbc_base; 55}; 56 57static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = { 58 {PXA168_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768}, 59 {PXA168_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000}, 60 {PXA168_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000}, 61}; 62 63static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = { 64 {PXA168_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0}, 65 {PXA168_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0}, 66 {PXA168_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0}, 67 {PXA168_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0}, 68 {PXA168_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0}, 69 {PXA168_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0}, 70 {PXA168_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0}, 71 {PXA168_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0}, 72 {PXA168_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0}, 73 {PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0}, 74 {PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0}, 75 {PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0}, 76 {PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0}, 77}; 78 79static struct mmp_clk_factor_masks uart_factor_masks = { 80 .factor = 2, 81 .num_mask = 0x1fff, 82 .den_mask = 0x1fff, 83 .num_shift = 16, 84 .den_shift = 0, 85}; 86 87static struct mmp_clk_factor_tbl uart_factor_tbl[] = { 88 {.num = 8125, .den = 1536}, /*14.745MHZ */ 89}; 90 91static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit) 92{ 93 struct clk *clk; 94 struct mmp_clk_unit *unit = &pxa_unit->unit; 95 96 mmp_register_fixed_rate_clks(unit, fixed_rate_clks, 97 ARRAY_SIZE(fixed_rate_clks)); 98 99 mmp_register_fixed_factor_clks(unit, fixed_factor_clks, 100 ARRAY_SIZE(fixed_factor_clks)); 101 102 clk = mmp_clk_register_factor("uart_pll", "pll1_4", 103 CLK_SET_RATE_PARENT, 104 pxa_unit->mpmu_base + MPMU_UART_PLL, 105 &uart_factor_masks, uart_factor_tbl, 106 ARRAY_SIZE(uart_factor_tbl), NULL); 107 mmp_clk_add(unit, PXA168_CLK_UART_PLL, clk); 108} 109 110static DEFINE_SPINLOCK(uart0_lock); 111static DEFINE_SPINLOCK(uart1_lock); 112static DEFINE_SPINLOCK(uart2_lock); 113static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"}; 114 115static DEFINE_SPINLOCK(ssp0_lock); 116static DEFINE_SPINLOCK(ssp1_lock); 117static DEFINE_SPINLOCK(ssp2_lock); 118static DEFINE_SPINLOCK(ssp3_lock); 119static DEFINE_SPINLOCK(ssp4_lock); 120static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"}; 121 122static DEFINE_SPINLOCK(reset_lock); 123 124static struct mmp_param_mux_clk apbc_mux_clks[] = { 125 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock}, 126 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock}, 127 {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock}, 128 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock}, 129 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock}, 130 {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock}, 131 {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock}, 132 {0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4, 3, 0, &ssp4_lock}, 133}; 134 135static struct mmp_param_gate_clk apbc_gate_clks[] = { 136 {PXA168_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock}, 137 {PXA168_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock}, 138 {PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock}, 139 {PXA168_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL}, 140 {PXA168_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL}, 141 {PXA168_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock}, 142 {PXA168_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock}, 143 {PXA168_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock}, 144 {PXA168_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock}, 145 /* The gate clocks has mux parent. */ 146 {PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock}, 147 {PXA168_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock}, 148 {PXA168_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock}, 149 {PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock}, 150 {PXA168_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock}, 151 {PXA168_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x3, 0x3, 0x0, 0, &ssp2_lock}, 152 {PXA168_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x3, 0x3, 0x0, 0, &ssp3_lock}, 153 {PXA168_CLK_SSP4, "ssp4_clk", "ssp4_mux", CLK_SET_RATE_PARENT, APBC_SSP4, 0x3, 0x3, 0x0, 0, &ssp4_lock}, 154}; 155 156static void pxa168_apb_periph_clk_init(struct pxa168_clk_unit *pxa_unit) 157{ 158 struct mmp_clk_unit *unit = &pxa_unit->unit; 159 160 mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base, 161 ARRAY_SIZE(apbc_mux_clks)); 162 163 mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base, 164 ARRAY_SIZE(apbc_gate_clks)); 165 166} 167 168static DEFINE_SPINLOCK(sdh0_lock); 169static DEFINE_SPINLOCK(sdh1_lock); 170static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"}; 171 172static DEFINE_SPINLOCK(usb_lock); 173 174static DEFINE_SPINLOCK(disp0_lock); 175static const char *disp_parent_names[] = {"pll1_2", "pll1_12"}; 176 177static DEFINE_SPINLOCK(ccic0_lock); 178static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"}; 179static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"}; 180 181static struct mmp_param_mux_clk apmu_mux_clks[] = { 182 {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock}, 183 {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock}, 184 {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock}, 185 {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock}, 186 {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock}, 187}; 188 189static struct mmp_param_div_clk apmu_div_clks[] = { 190 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock}, 191}; 192 193static struct mmp_param_gate_clk apmu_gate_clks[] = { 194 {PXA168_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL}, 195 {PXA168_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock}, 196 {PXA168_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock}, 197 /* The gate clocks has mux parent. */ 198 {PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock}, 199 {PXA168_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock}, 200 {PXA168_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock}, 201 {PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock}, 202 {PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock}, 203 {PXA168_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock}, 204}; 205 206static void pxa168_axi_periph_clk_init(struct pxa168_clk_unit *pxa_unit) 207{ 208 struct mmp_clk_unit *unit = &pxa_unit->unit; 209 210 mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base, 211 ARRAY_SIZE(apmu_mux_clks)); 212 213 mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base, 214 ARRAY_SIZE(apmu_div_clks)); 215 216 mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base, 217 ARRAY_SIZE(apmu_gate_clks)); 218} 219 220static void pxa168_clk_reset_init(struct device_node *np, 221 struct pxa168_clk_unit *pxa_unit) 222{ 223 struct mmp_clk_reset_cell *cells; 224 int i, nr_resets; 225 226 nr_resets = ARRAY_SIZE(apbc_gate_clks); 227 cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL); 228 if (!cells) 229 return; 230 231 for (i = 0; i < nr_resets; i++) { 232 cells[i].clk_id = apbc_gate_clks[i].id; 233 cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset; 234 cells[i].flags = 0; 235 cells[i].lock = apbc_gate_clks[i].lock; 236 cells[i].bits = 0x4; 237 } 238 239 mmp_clk_reset_register(np, cells, nr_resets); 240} 241 242static void __init pxa168_clk_init(struct device_node *np) 243{ 244 struct pxa168_clk_unit *pxa_unit; 245 246 pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL); 247 if (!pxa_unit) 248 return; 249 250 pxa_unit->mpmu_base = of_iomap(np, 0); 251 if (!pxa_unit->mpmu_base) { 252 pr_err("failed to map mpmu registers\n"); 253 return; 254 } 255 256 pxa_unit->apmu_base = of_iomap(np, 1); 257 if (!pxa_unit->mpmu_base) { 258 pr_err("failed to map apmu registers\n"); 259 return; 260 } 261 262 pxa_unit->apbc_base = of_iomap(np, 2); 263 if (!pxa_unit->apbc_base) { 264 pr_err("failed to map apbc registers\n"); 265 return; 266 } 267 268 mmp_clk_init(np, &pxa_unit->unit, PXA168_NR_CLKS); 269 270 pxa168_pll_init(pxa_unit); 271 272 pxa168_apb_periph_clk_init(pxa_unit); 273 274 pxa168_axi_periph_clk_init(pxa_unit); 275 276 pxa168_clk_reset_init(np, pxa_unit); 277} 278 279CLK_OF_DECLARE(pxa168_clk, "marvell,pxa168-clock", pxa168_clk_init); 280