1/*
2 * Copyright (C) 2014 Google, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/kernel.h>
11#include <linux/of.h>
12#include <linux/of_address.h>
13#include <linux/slab.h>
14
15#include "clk.h"
16
17struct pistachio_clk_provider *
18pistachio_clk_alloc_provider(struct device_node *node, unsigned int num_clks)
19{
20	struct pistachio_clk_provider *p;
21
22	p = kzalloc(sizeof(*p), GFP_KERNEL);
23	if (!p)
24		return p;
25
26	p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL);
27	if (!p->clk_data.clks)
28		goto free_provider;
29	p->clk_data.clk_num = num_clks;
30	p->node = node;
31	p->base = of_iomap(node, 0);
32	if (!p->base) {
33		pr_err("Failed to map clock provider registers\n");
34		goto free_clks;
35	}
36
37	return p;
38
39free_clks:
40	kfree(p->clk_data.clks);
41free_provider:
42	kfree(p);
43	return NULL;
44}
45
46void pistachio_clk_register_provider(struct pistachio_clk_provider *p)
47{
48	unsigned int i;
49
50	for (i = 0; i < p->clk_data.clk_num; i++) {
51		if (IS_ERR(p->clk_data.clks[i]))
52			pr_warn("Failed to register clock %d: %ld\n", i,
53				PTR_ERR(p->clk_data.clks[i]));
54	}
55
56	of_clk_add_provider(p->node, of_clk_src_onecell_get, &p->clk_data);
57}
58
59void pistachio_clk_register_gate(struct pistachio_clk_provider *p,
60				 struct pistachio_gate *gate,
61				 unsigned int num)
62{
63	struct clk *clk;
64	unsigned int i;
65
66	for (i = 0; i < num; i++) {
67		clk = clk_register_gate(NULL, gate[i].name, gate[i].parent,
68					CLK_SET_RATE_PARENT,
69					p->base + gate[i].reg, gate[i].shift,
70					0, NULL);
71		p->clk_data.clks[gate[i].id] = clk;
72	}
73}
74
75void pistachio_clk_register_mux(struct pistachio_clk_provider *p,
76				struct pistachio_mux *mux,
77				unsigned int num)
78{
79	struct clk *clk;
80	unsigned int i;
81
82	for (i = 0; i < num; i++) {
83		clk = clk_register_mux(NULL, mux[i].name, mux[i].parents,
84				       mux[i].num_parents,
85				       CLK_SET_RATE_NO_REPARENT,
86				       p->base + mux[i].reg, mux[i].shift,
87				       get_count_order(mux[i].num_parents),
88				       0, NULL);
89		p->clk_data.clks[mux[i].id] = clk;
90	}
91}
92
93void pistachio_clk_register_div(struct pistachio_clk_provider *p,
94				struct pistachio_div *div,
95				unsigned int num)
96{
97	struct clk *clk;
98	unsigned int i;
99
100	for (i = 0; i < num; i++) {
101		clk = clk_register_divider(NULL, div[i].name, div[i].parent,
102					   0, p->base + div[i].reg, 0,
103					   div[i].width, div[i].div_flags,
104					   NULL);
105		p->clk_data.clks[div[i].id] = clk;
106	}
107}
108
109void pistachio_clk_register_fixed_factor(struct pistachio_clk_provider *p,
110					 struct pistachio_fixed_factor *ff,
111					 unsigned int num)
112{
113	struct clk *clk;
114	unsigned int i;
115
116	for (i = 0; i < num; i++) {
117		clk = clk_register_fixed_factor(NULL, ff[i].name, ff[i].parent,
118						0, 1, ff[i].div);
119		p->clk_data.clks[ff[i].id] = clk;
120	}
121}
122
123void pistachio_clk_force_enable(struct pistachio_clk_provider *p,
124				unsigned int *clk_ids, unsigned int num)
125{
126	unsigned int i;
127	int err;
128
129	for (i = 0; i < num; i++) {
130		struct clk *clk = p->clk_data.clks[clk_ids[i]];
131
132		if (IS_ERR(clk))
133			continue;
134
135		err = clk_prepare_enable(clk);
136		if (err)
137			pr_err("Failed to enable clock %s: %d\n",
138			       __clk_get_name(clk), err);
139	}
140}
141