1/*
2 * TI Divider Clock
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Tero Kristo <t-kristo@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/clk-provider.h>
19#include <linux/slab.h>
20#include <linux/err.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/clk/ti.h>
24#include "clock.h"
25
26#undef pr_fmt
27#define pr_fmt(fmt) "%s: " fmt, __func__
28
29#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
30
31#define div_mask(d)	((1 << ((d)->width)) - 1)
32
33static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
34{
35	unsigned int maxdiv = 0;
36	const struct clk_div_table *clkt;
37
38	for (clkt = table; clkt->div; clkt++)
39		if (clkt->div > maxdiv)
40			maxdiv = clkt->div;
41	return maxdiv;
42}
43
44static unsigned int _get_maxdiv(struct clk_divider *divider)
45{
46	if (divider->flags & CLK_DIVIDER_ONE_BASED)
47		return div_mask(divider);
48	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
49		return 1 << div_mask(divider);
50	if (divider->table)
51		return _get_table_maxdiv(divider->table);
52	return div_mask(divider) + 1;
53}
54
55static unsigned int _get_table_div(const struct clk_div_table *table,
56				   unsigned int val)
57{
58	const struct clk_div_table *clkt;
59
60	for (clkt = table; clkt->div; clkt++)
61		if (clkt->val == val)
62			return clkt->div;
63	return 0;
64}
65
66static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
67{
68	if (divider->flags & CLK_DIVIDER_ONE_BASED)
69		return val;
70	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
71		return 1 << val;
72	if (divider->table)
73		return _get_table_div(divider->table, val);
74	return val + 1;
75}
76
77static unsigned int _get_table_val(const struct clk_div_table *table,
78				   unsigned int div)
79{
80	const struct clk_div_table *clkt;
81
82	for (clkt = table; clkt->div; clkt++)
83		if (clkt->div == div)
84			return clkt->val;
85	return 0;
86}
87
88static unsigned int _get_val(struct clk_divider *divider, u8 div)
89{
90	if (divider->flags & CLK_DIVIDER_ONE_BASED)
91		return div;
92	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
93		return __ffs(div);
94	if (divider->table)
95		return  _get_table_val(divider->table, div);
96	return div - 1;
97}
98
99static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
100						unsigned long parent_rate)
101{
102	struct clk_divider *divider = to_clk_divider(hw);
103	unsigned int div, val;
104
105	val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift;
106	val &= div_mask(divider);
107
108	div = _get_div(divider, val);
109	if (!div) {
110		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
111		     "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
112		     __clk_get_name(hw->clk));
113		return parent_rate;
114	}
115
116	return DIV_ROUND_UP(parent_rate, div);
117}
118
119/*
120 * The reverse of DIV_ROUND_UP: The maximum number which
121 * divided by m is r
122 */
123#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
124
125static bool _is_valid_table_div(const struct clk_div_table *table,
126				unsigned int div)
127{
128	const struct clk_div_table *clkt;
129
130	for (clkt = table; clkt->div; clkt++)
131		if (clkt->div == div)
132			return true;
133	return false;
134}
135
136static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
137{
138	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
139		return is_power_of_2(div);
140	if (divider->table)
141		return _is_valid_table_div(divider->table, div);
142	return true;
143}
144
145static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
146				  unsigned long *best_parent_rate)
147{
148	struct clk_divider *divider = to_clk_divider(hw);
149	int i, bestdiv = 0;
150	unsigned long parent_rate, best = 0, now, maxdiv;
151	unsigned long parent_rate_saved = *best_parent_rate;
152
153	if (!rate)
154		rate = 1;
155
156	maxdiv = _get_maxdiv(divider);
157
158	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
159		parent_rate = *best_parent_rate;
160		bestdiv = DIV_ROUND_UP(parent_rate, rate);
161		bestdiv = bestdiv == 0 ? 1 : bestdiv;
162		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
163		return bestdiv;
164	}
165
166	/*
167	 * The maximum divider we can use without overflowing
168	 * unsigned long in rate * i below
169	 */
170	maxdiv = min(ULONG_MAX / rate, maxdiv);
171
172	for (i = 1; i <= maxdiv; i++) {
173		if (!_is_valid_div(divider, i))
174			continue;
175		if (rate * i == parent_rate_saved) {
176			/*
177			 * It's the most ideal case if the requested rate can be
178			 * divided from parent clock without needing to change
179			 * parent rate, so return the divider immediately.
180			 */
181			*best_parent_rate = parent_rate_saved;
182			return i;
183		}
184		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
185				MULT_ROUND_UP(rate, i));
186		now = DIV_ROUND_UP(parent_rate, i);
187		if (now <= rate && now > best) {
188			bestdiv = i;
189			best = now;
190			*best_parent_rate = parent_rate;
191		}
192	}
193
194	if (!bestdiv) {
195		bestdiv = _get_maxdiv(divider);
196		*best_parent_rate =
197			__clk_round_rate(__clk_get_parent(hw->clk), 1);
198	}
199
200	return bestdiv;
201}
202
203static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
204				      unsigned long *prate)
205{
206	int div;
207	div = ti_clk_divider_bestdiv(hw, rate, prate);
208
209	return DIV_ROUND_UP(*prate, div);
210}
211
212static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
213				   unsigned long parent_rate)
214{
215	struct clk_divider *divider;
216	unsigned int div, value;
217	unsigned long flags = 0;
218	u32 val;
219
220	if (!hw || !rate)
221		return -EINVAL;
222
223	divider = to_clk_divider(hw);
224
225	div = DIV_ROUND_UP(parent_rate, rate);
226	value = _get_val(divider, div);
227
228	if (value > div_mask(divider))
229		value = div_mask(divider);
230
231	if (divider->lock)
232		spin_lock_irqsave(divider->lock, flags);
233
234	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
235		val = div_mask(divider) << (divider->shift + 16);
236	} else {
237		val = ti_clk_ll_ops->clk_readl(divider->reg);
238		val &= ~(div_mask(divider) << divider->shift);
239	}
240	val |= value << divider->shift;
241	ti_clk_ll_ops->clk_writel(val, divider->reg);
242
243	if (divider->lock)
244		spin_unlock_irqrestore(divider->lock, flags);
245
246	return 0;
247}
248
249const struct clk_ops ti_clk_divider_ops = {
250	.recalc_rate = ti_clk_divider_recalc_rate,
251	.round_rate = ti_clk_divider_round_rate,
252	.set_rate = ti_clk_divider_set_rate,
253};
254
255static struct clk *_register_divider(struct device *dev, const char *name,
256				     const char *parent_name,
257				     unsigned long flags, void __iomem *reg,
258				     u8 shift, u8 width, u8 clk_divider_flags,
259				     const struct clk_div_table *table,
260				     spinlock_t *lock)
261{
262	struct clk_divider *div;
263	struct clk *clk;
264	struct clk_init_data init;
265
266	if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
267		if (width + shift > 16) {
268			pr_warn("divider value exceeds LOWORD field\n");
269			return ERR_PTR(-EINVAL);
270		}
271	}
272
273	/* allocate the divider */
274	div = kzalloc(sizeof(*div), GFP_KERNEL);
275	if (!div) {
276		pr_err("%s: could not allocate divider clk\n", __func__);
277		return ERR_PTR(-ENOMEM);
278	}
279
280	init.name = name;
281	init.ops = &ti_clk_divider_ops;
282	init.flags = flags | CLK_IS_BASIC;
283	init.parent_names = (parent_name ? &parent_name : NULL);
284	init.num_parents = (parent_name ? 1 : 0);
285
286	/* struct clk_divider assignments */
287	div->reg = reg;
288	div->shift = shift;
289	div->width = width;
290	div->flags = clk_divider_flags;
291	div->lock = lock;
292	div->hw.init = &init;
293	div->table = table;
294
295	/* register the clock */
296	clk = clk_register(dev, &div->hw);
297
298	if (IS_ERR(clk))
299		kfree(div);
300
301	return clk;
302}
303
304static struct clk_div_table *
305_get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
306{
307	int valid_div = 0;
308	struct clk_div_table *table;
309	int i;
310	int div;
311	u32 val;
312	u8 flags;
313
314	if (!setup->num_dividers) {
315		/* Clk divider table not provided, determine min/max divs */
316		flags = setup->flags;
317
318		if (flags & CLKF_INDEX_STARTS_AT_ONE)
319			val = 1;
320		else
321			val = 0;
322
323		div = 1;
324
325		while (div < setup->max_div) {
326			if (flags & CLKF_INDEX_POWER_OF_TWO)
327				div <<= 1;
328			else
329				div++;
330			val++;
331		}
332
333		*width = fls(val);
334
335		return NULL;
336	}
337
338	for (i = 0; i < setup->num_dividers; i++)
339		if (setup->dividers[i])
340			valid_div++;
341
342	table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
343	if (!table)
344		return ERR_PTR(-ENOMEM);
345
346	valid_div = 0;
347	*width = 0;
348
349	for (i = 0; i < setup->num_dividers; i++)
350		if (setup->dividers[i]) {
351			table[valid_div].div = setup->dividers[i];
352			table[valid_div].val = i;
353			valid_div++;
354			*width = i;
355		}
356
357	*width = fls(*width);
358
359	return table;
360}
361
362struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
363{
364	struct clk_divider *div;
365	struct clk_omap_reg *reg;
366
367	if (!setup)
368		return NULL;
369
370	div = kzalloc(sizeof(*div), GFP_KERNEL);
371	if (!div)
372		return ERR_PTR(-ENOMEM);
373
374	reg = (struct clk_omap_reg *)&div->reg;
375	reg->index = setup->module;
376	reg->offset = setup->reg;
377
378	if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
379		div->flags |= CLK_DIVIDER_ONE_BASED;
380
381	if (setup->flags & CLKF_INDEX_POWER_OF_TWO)
382		div->flags |= CLK_DIVIDER_POWER_OF_TWO;
383
384	div->table = _get_div_table_from_setup(setup, &div->width);
385
386	div->shift = setup->bit_shift;
387
388	return &div->hw;
389}
390
391struct clk *ti_clk_register_divider(struct ti_clk *setup)
392{
393	struct ti_clk_divider *div;
394	struct clk_omap_reg *reg_setup;
395	u32 reg;
396	u8 width;
397	u32 flags = 0;
398	u8 div_flags = 0;
399	struct clk_div_table *table;
400	struct clk *clk;
401
402	div = setup->data;
403
404	reg_setup = (struct clk_omap_reg *)&reg;
405
406	reg_setup->index = div->module;
407	reg_setup->offset = div->reg;
408
409	if (div->flags & CLKF_INDEX_STARTS_AT_ONE)
410		div_flags |= CLK_DIVIDER_ONE_BASED;
411
412	if (div->flags & CLKF_INDEX_POWER_OF_TWO)
413		div_flags |= CLK_DIVIDER_POWER_OF_TWO;
414
415	if (div->flags & CLKF_SET_RATE_PARENT)
416		flags |= CLK_SET_RATE_PARENT;
417
418	table = _get_div_table_from_setup(div, &width);
419	if (IS_ERR(table))
420		return (struct clk *)table;
421
422	clk = _register_divider(NULL, setup->name, div->parent,
423				flags, (void __iomem *)reg, div->bit_shift,
424				width, div_flags, table, NULL);
425
426	if (IS_ERR(clk))
427		kfree(table);
428
429	return clk;
430}
431
432static struct clk_div_table *
433__init ti_clk_get_div_table(struct device_node *node)
434{
435	struct clk_div_table *table;
436	const __be32 *divspec;
437	u32 val;
438	u32 num_div;
439	u32 valid_div;
440	int i;
441
442	divspec = of_get_property(node, "ti,dividers", &num_div);
443
444	if (!divspec)
445		return NULL;
446
447	num_div /= 4;
448
449	valid_div = 0;
450
451	/* Determine required size for divider table */
452	for (i = 0; i < num_div; i++) {
453		of_property_read_u32_index(node, "ti,dividers", i, &val);
454		if (val)
455			valid_div++;
456	}
457
458	if (!valid_div) {
459		pr_err("no valid dividers for %s table\n", node->name);
460		return ERR_PTR(-EINVAL);
461	}
462
463	table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
464
465	if (!table)
466		return ERR_PTR(-ENOMEM);
467
468	valid_div = 0;
469
470	for (i = 0; i < num_div; i++) {
471		of_property_read_u32_index(node, "ti,dividers", i, &val);
472		if (val) {
473			table[valid_div].div = val;
474			table[valid_div].val = i;
475			valid_div++;
476		}
477	}
478
479	return table;
480}
481
482static int _get_divider_width(struct device_node *node,
483			      const struct clk_div_table *table,
484			      u8 flags)
485{
486	u32 min_div;
487	u32 max_div;
488	u32 val = 0;
489	u32 div;
490
491	if (!table) {
492		/* Clk divider table not provided, determine min/max divs */
493		if (of_property_read_u32(node, "ti,min-div", &min_div))
494			min_div = 1;
495
496		if (of_property_read_u32(node, "ti,max-div", &max_div)) {
497			pr_err("no max-div for %s!\n", node->name);
498			return -EINVAL;
499		}
500
501		/* Determine bit width for the field */
502		if (flags & CLK_DIVIDER_ONE_BASED)
503			val = 1;
504
505		div = min_div;
506
507		while (div < max_div) {
508			if (flags & CLK_DIVIDER_POWER_OF_TWO)
509				div <<= 1;
510			else
511				div++;
512			val++;
513		}
514	} else {
515		div = 0;
516
517		while (table[div].div) {
518			val = table[div].val;
519			div++;
520		}
521	}
522
523	return fls(val);
524}
525
526static int __init ti_clk_divider_populate(struct device_node *node,
527	void __iomem **reg, const struct clk_div_table **table,
528	u32 *flags, u8 *div_flags, u8 *width, u8 *shift)
529{
530	u32 val;
531
532	*reg = ti_clk_get_reg_addr(node, 0);
533	if (IS_ERR(*reg))
534		return PTR_ERR(*reg);
535
536	if (!of_property_read_u32(node, "ti,bit-shift", &val))
537		*shift = val;
538	else
539		*shift = 0;
540
541	*flags = 0;
542	*div_flags = 0;
543
544	if (of_property_read_bool(node, "ti,index-starts-at-one"))
545		*div_flags |= CLK_DIVIDER_ONE_BASED;
546
547	if (of_property_read_bool(node, "ti,index-power-of-two"))
548		*div_flags |= CLK_DIVIDER_POWER_OF_TWO;
549
550	if (of_property_read_bool(node, "ti,set-rate-parent"))
551		*flags |= CLK_SET_RATE_PARENT;
552
553	*table = ti_clk_get_div_table(node);
554
555	if (IS_ERR(*table))
556		return PTR_ERR(*table);
557
558	*width = _get_divider_width(node, *table, *div_flags);
559
560	return 0;
561}
562
563/**
564 * of_ti_divider_clk_setup - Setup function for simple div rate clock
565 * @node: device node for this clock
566 *
567 * Sets up a basic divider clock.
568 */
569static void __init of_ti_divider_clk_setup(struct device_node *node)
570{
571	struct clk *clk;
572	const char *parent_name;
573	void __iomem *reg;
574	u8 clk_divider_flags = 0;
575	u8 width = 0;
576	u8 shift = 0;
577	const struct clk_div_table *table = NULL;
578	u32 flags = 0;
579
580	parent_name = of_clk_get_parent_name(node, 0);
581
582	if (ti_clk_divider_populate(node, &reg, &table, &flags,
583				    &clk_divider_flags, &width, &shift))
584		goto cleanup;
585
586	clk = _register_divider(NULL, node->name, parent_name, flags, reg,
587				shift, width, clk_divider_flags, table,
588				NULL);
589
590	if (!IS_ERR(clk)) {
591		of_clk_add_provider(node, of_clk_src_simple_get, clk);
592		of_ti_clk_autoidle_setup(node);
593		return;
594	}
595
596cleanup:
597	kfree(table);
598}
599CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
600
601static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
602{
603	struct clk_divider *div;
604	u32 val;
605
606	div = kzalloc(sizeof(*div), GFP_KERNEL);
607	if (!div)
608		return;
609
610	if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
611				    &div->flags, &div->width, &div->shift) < 0)
612		goto cleanup;
613
614	if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
615		return;
616
617cleanup:
618	kfree(div->table);
619	kfree(div);
620}
621CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
622	       of_ti_composite_divider_clk_setup);
623