1/* 2 * DMA controller driver for CSR SiRFprimaII 3 * 4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 5 * 6 * Licensed under GPLv2 or later. 7 */ 8 9#include <linux/module.h> 10#include <linux/dmaengine.h> 11#include <linux/dma-mapping.h> 12#include <linux/pm_runtime.h> 13#include <linux/interrupt.h> 14#include <linux/io.h> 15#include <linux/slab.h> 16#include <linux/of_irq.h> 17#include <linux/of_address.h> 18#include <linux/of_device.h> 19#include <linux/of_platform.h> 20#include <linux/clk.h> 21#include <linux/of_dma.h> 22#include <linux/sirfsoc_dma.h> 23 24#include "dmaengine.h" 25 26#define SIRFSOC_DMA_DESCRIPTORS 16 27#define SIRFSOC_DMA_CHANNELS 16 28 29#define SIRFSOC_DMA_CH_ADDR 0x00 30#define SIRFSOC_DMA_CH_XLEN 0x04 31#define SIRFSOC_DMA_CH_YLEN 0x08 32#define SIRFSOC_DMA_CH_CTRL 0x0C 33 34#define SIRFSOC_DMA_WIDTH_0 0x100 35#define SIRFSOC_DMA_CH_VALID 0x140 36#define SIRFSOC_DMA_CH_INT 0x144 37#define SIRFSOC_DMA_INT_EN 0x148 38#define SIRFSOC_DMA_INT_EN_CLR 0x14C 39#define SIRFSOC_DMA_CH_LOOP_CTRL 0x150 40#define SIRFSOC_DMA_CH_LOOP_CTRL_CLR 0x15C 41 42#define SIRFSOC_DMA_MODE_CTRL_BIT 4 43#define SIRFSOC_DMA_DIR_CTRL_BIT 5 44 45/* xlen and dma_width register is in 4 bytes boundary */ 46#define SIRFSOC_DMA_WORD_LEN 4 47 48struct sirfsoc_dma_desc { 49 struct dma_async_tx_descriptor desc; 50 struct list_head node; 51 52 /* SiRFprimaII 2D-DMA parameters */ 53 54 int xlen; /* DMA xlen */ 55 int ylen; /* DMA ylen */ 56 int width; /* DMA width */ 57 int dir; 58 bool cyclic; /* is loop DMA? */ 59 u32 addr; /* DMA buffer address */ 60}; 61 62struct sirfsoc_dma_chan { 63 struct dma_chan chan; 64 struct list_head free; 65 struct list_head prepared; 66 struct list_head queued; 67 struct list_head active; 68 struct list_head completed; 69 unsigned long happened_cyclic; 70 unsigned long completed_cyclic; 71 72 /* Lock for this structure */ 73 spinlock_t lock; 74 75 int mode; 76}; 77 78struct sirfsoc_dma_regs { 79 u32 ctrl[SIRFSOC_DMA_CHANNELS]; 80 u32 interrupt_en; 81}; 82 83struct sirfsoc_dma { 84 struct dma_device dma; 85 struct tasklet_struct tasklet; 86 struct sirfsoc_dma_chan channels[SIRFSOC_DMA_CHANNELS]; 87 void __iomem *base; 88 int irq; 89 struct clk *clk; 90 bool is_marco; 91 struct sirfsoc_dma_regs regs_save; 92}; 93 94#define DRV_NAME "sirfsoc_dma" 95 96static int sirfsoc_dma_runtime_suspend(struct device *dev); 97 98/* Convert struct dma_chan to struct sirfsoc_dma_chan */ 99static inline 100struct sirfsoc_dma_chan *dma_chan_to_sirfsoc_dma_chan(struct dma_chan *c) 101{ 102 return container_of(c, struct sirfsoc_dma_chan, chan); 103} 104 105/* Convert struct dma_chan to struct sirfsoc_dma */ 106static inline struct sirfsoc_dma *dma_chan_to_sirfsoc_dma(struct dma_chan *c) 107{ 108 struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(c); 109 return container_of(schan, struct sirfsoc_dma, channels[c->chan_id]); 110} 111 112/* Execute all queued DMA descriptors */ 113static void sirfsoc_dma_execute(struct sirfsoc_dma_chan *schan) 114{ 115 struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan); 116 int cid = schan->chan.chan_id; 117 struct sirfsoc_dma_desc *sdesc = NULL; 118 119 /* 120 * lock has been held by functions calling this, so we don't hold 121 * lock again 122 */ 123 124 sdesc = list_first_entry(&schan->queued, struct sirfsoc_dma_desc, 125 node); 126 /* Move the first queued descriptor to active list */ 127 list_move_tail(&sdesc->node, &schan->active); 128 129 /* Start the DMA transfer */ 130 writel_relaxed(sdesc->width, sdma->base + SIRFSOC_DMA_WIDTH_0 + 131 cid * 4); 132 writel_relaxed(cid | (schan->mode << SIRFSOC_DMA_MODE_CTRL_BIT) | 133 (sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT), 134 sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL); 135 writel_relaxed(sdesc->xlen, sdma->base + cid * 0x10 + 136 SIRFSOC_DMA_CH_XLEN); 137 writel_relaxed(sdesc->ylen, sdma->base + cid * 0x10 + 138 SIRFSOC_DMA_CH_YLEN); 139 writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) | 140 (1 << cid), sdma->base + SIRFSOC_DMA_INT_EN); 141 142 /* 143 * writel has an implict memory write barrier to make sure data is 144 * flushed into memory before starting DMA 145 */ 146 writel(sdesc->addr >> 2, sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR); 147 148 if (sdesc->cyclic) { 149 writel((1 << cid) | 1 << (cid + 16) | 150 readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL), 151 sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); 152 schan->happened_cyclic = schan->completed_cyclic = 0; 153 } 154} 155 156/* Interrupt handler */ 157static irqreturn_t sirfsoc_dma_irq(int irq, void *data) 158{ 159 struct sirfsoc_dma *sdma = data; 160 struct sirfsoc_dma_chan *schan; 161 struct sirfsoc_dma_desc *sdesc = NULL; 162 u32 is; 163 int ch; 164 165 is = readl(sdma->base + SIRFSOC_DMA_CH_INT); 166 while ((ch = fls(is) - 1) >= 0) { 167 is &= ~(1 << ch); 168 writel_relaxed(1 << ch, sdma->base + SIRFSOC_DMA_CH_INT); 169 schan = &sdma->channels[ch]; 170 171 spin_lock(&schan->lock); 172 173 sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc, 174 node); 175 if (!sdesc->cyclic) { 176 /* Execute queued descriptors */ 177 list_splice_tail_init(&schan->active, &schan->completed); 178 if (!list_empty(&schan->queued)) 179 sirfsoc_dma_execute(schan); 180 } else 181 schan->happened_cyclic++; 182 183 spin_unlock(&schan->lock); 184 } 185 186 /* Schedule tasklet */ 187 tasklet_schedule(&sdma->tasklet); 188 189 return IRQ_HANDLED; 190} 191 192/* process completed descriptors */ 193static void sirfsoc_dma_process_completed(struct sirfsoc_dma *sdma) 194{ 195 dma_cookie_t last_cookie = 0; 196 struct sirfsoc_dma_chan *schan; 197 struct sirfsoc_dma_desc *sdesc; 198 struct dma_async_tx_descriptor *desc; 199 unsigned long flags; 200 unsigned long happened_cyclic; 201 LIST_HEAD(list); 202 int i; 203 204 for (i = 0; i < sdma->dma.chancnt; i++) { 205 schan = &sdma->channels[i]; 206 207 /* Get all completed descriptors */ 208 spin_lock_irqsave(&schan->lock, flags); 209 if (!list_empty(&schan->completed)) { 210 list_splice_tail_init(&schan->completed, &list); 211 spin_unlock_irqrestore(&schan->lock, flags); 212 213 /* Execute callbacks and run dependencies */ 214 list_for_each_entry(sdesc, &list, node) { 215 desc = &sdesc->desc; 216 217 if (desc->callback) 218 desc->callback(desc->callback_param); 219 220 last_cookie = desc->cookie; 221 dma_run_dependencies(desc); 222 } 223 224 /* Free descriptors */ 225 spin_lock_irqsave(&schan->lock, flags); 226 list_splice_tail_init(&list, &schan->free); 227 schan->chan.completed_cookie = last_cookie; 228 spin_unlock_irqrestore(&schan->lock, flags); 229 } else { 230 /* for cyclic channel, desc is always in active list */ 231 sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc, 232 node); 233 234 if (!sdesc || (sdesc && !sdesc->cyclic)) { 235 /* without active cyclic DMA */ 236 spin_unlock_irqrestore(&schan->lock, flags); 237 continue; 238 } 239 240 /* cyclic DMA */ 241 happened_cyclic = schan->happened_cyclic; 242 spin_unlock_irqrestore(&schan->lock, flags); 243 244 desc = &sdesc->desc; 245 while (happened_cyclic != schan->completed_cyclic) { 246 if (desc->callback) 247 desc->callback(desc->callback_param); 248 schan->completed_cyclic++; 249 } 250 } 251 } 252} 253 254/* DMA Tasklet */ 255static void sirfsoc_dma_tasklet(unsigned long data) 256{ 257 struct sirfsoc_dma *sdma = (void *)data; 258 259 sirfsoc_dma_process_completed(sdma); 260} 261 262/* Submit descriptor to hardware */ 263static dma_cookie_t sirfsoc_dma_tx_submit(struct dma_async_tx_descriptor *txd) 264{ 265 struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(txd->chan); 266 struct sirfsoc_dma_desc *sdesc; 267 unsigned long flags; 268 dma_cookie_t cookie; 269 270 sdesc = container_of(txd, struct sirfsoc_dma_desc, desc); 271 272 spin_lock_irqsave(&schan->lock, flags); 273 274 /* Move descriptor to queue */ 275 list_move_tail(&sdesc->node, &schan->queued); 276 277 cookie = dma_cookie_assign(txd); 278 279 spin_unlock_irqrestore(&schan->lock, flags); 280 281 return cookie; 282} 283 284static int sirfsoc_dma_slave_config(struct dma_chan *chan, 285 struct dma_slave_config *config) 286{ 287 struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); 288 unsigned long flags; 289 290 if ((config->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || 291 (config->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)) 292 return -EINVAL; 293 294 spin_lock_irqsave(&schan->lock, flags); 295 schan->mode = (config->src_maxburst == 4 ? 1 : 0); 296 spin_unlock_irqrestore(&schan->lock, flags); 297 298 return 0; 299} 300 301static int sirfsoc_dma_terminate_all(struct dma_chan *chan) 302{ 303 struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); 304 struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan); 305 int cid = schan->chan.chan_id; 306 unsigned long flags; 307 308 spin_lock_irqsave(&schan->lock, flags); 309 310 if (!sdma->is_marco) { 311 writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) & 312 ~(1 << cid), sdma->base + SIRFSOC_DMA_INT_EN); 313 writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL) 314 & ~((1 << cid) | 1 << (cid + 16)), 315 sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); 316 } else { 317 writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_INT_EN_CLR); 318 writel_relaxed((1 << cid) | 1 << (cid + 16), 319 sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL_CLR); 320 } 321 322 writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID); 323 324 list_splice_tail_init(&schan->active, &schan->free); 325 list_splice_tail_init(&schan->queued, &schan->free); 326 327 spin_unlock_irqrestore(&schan->lock, flags); 328 329 return 0; 330} 331 332static int sirfsoc_dma_pause_chan(struct dma_chan *chan) 333{ 334 struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); 335 struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan); 336 int cid = schan->chan.chan_id; 337 unsigned long flags; 338 339 spin_lock_irqsave(&schan->lock, flags); 340 341 if (!sdma->is_marco) 342 writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL) 343 & ~((1 << cid) | 1 << (cid + 16)), 344 sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); 345 else 346 writel_relaxed((1 << cid) | 1 << (cid + 16), 347 sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL_CLR); 348 349 spin_unlock_irqrestore(&schan->lock, flags); 350 351 return 0; 352} 353 354static int sirfsoc_dma_resume_chan(struct dma_chan *chan) 355{ 356 struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); 357 struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan); 358 int cid = schan->chan.chan_id; 359 unsigned long flags; 360 361 spin_lock_irqsave(&schan->lock, flags); 362 363 if (!sdma->is_marco) 364 writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL) 365 | ((1 << cid) | 1 << (cid + 16)), 366 sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); 367 else 368 writel_relaxed((1 << cid) | 1 << (cid + 16), 369 sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); 370 371 spin_unlock_irqrestore(&schan->lock, flags); 372 373 return 0; 374} 375 376/* Alloc channel resources */ 377static int sirfsoc_dma_alloc_chan_resources(struct dma_chan *chan) 378{ 379 struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan); 380 struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); 381 struct sirfsoc_dma_desc *sdesc; 382 unsigned long flags; 383 LIST_HEAD(descs); 384 int i; 385 386 pm_runtime_get_sync(sdma->dma.dev); 387 388 /* Alloc descriptors for this channel */ 389 for (i = 0; i < SIRFSOC_DMA_DESCRIPTORS; i++) { 390 sdesc = kzalloc(sizeof(*sdesc), GFP_KERNEL); 391 if (!sdesc) { 392 dev_notice(sdma->dma.dev, "Memory allocation error. " 393 "Allocated only %u descriptors\n", i); 394 break; 395 } 396 397 dma_async_tx_descriptor_init(&sdesc->desc, chan); 398 sdesc->desc.flags = DMA_CTRL_ACK; 399 sdesc->desc.tx_submit = sirfsoc_dma_tx_submit; 400 401 list_add_tail(&sdesc->node, &descs); 402 } 403 404 /* Return error only if no descriptors were allocated */ 405 if (i == 0) 406 return -ENOMEM; 407 408 spin_lock_irqsave(&schan->lock, flags); 409 410 list_splice_tail_init(&descs, &schan->free); 411 spin_unlock_irqrestore(&schan->lock, flags); 412 413 return i; 414} 415 416/* Free channel resources */ 417static void sirfsoc_dma_free_chan_resources(struct dma_chan *chan) 418{ 419 struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); 420 struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan); 421 struct sirfsoc_dma_desc *sdesc, *tmp; 422 unsigned long flags; 423 LIST_HEAD(descs); 424 425 spin_lock_irqsave(&schan->lock, flags); 426 427 /* Channel must be idle */ 428 BUG_ON(!list_empty(&schan->prepared)); 429 BUG_ON(!list_empty(&schan->queued)); 430 BUG_ON(!list_empty(&schan->active)); 431 BUG_ON(!list_empty(&schan->completed)); 432 433 /* Move data */ 434 list_splice_tail_init(&schan->free, &descs); 435 436 spin_unlock_irqrestore(&schan->lock, flags); 437 438 /* Free descriptors */ 439 list_for_each_entry_safe(sdesc, tmp, &descs, node) 440 kfree(sdesc); 441 442 pm_runtime_put(sdma->dma.dev); 443} 444 445/* Send pending descriptor to hardware */ 446static void sirfsoc_dma_issue_pending(struct dma_chan *chan) 447{ 448 struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); 449 unsigned long flags; 450 451 spin_lock_irqsave(&schan->lock, flags); 452 453 if (list_empty(&schan->active) && !list_empty(&schan->queued)) 454 sirfsoc_dma_execute(schan); 455 456 spin_unlock_irqrestore(&schan->lock, flags); 457} 458 459/* Check request completion status */ 460static enum dma_status 461sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 462 struct dma_tx_state *txstate) 463{ 464 struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan); 465 struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); 466 unsigned long flags; 467 enum dma_status ret; 468 struct sirfsoc_dma_desc *sdesc; 469 int cid = schan->chan.chan_id; 470 unsigned long dma_pos; 471 unsigned long dma_request_bytes; 472 unsigned long residue; 473 474 spin_lock_irqsave(&schan->lock, flags); 475 476 sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc, 477 node); 478 dma_request_bytes = (sdesc->xlen + 1) * (sdesc->ylen + 1) * 479 (sdesc->width * SIRFSOC_DMA_WORD_LEN); 480 481 ret = dma_cookie_status(chan, cookie, txstate); 482 dma_pos = readl_relaxed(sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR) 483 << 2; 484 residue = dma_request_bytes - (dma_pos - sdesc->addr); 485 dma_set_residue(txstate, residue); 486 487 spin_unlock_irqrestore(&schan->lock, flags); 488 489 return ret; 490} 491 492static struct dma_async_tx_descriptor *sirfsoc_dma_prep_interleaved( 493 struct dma_chan *chan, struct dma_interleaved_template *xt, 494 unsigned long flags) 495{ 496 struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan); 497 struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); 498 struct sirfsoc_dma_desc *sdesc = NULL; 499 unsigned long iflags; 500 int ret; 501 502 if ((xt->dir != DMA_MEM_TO_DEV) && (xt->dir != DMA_DEV_TO_MEM)) { 503 ret = -EINVAL; 504 goto err_dir; 505 } 506 507 /* Get free descriptor */ 508 spin_lock_irqsave(&schan->lock, iflags); 509 if (!list_empty(&schan->free)) { 510 sdesc = list_first_entry(&schan->free, struct sirfsoc_dma_desc, 511 node); 512 list_del(&sdesc->node); 513 } 514 spin_unlock_irqrestore(&schan->lock, iflags); 515 516 if (!sdesc) { 517 /* try to free completed descriptors */ 518 sirfsoc_dma_process_completed(sdma); 519 ret = 0; 520 goto no_desc; 521 } 522 523 /* Place descriptor in prepared list */ 524 spin_lock_irqsave(&schan->lock, iflags); 525 526 /* 527 * Number of chunks in a frame can only be 1 for prima2 528 * and ylen (number of frame - 1) must be at least 0 529 */ 530 if ((xt->frame_size == 1) && (xt->numf > 0)) { 531 sdesc->cyclic = 0; 532 sdesc->xlen = xt->sgl[0].size / SIRFSOC_DMA_WORD_LEN; 533 sdesc->width = (xt->sgl[0].size + xt->sgl[0].icg) / 534 SIRFSOC_DMA_WORD_LEN; 535 sdesc->ylen = xt->numf - 1; 536 if (xt->dir == DMA_MEM_TO_DEV) { 537 sdesc->addr = xt->src_start; 538 sdesc->dir = 1; 539 } else { 540 sdesc->addr = xt->dst_start; 541 sdesc->dir = 0; 542 } 543 544 list_add_tail(&sdesc->node, &schan->prepared); 545 } else { 546 pr_err("sirfsoc DMA Invalid xfer\n"); 547 ret = -EINVAL; 548 goto err_xfer; 549 } 550 spin_unlock_irqrestore(&schan->lock, iflags); 551 552 return &sdesc->desc; 553err_xfer: 554 spin_unlock_irqrestore(&schan->lock, iflags); 555no_desc: 556err_dir: 557 return ERR_PTR(ret); 558} 559 560static struct dma_async_tx_descriptor * 561sirfsoc_dma_prep_cyclic(struct dma_chan *chan, dma_addr_t addr, 562 size_t buf_len, size_t period_len, 563 enum dma_transfer_direction direction, unsigned long flags) 564{ 565 struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); 566 struct sirfsoc_dma_desc *sdesc = NULL; 567 unsigned long iflags; 568 569 /* 570 * we only support cycle transfer with 2 period 571 * If the X-length is set to 0, it would be the loop mode. 572 * The DMA address keeps increasing until reaching the end of a loop 573 * area whose size is defined by (DMA_WIDTH x (Y_LENGTH + 1)). Then 574 * the DMA address goes back to the beginning of this area. 575 * In loop mode, the DMA data region is divided into two parts, BUFA 576 * and BUFB. DMA controller generates interrupts twice in each loop: 577 * when the DMA address reaches the end of BUFA or the end of the 578 * BUFB 579 */ 580 if (buf_len != 2 * period_len) 581 return ERR_PTR(-EINVAL); 582 583 /* Get free descriptor */ 584 spin_lock_irqsave(&schan->lock, iflags); 585 if (!list_empty(&schan->free)) { 586 sdesc = list_first_entry(&schan->free, struct sirfsoc_dma_desc, 587 node); 588 list_del(&sdesc->node); 589 } 590 spin_unlock_irqrestore(&schan->lock, iflags); 591 592 if (!sdesc) 593 return NULL; 594 595 /* Place descriptor in prepared list */ 596 spin_lock_irqsave(&schan->lock, iflags); 597 sdesc->addr = addr; 598 sdesc->cyclic = 1; 599 sdesc->xlen = 0; 600 sdesc->ylen = buf_len / SIRFSOC_DMA_WORD_LEN - 1; 601 sdesc->width = 1; 602 list_add_tail(&sdesc->node, &schan->prepared); 603 spin_unlock_irqrestore(&schan->lock, iflags); 604 605 return &sdesc->desc; 606} 607 608/* 609 * The DMA controller consists of 16 independent DMA channels. 610 * Each channel is allocated to a different function 611 */ 612bool sirfsoc_dma_filter_id(struct dma_chan *chan, void *chan_id) 613{ 614 unsigned int ch_nr = (unsigned int) chan_id; 615 616 if (ch_nr == chan->chan_id + 617 chan->device->dev_id * SIRFSOC_DMA_CHANNELS) 618 return true; 619 620 return false; 621} 622EXPORT_SYMBOL(sirfsoc_dma_filter_id); 623 624#define SIRFSOC_DMA_BUSWIDTHS \ 625 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ 626 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 627 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 628 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ 629 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) 630 631static struct dma_chan *of_dma_sirfsoc_xlate(struct of_phandle_args *dma_spec, 632 struct of_dma *ofdma) 633{ 634 struct sirfsoc_dma *sdma = ofdma->of_dma_data; 635 unsigned int request = dma_spec->args[0]; 636 637 if (request >= SIRFSOC_DMA_CHANNELS) 638 return NULL; 639 640 return dma_get_slave_channel(&sdma->channels[request].chan); 641} 642 643static int sirfsoc_dma_probe(struct platform_device *op) 644{ 645 struct device_node *dn = op->dev.of_node; 646 struct device *dev = &op->dev; 647 struct dma_device *dma; 648 struct sirfsoc_dma *sdma; 649 struct sirfsoc_dma_chan *schan; 650 struct resource res; 651 ulong regs_start, regs_size; 652 u32 id; 653 int ret, i; 654 655 sdma = devm_kzalloc(dev, sizeof(*sdma), GFP_KERNEL); 656 if (!sdma) { 657 dev_err(dev, "Memory exhausted!\n"); 658 return -ENOMEM; 659 } 660 661 if (of_device_is_compatible(dn, "sirf,marco-dmac")) 662 sdma->is_marco = true; 663 664 if (of_property_read_u32(dn, "cell-index", &id)) { 665 dev_err(dev, "Fail to get DMAC index\n"); 666 return -ENODEV; 667 } 668 669 sdma->irq = irq_of_parse_and_map(dn, 0); 670 if (sdma->irq == NO_IRQ) { 671 dev_err(dev, "Error mapping IRQ!\n"); 672 return -EINVAL; 673 } 674 675 sdma->clk = devm_clk_get(dev, NULL); 676 if (IS_ERR(sdma->clk)) { 677 dev_err(dev, "failed to get a clock.\n"); 678 return PTR_ERR(sdma->clk); 679 } 680 681 ret = of_address_to_resource(dn, 0, &res); 682 if (ret) { 683 dev_err(dev, "Error parsing memory region!\n"); 684 goto irq_dispose; 685 } 686 687 regs_start = res.start; 688 regs_size = resource_size(&res); 689 690 sdma->base = devm_ioremap(dev, regs_start, regs_size); 691 if (!sdma->base) { 692 dev_err(dev, "Error mapping memory region!\n"); 693 ret = -ENOMEM; 694 goto irq_dispose; 695 } 696 697 ret = request_irq(sdma->irq, &sirfsoc_dma_irq, 0, DRV_NAME, sdma); 698 if (ret) { 699 dev_err(dev, "Error requesting IRQ!\n"); 700 ret = -EINVAL; 701 goto irq_dispose; 702 } 703 704 dma = &sdma->dma; 705 dma->dev = dev; 706 707 dma->device_alloc_chan_resources = sirfsoc_dma_alloc_chan_resources; 708 dma->device_free_chan_resources = sirfsoc_dma_free_chan_resources; 709 dma->device_issue_pending = sirfsoc_dma_issue_pending; 710 dma->device_config = sirfsoc_dma_slave_config; 711 dma->device_pause = sirfsoc_dma_pause_chan; 712 dma->device_resume = sirfsoc_dma_resume_chan; 713 dma->device_terminate_all = sirfsoc_dma_terminate_all; 714 dma->device_tx_status = sirfsoc_dma_tx_status; 715 dma->device_prep_interleaved_dma = sirfsoc_dma_prep_interleaved; 716 dma->device_prep_dma_cyclic = sirfsoc_dma_prep_cyclic; 717 dma->src_addr_widths = SIRFSOC_DMA_BUSWIDTHS; 718 dma->dst_addr_widths = SIRFSOC_DMA_BUSWIDTHS; 719 dma->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 720 721 INIT_LIST_HEAD(&dma->channels); 722 dma_cap_set(DMA_SLAVE, dma->cap_mask); 723 dma_cap_set(DMA_CYCLIC, dma->cap_mask); 724 dma_cap_set(DMA_INTERLEAVE, dma->cap_mask); 725 dma_cap_set(DMA_PRIVATE, dma->cap_mask); 726 727 for (i = 0; i < SIRFSOC_DMA_CHANNELS; i++) { 728 schan = &sdma->channels[i]; 729 730 schan->chan.device = dma; 731 dma_cookie_init(&schan->chan); 732 733 INIT_LIST_HEAD(&schan->free); 734 INIT_LIST_HEAD(&schan->prepared); 735 INIT_LIST_HEAD(&schan->queued); 736 INIT_LIST_HEAD(&schan->active); 737 INIT_LIST_HEAD(&schan->completed); 738 739 spin_lock_init(&schan->lock); 740 list_add_tail(&schan->chan.device_node, &dma->channels); 741 } 742 743 tasklet_init(&sdma->tasklet, sirfsoc_dma_tasklet, (unsigned long)sdma); 744 745 /* Register DMA engine */ 746 dev_set_drvdata(dev, sdma); 747 748 ret = dma_async_device_register(dma); 749 if (ret) 750 goto free_irq; 751 752 /* Device-tree DMA controller registration */ 753 ret = of_dma_controller_register(dn, of_dma_sirfsoc_xlate, sdma); 754 if (ret) { 755 dev_err(dev, "failed to register DMA controller\n"); 756 goto unreg_dma_dev; 757 } 758 759 pm_runtime_enable(&op->dev); 760 dev_info(dev, "initialized SIRFSOC DMAC driver\n"); 761 762 return 0; 763 764unreg_dma_dev: 765 dma_async_device_unregister(dma); 766free_irq: 767 free_irq(sdma->irq, sdma); 768irq_dispose: 769 irq_dispose_mapping(sdma->irq); 770 return ret; 771} 772 773static int sirfsoc_dma_remove(struct platform_device *op) 774{ 775 struct device *dev = &op->dev; 776 struct sirfsoc_dma *sdma = dev_get_drvdata(dev); 777 778 of_dma_controller_free(op->dev.of_node); 779 dma_async_device_unregister(&sdma->dma); 780 free_irq(sdma->irq, sdma); 781 irq_dispose_mapping(sdma->irq); 782 pm_runtime_disable(&op->dev); 783 if (!pm_runtime_status_suspended(&op->dev)) 784 sirfsoc_dma_runtime_suspend(&op->dev); 785 786 return 0; 787} 788 789static int sirfsoc_dma_runtime_suspend(struct device *dev) 790{ 791 struct sirfsoc_dma *sdma = dev_get_drvdata(dev); 792 793 clk_disable_unprepare(sdma->clk); 794 return 0; 795} 796 797static int sirfsoc_dma_runtime_resume(struct device *dev) 798{ 799 struct sirfsoc_dma *sdma = dev_get_drvdata(dev); 800 int ret; 801 802 ret = clk_prepare_enable(sdma->clk); 803 if (ret < 0) { 804 dev_err(dev, "clk_enable failed: %d\n", ret); 805 return ret; 806 } 807 return 0; 808} 809 810#ifdef CONFIG_PM_SLEEP 811static int sirfsoc_dma_pm_suspend(struct device *dev) 812{ 813 struct sirfsoc_dma *sdma = dev_get_drvdata(dev); 814 struct sirfsoc_dma_regs *save = &sdma->regs_save; 815 struct sirfsoc_dma_desc *sdesc; 816 struct sirfsoc_dma_chan *schan; 817 int ch; 818 int ret; 819 820 /* 821 * if we were runtime-suspended before, resume to enable clock 822 * before accessing register 823 */ 824 if (pm_runtime_status_suspended(dev)) { 825 ret = sirfsoc_dma_runtime_resume(dev); 826 if (ret < 0) 827 return ret; 828 } 829 830 /* 831 * DMA controller will lose all registers while suspending 832 * so we need to save registers for active channels 833 */ 834 for (ch = 0; ch < SIRFSOC_DMA_CHANNELS; ch++) { 835 schan = &sdma->channels[ch]; 836 if (list_empty(&schan->active)) 837 continue; 838 sdesc = list_first_entry(&schan->active, 839 struct sirfsoc_dma_desc, 840 node); 841 save->ctrl[ch] = readl_relaxed(sdma->base + 842 ch * 0x10 + SIRFSOC_DMA_CH_CTRL); 843 } 844 save->interrupt_en = readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN); 845 846 /* Disable clock */ 847 sirfsoc_dma_runtime_suspend(dev); 848 849 return 0; 850} 851 852static int sirfsoc_dma_pm_resume(struct device *dev) 853{ 854 struct sirfsoc_dma *sdma = dev_get_drvdata(dev); 855 struct sirfsoc_dma_regs *save = &sdma->regs_save; 856 struct sirfsoc_dma_desc *sdesc; 857 struct sirfsoc_dma_chan *schan; 858 int ch; 859 int ret; 860 861 /* Enable clock before accessing register */ 862 ret = sirfsoc_dma_runtime_resume(dev); 863 if (ret < 0) 864 return ret; 865 866 writel_relaxed(save->interrupt_en, sdma->base + SIRFSOC_DMA_INT_EN); 867 for (ch = 0; ch < SIRFSOC_DMA_CHANNELS; ch++) { 868 schan = &sdma->channels[ch]; 869 if (list_empty(&schan->active)) 870 continue; 871 sdesc = list_first_entry(&schan->active, 872 struct sirfsoc_dma_desc, 873 node); 874 writel_relaxed(sdesc->width, 875 sdma->base + SIRFSOC_DMA_WIDTH_0 + ch * 4); 876 writel_relaxed(sdesc->xlen, 877 sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_XLEN); 878 writel_relaxed(sdesc->ylen, 879 sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_YLEN); 880 writel_relaxed(save->ctrl[ch], 881 sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_CTRL); 882 writel_relaxed(sdesc->addr >> 2, 883 sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_ADDR); 884 } 885 886 /* if we were runtime-suspended before, suspend again */ 887 if (pm_runtime_status_suspended(dev)) 888 sirfsoc_dma_runtime_suspend(dev); 889 890 return 0; 891} 892#endif 893 894static const struct dev_pm_ops sirfsoc_dma_pm_ops = { 895 SET_RUNTIME_PM_OPS(sirfsoc_dma_runtime_suspend, sirfsoc_dma_runtime_resume, NULL) 896 SET_SYSTEM_SLEEP_PM_OPS(sirfsoc_dma_pm_suspend, sirfsoc_dma_pm_resume) 897}; 898 899static const struct of_device_id sirfsoc_dma_match[] = { 900 { .compatible = "sirf,prima2-dmac", }, 901 { .compatible = "sirf,marco-dmac", }, 902 {}, 903}; 904 905static struct platform_driver sirfsoc_dma_driver = { 906 .probe = sirfsoc_dma_probe, 907 .remove = sirfsoc_dma_remove, 908 .driver = { 909 .name = DRV_NAME, 910 .pm = &sirfsoc_dma_pm_ops, 911 .of_match_table = sirfsoc_dma_match, 912 }, 913}; 914 915static __init int sirfsoc_dma_init(void) 916{ 917 return platform_driver_register(&sirfsoc_dma_driver); 918} 919 920static void __exit sirfsoc_dma_exit(void) 921{ 922 platform_driver_unregister(&sirfsoc_dma_driver); 923} 924 925subsys_initcall(sirfsoc_dma_init); 926module_exit(sirfsoc_dma_exit); 927 928MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, " 929 "Barry Song <baohua.song@csr.com>"); 930MODULE_DESCRIPTION("SIRFSOC DMA control driver"); 931MODULE_LICENSE("GPL v2"); 932