1/* 2 * AMD64 class Memory Controller kernel module 3 * 4 * Copyright (c) 2009 SoftwareBitMaker. 5 * Copyright (c) 2009 Advanced Micro Devices, Inc. 6 * 7 * This file may be distributed under the terms of the 8 * GNU General Public License. 9 * 10 * Originally Written by Thayne Harbaugh 11 * 12 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: 13 * - K8 CPU Revision D and greater support 14 * 15 * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>: 16 * - Module largely rewritten, with new (and hopefully correct) 17 * code for dealing with node and chip select interleaving, 18 * various code cleanup, and bug fixes 19 * - Added support for memory hoisting using DRAM hole address 20 * register 21 * 22 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: 23 * -K8 Rev (1207) revision support added, required Revision 24 * specific mini-driver code to support Rev F as well as 25 * prior revisions 26 * 27 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: 28 * -Family 10h revision support added. New PCI Device IDs, 29 * indicating new changes. Actual registers modified 30 * were slight, less than the Rev E to Rev F transition 31 * but changing the PCI Device ID was the proper thing to 32 * do, as it provides for almost automactic family 33 * detection. The mods to Rev F required more family 34 * information detection. 35 * 36 * Changes/Fixes by Borislav Petkov <bp@alien8.de>: 37 * - misc fixes and code cleanups 38 * 39 * This module is based on the following documents 40 * (available from http://www.amd.com/): 41 * 42 * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD 43 * Opteron Processors 44 * AMD publication #: 26094 45 *` Revision: 3.26 46 * 47 * Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh 48 * Processors 49 * AMD publication #: 32559 50 * Revision: 3.00 51 * Issue Date: May 2006 52 * 53 * Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h 54 * Processors 55 * AMD publication #: 31116 56 * Revision: 3.00 57 * Issue Date: September 07, 2007 58 * 59 * Sections in the first 2 documents are no longer in sync with each other. 60 * The Family 10h BKDG was totally re-written from scratch with a new 61 * presentation model. 62 * Therefore, comments that refer to a Document section might be off. 63 */ 64 65#include <linux/module.h> 66#include <linux/ctype.h> 67#include <linux/init.h> 68#include <linux/pci.h> 69#include <linux/pci_ids.h> 70#include <linux/slab.h> 71#include <linux/mmzone.h> 72#include <linux/edac.h> 73#include <asm/msr.h> 74#include "edac_core.h" 75#include "mce_amd.h" 76 77#define amd64_debug(fmt, arg...) \ 78 edac_printk(KERN_DEBUG, "amd64", fmt, ##arg) 79 80#define amd64_info(fmt, arg...) \ 81 edac_printk(KERN_INFO, "amd64", fmt, ##arg) 82 83#define amd64_notice(fmt, arg...) \ 84 edac_printk(KERN_NOTICE, "amd64", fmt, ##arg) 85 86#define amd64_warn(fmt, arg...) \ 87 edac_printk(KERN_WARNING, "amd64", fmt, ##arg) 88 89#define amd64_err(fmt, arg...) \ 90 edac_printk(KERN_ERR, "amd64", fmt, ##arg) 91 92#define amd64_mc_warn(mci, fmt, arg...) \ 93 edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg) 94 95#define amd64_mc_err(mci, fmt, arg...) \ 96 edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg) 97 98/* 99 * Throughout the comments in this code, the following terms are used: 100 * 101 * SysAddr, DramAddr, and InputAddr 102 * 103 * These terms come directly from the amd64 documentation 104 * (AMD publication #26094). They are defined as follows: 105 * 106 * SysAddr: 107 * This is a physical address generated by a CPU core or a device 108 * doing DMA. If generated by a CPU core, a SysAddr is the result of 109 * a virtual to physical address translation by the CPU core's address 110 * translation mechanism (MMU). 111 * 112 * DramAddr: 113 * A DramAddr is derived from a SysAddr by subtracting an offset that 114 * depends on which node the SysAddr maps to and whether the SysAddr 115 * is within a range affected by memory hoisting. The DRAM Base 116 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers 117 * determine which node a SysAddr maps to. 118 * 119 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr 120 * is within the range of addresses specified by this register, then 121 * a value x from the DHAR is subtracted from the SysAddr to produce a 122 * DramAddr. Here, x represents the base address for the node that 123 * the SysAddr maps to plus an offset due to memory hoisting. See 124 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and 125 * sys_addr_to_dram_addr() below for more information. 126 * 127 * If the SysAddr is not affected by the DHAR then a value y is 128 * subtracted from the SysAddr to produce a DramAddr. Here, y is the 129 * base address for the node that the SysAddr maps to. See section 130 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more 131 * information. 132 * 133 * InputAddr: 134 * A DramAddr is translated to an InputAddr before being passed to the 135 * memory controller for the node that the DramAddr is associated 136 * with. The memory controller then maps the InputAddr to a csrow. 137 * If node interleaving is not in use, then the InputAddr has the same 138 * value as the DramAddr. Otherwise, the InputAddr is produced by 139 * discarding the bits used for node interleaving from the DramAddr. 140 * See section 3.4.4 for more information. 141 * 142 * The memory controller for a given node uses its DRAM CS Base and 143 * DRAM CS Mask registers to map an InputAddr to a csrow. See 144 * sections 3.5.4 and 3.5.5 for more information. 145 */ 146 147#define EDAC_AMD64_VERSION "3.4.0" 148#define EDAC_MOD_STR "amd64_edac" 149 150/* Extended Model from CPUID, for CPU Revision numbers */ 151#define K8_REV_D 1 152#define K8_REV_E 2 153#define K8_REV_F 4 154 155/* Hardware limit on ChipSelect rows per MC and processors per system */ 156#define NUM_CHIPSELECTS 8 157#define DRAM_RANGES 8 158 159#define ON true 160#define OFF false 161 162/* 163 * PCI-defined configuration space registers 164 */ 165#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 166#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 167#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b 168#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c 169#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571 170#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572 171#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531 172#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532 173#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581 174#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582 175 176/* 177 * Function 1 - Address Map 178 */ 179#define DRAM_BASE_LO 0x40 180#define DRAM_LIMIT_LO 0x44 181 182/* 183 * F15 M30h D18F1x2[1C:00] 184 */ 185#define DRAM_CONT_BASE 0x200 186#define DRAM_CONT_LIMIT 0x204 187 188/* 189 * F15 M30h D18F1x2[4C:40] 190 */ 191#define DRAM_CONT_HIGH_OFF 0x240 192 193#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3)) 194#define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7)) 195#define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7)) 196 197#define DHAR 0xf0 198#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) 199#define dhar_base(pvt) ((pvt)->dhar & 0xff000000) 200#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16) 201 202 /* NOTE: Extra mask bit vs K8 */ 203#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16) 204 205#define DCT_CFG_SEL 0x10C 206 207#define DRAM_LOCAL_NODE_BASE 0x120 208#define DRAM_LOCAL_NODE_LIM 0x124 209 210#define DRAM_BASE_HI 0x140 211#define DRAM_LIMIT_HI 0x144 212 213 214/* 215 * Function 2 - DRAM controller 216 */ 217#define DCSB0 0x40 218#define DCSB1 0x140 219#define DCSB_CS_ENABLE BIT(0) 220 221#define DCSM0 0x60 222#define DCSM1 0x160 223 224#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) 225 226#define DRAM_CONTROL 0x78 227 228#define DBAM0 0x80 229#define DBAM1 0x180 230 231/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ 232#define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF) 233 234#define DBAM_MAX_VALUE 11 235 236#define DCLR0 0x90 237#define DCLR1 0x190 238#define REVE_WIDTH_128 BIT(16) 239#define WIDTH_128 BIT(11) 240 241#define DCHR0 0x94 242#define DCHR1 0x194 243#define DDR3_MODE BIT(8) 244 245#define DCT_SEL_LO 0x110 246#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0)) 247#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2)) 248 249#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4))) 250 251#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5)) 252#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10)) 253 254#define SWAP_INTLV_REG 0x10c 255 256#define DCT_SEL_HI 0x114 257 258/* 259 * Function 3 - Misc Control 260 */ 261#define NBCTL 0x40 262 263#define NBCFG 0x44 264#define NBCFG_CHIPKILL BIT(23) 265#define NBCFG_ECC_ENABLE BIT(22) 266 267/* F3x48: NBSL */ 268#define F10_NBSL_EXT_ERR_ECC 0x8 269#define NBSL_PP_OBS 0x2 270 271#define SCRCTRL 0x58 272 273#define F10_ONLINE_SPARE 0xB0 274#define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1) 275#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7) 276 277#define F10_NB_ARRAY_ADDR 0xB8 278#define F10_NB_ARRAY_DRAM BIT(31) 279 280/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ 281#define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1) 282 283#define F10_NB_ARRAY_DATA 0xBC 284#define F10_NB_ARR_ECC_WR_REQ BIT(17) 285#define SET_NB_DRAM_INJECTION_WRITE(inj) \ 286 (BIT(((inj.word) & 0xF) + 20) | \ 287 F10_NB_ARR_ECC_WR_REQ | inj.bit_map) 288#define SET_NB_DRAM_INJECTION_READ(inj) \ 289 (BIT(((inj.word) & 0xF) + 20) | \ 290 BIT(16) | inj.bit_map) 291 292 293#define NBCAP 0xE8 294#define NBCAP_CHIPKILL BIT(4) 295#define NBCAP_SECDED BIT(3) 296#define NBCAP_DCT_DUAL BIT(0) 297 298#define EXT_NB_MCA_CFG 0x180 299 300/* MSRs */ 301#define MSR_MCGCTL_NBE BIT(4) 302 303enum amd_families { 304 K8_CPUS = 0, 305 F10_CPUS, 306 F15_CPUS, 307 F15_M30H_CPUS, 308 F15_M60H_CPUS, 309 F16_CPUS, 310 F16_M30H_CPUS, 311 NUM_FAMILIES, 312}; 313 314/* Error injection control structure */ 315struct error_injection { 316 u32 section; 317 u32 word; 318 u32 bit_map; 319}; 320 321/* low and high part of PCI config space regs */ 322struct reg_pair { 323 u32 lo, hi; 324}; 325 326/* 327 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers 328 */ 329struct dram_range { 330 struct reg_pair base; 331 struct reg_pair lim; 332}; 333 334/* A DCT chip selects collection */ 335struct chip_select { 336 u32 csbases[NUM_CHIPSELECTS]; 337 u8 b_cnt; 338 339 u32 csmasks[NUM_CHIPSELECTS]; 340 u8 m_cnt; 341}; 342 343struct amd64_pvt { 344 struct low_ops *ops; 345 346 /* pci_device handles which we utilize */ 347 struct pci_dev *F1, *F2, *F3; 348 349 u16 mc_node_id; /* MC index of this MC node */ 350 u8 fam; /* CPU family */ 351 u8 model; /* ... model */ 352 u8 stepping; /* ... stepping */ 353 354 int ext_model; /* extended model value of this node */ 355 int channel_count; 356 357 /* Raw registers */ 358 u32 dclr0; /* DRAM Configuration Low DCT0 reg */ 359 u32 dclr1; /* DRAM Configuration Low DCT1 reg */ 360 u32 dchr0; /* DRAM Configuration High DCT0 reg */ 361 u32 dchr1; /* DRAM Configuration High DCT1 reg */ 362 u32 nbcap; /* North Bridge Capabilities */ 363 u32 nbcfg; /* F10 North Bridge Configuration */ 364 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */ 365 u32 dhar; /* DRAM Hoist reg */ 366 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ 367 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ 368 369 /* one for each DCT */ 370 struct chip_select csels[2]; 371 372 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ 373 struct dram_range ranges[DRAM_RANGES]; 374 375 u64 top_mem; /* top of memory below 4GB */ 376 u64 top_mem2; /* top of memory above 4GB */ 377 378 u32 dct_sel_lo; /* DRAM Controller Select Low */ 379 u32 dct_sel_hi; /* DRAM Controller Select High */ 380 u32 online_spare; /* On-Line spare Reg */ 381 382 /* x4 or x8 syndromes in use */ 383 u8 ecc_sym_sz; 384 385 /* place to store error injection parameters prior to issue */ 386 struct error_injection injection; 387 388 /* cache the dram_type */ 389 enum mem_type dram_type; 390}; 391 392enum err_codes { 393 DECODE_OK = 0, 394 ERR_NODE = -1, 395 ERR_CSROW = -2, 396 ERR_CHANNEL = -3, 397}; 398 399struct err_info { 400 int err_code; 401 struct mem_ctl_info *src_mci; 402 int csrow; 403 int channel; 404 u16 syndrome; 405 u32 page; 406 u32 offset; 407}; 408 409static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i) 410{ 411 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; 412 413 if (boot_cpu_data.x86 == 0xf) 414 return addr; 415 416 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; 417} 418 419static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i) 420{ 421 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff; 422 423 if (boot_cpu_data.x86 == 0xf) 424 return lim; 425 426 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; 427} 428 429static inline u16 extract_syndrome(u64 status) 430{ 431 return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00); 432} 433 434static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt) 435{ 436 if (pvt->fam == 0x15 && pvt->model >= 0x30) 437 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) | 438 ((pvt->dct_sel_lo >> 6) & 0x3); 439 440 return ((pvt)->dct_sel_lo >> 6) & 0x3; 441} 442/* 443 * per-node ECC settings descriptor 444 */ 445struct ecc_settings { 446 u32 old_nbctl; 447 bool nbctl_valid; 448 449 struct flags { 450 unsigned long nb_mce_enable:1; 451 unsigned long nb_ecc_prev:1; 452 } flags; 453}; 454 455#ifdef CONFIG_EDAC_DEBUG 456extern const struct attribute_group amd64_edac_dbg_group; 457#endif 458 459#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION 460extern const struct attribute_group amd64_edac_inj_group; 461#endif 462 463/* 464 * Each of the PCI Device IDs types have their own set of hardware accessor 465 * functions and per device encoding/decoding logic. 466 */ 467struct low_ops { 468 int (*early_channel_count) (struct amd64_pvt *pvt); 469 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr, 470 struct err_info *); 471 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, 472 unsigned cs_mode, int cs_mask_nr); 473}; 474 475struct amd64_family_type { 476 const char *ctl_name; 477 u16 f1_id, f3_id; 478 struct low_ops ops; 479}; 480 481int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, 482 u32 *val, const char *func); 483int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, 484 u32 val, const char *func); 485 486#define amd64_read_pci_cfg(pdev, offset, val) \ 487 __amd64_read_pci_cfg_dword(pdev, offset, val, __func__) 488 489#define amd64_write_pci_cfg(pdev, offset, val) \ 490 __amd64_write_pci_cfg_dword(pdev, offset, val, __func__) 491 492int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, 493 u64 *hole_offset, u64 *hole_size); 494 495#define to_mci(k) container_of(k, struct mem_ctl_info, dev) 496 497/* Injection helpers */ 498static inline void disable_caches(void *dummy) 499{ 500 write_cr0(read_cr0() | X86_CR0_CD); 501 wbinvd(); 502} 503 504static inline void enable_caches(void *dummy) 505{ 506 write_cr0(read_cr0() & ~X86_CR0_CD); 507} 508 509static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i) 510{ 511 if (pvt->fam == 0x15 && pvt->model >= 0x30) { 512 u32 tmp; 513 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp); 514 return (u8) tmp & 0xF; 515 } 516 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7; 517} 518 519static inline u8 dhar_valid(struct amd64_pvt *pvt) 520{ 521 if (pvt->fam == 0x15 && pvt->model >= 0x30) { 522 u32 tmp; 523 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); 524 return (tmp >> 1) & BIT(0); 525 } 526 return (pvt)->dhar & BIT(0); 527} 528 529static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt) 530{ 531 if (pvt->fam == 0x15 && pvt->model >= 0x30) { 532 u32 tmp; 533 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); 534 return (tmp >> 11) & 0x1FFF; 535 } 536 return (pvt)->dct_sel_lo & 0xFFFFF800; 537} 538