1/*
2 * Generic driver for memory-mapped GPIO controllers.
3 *
4 * Copyright 2008 MontaVista Software, Inc.
5 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
6 *
7 * This program is free software; you can redistribute  it and/or modify it
8 * under  the terms of  the GNU General  Public License as published by the
9 * Free Software Foundation;  either version 2 of the  License, or (at your
10 * option) any later version.
11 *
12 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
13 * ...``                                                         ```````..
14 * ..The simplest form of a GPIO controller that the driver supports is``
15 *  `.just a single "data" register, where GPIO state can be read and/or `
16 *    `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
17 *        `````````
18                                    ___
19_/~~|___/~|   . ```~~~~~~       ___/___\___     ,~.`.`.`.`````.~~...,,,,...
20__________|~$@~~~        %~    /o*o*o*o*o*o\   .. Implementing such a GPIO .
21o        `                     ~~~~\___/~~~~    ` controller in FPGA is ,.`
22                                                 `....trivial..'~`.```.```
23 *                                                    ```````
24 *  .```````~~~~`..`.``.``.
25 * .  The driver supports  `...       ,..```.`~~~```````````````....````.``,,
26 * .   big-endian notation, just`.  .. A bit more sophisticated controllers ,
27 *  . register the device with -be`. .with a pair of set/clear-bit registers ,
28 *   `.. suffix.  ```~~`````....`.`   . affecting the data register and the .`
29 *     ``.`.``...```                  ```.. output pins are also supported.`
30 *                        ^^             `````.`````````.,``~``~``~~``````
31 *                                                   .                  ^^
32 *   ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
33 * .. The expectation is that in at least some cases .    ,-~~~-,
34 *  .this will be used with roll-your-own ASIC/FPGA .`     \   /
35 *  .logic in Verilog or VHDL. ~~~`````````..`````~~`       \ /
36 *  ..````````......```````````                             \o_
37 *                                                           |
38 *                              ^^                          / \
39 *
40 *           ...`````~~`.....``.`..........``````.`.``.```........``.
41 *            `  8, 16, 32 and 64 bits registers are supported, and``.
42 *            . the number of GPIOs is determined by the width of   ~
43 *             .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
44 *               `.......````.```
45 */
46
47#include <linux/init.h>
48#include <linux/err.h>
49#include <linux/bug.h>
50#include <linux/kernel.h>
51#include <linux/module.h>
52#include <linux/spinlock.h>
53#include <linux/compiler.h>
54#include <linux/types.h>
55#include <linux/errno.h>
56#include <linux/log2.h>
57#include <linux/ioport.h>
58#include <linux/io.h>
59#include <linux/gpio.h>
60#include <linux/slab.h>
61#include <linux/platform_device.h>
62#include <linux/mod_devicetable.h>
63#include <linux/basic_mmio_gpio.h>
64
65static void bgpio_write8(void __iomem *reg, unsigned long data)
66{
67	writeb(data, reg);
68}
69
70static unsigned long bgpio_read8(void __iomem *reg)
71{
72	return readb(reg);
73}
74
75static void bgpio_write16(void __iomem *reg, unsigned long data)
76{
77	writew(data, reg);
78}
79
80static unsigned long bgpio_read16(void __iomem *reg)
81{
82	return readw(reg);
83}
84
85static void bgpio_write32(void __iomem *reg, unsigned long data)
86{
87	writel(data, reg);
88}
89
90static unsigned long bgpio_read32(void __iomem *reg)
91{
92	return readl(reg);
93}
94
95#if BITS_PER_LONG >= 64
96static void bgpio_write64(void __iomem *reg, unsigned long data)
97{
98	writeq(data, reg);
99}
100
101static unsigned long bgpio_read64(void __iomem *reg)
102{
103	return readq(reg);
104}
105#endif /* BITS_PER_LONG >= 64 */
106
107static void bgpio_write16be(void __iomem *reg, unsigned long data)
108{
109	iowrite16be(data, reg);
110}
111
112static unsigned long bgpio_read16be(void __iomem *reg)
113{
114	return ioread16be(reg);
115}
116
117static void bgpio_write32be(void __iomem *reg, unsigned long data)
118{
119	iowrite32be(data, reg);
120}
121
122static unsigned long bgpio_read32be(void __iomem *reg)
123{
124	return ioread32be(reg);
125}
126
127static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
128{
129	return 1 << pin;
130}
131
132static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
133				       unsigned int pin)
134{
135	return 1 << (bgc->bits - 1 - pin);
136}
137
138static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
139{
140	struct bgpio_chip *bgc = to_bgpio_chip(gc);
141
142	return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
143}
144
145static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
146{
147	struct bgpio_chip *bgc = to_bgpio_chip(gc);
148	unsigned long mask = bgc->pin2mask(bgc, gpio);
149	unsigned long flags;
150
151	spin_lock_irqsave(&bgc->lock, flags);
152
153	if (val)
154		bgc->data |= mask;
155	else
156		bgc->data &= ~mask;
157
158	bgc->write_reg(bgc->reg_dat, bgc->data);
159
160	spin_unlock_irqrestore(&bgc->lock, flags);
161}
162
163static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
164				 int val)
165{
166	struct bgpio_chip *bgc = to_bgpio_chip(gc);
167	unsigned long mask = bgc->pin2mask(bgc, gpio);
168
169	if (val)
170		bgc->write_reg(bgc->reg_set, mask);
171	else
172		bgc->write_reg(bgc->reg_clr, mask);
173}
174
175static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
176{
177	struct bgpio_chip *bgc = to_bgpio_chip(gc);
178	unsigned long mask = bgc->pin2mask(bgc, gpio);
179	unsigned long flags;
180
181	spin_lock_irqsave(&bgc->lock, flags);
182
183	if (val)
184		bgc->data |= mask;
185	else
186		bgc->data &= ~mask;
187
188	bgc->write_reg(bgc->reg_set, bgc->data);
189
190	spin_unlock_irqrestore(&bgc->lock, flags);
191}
192
193static void bgpio_multiple_get_masks(struct bgpio_chip *bgc,
194				     unsigned long *mask, unsigned long *bits,
195				     unsigned long *set_mask,
196				     unsigned long *clear_mask)
197{
198	int i;
199
200	*set_mask = 0;
201	*clear_mask = 0;
202
203	for (i = 0; i < bgc->bits; i++) {
204		if (*mask == 0)
205			break;
206		if (__test_and_clear_bit(i, mask)) {
207			if (test_bit(i, bits))
208				*set_mask |= bgc->pin2mask(bgc, i);
209			else
210				*clear_mask |= bgc->pin2mask(bgc, i);
211		}
212	}
213}
214
215static void bgpio_set_multiple_single_reg(struct bgpio_chip *bgc,
216					  unsigned long *mask,
217					  unsigned long *bits,
218					  void __iomem *reg)
219{
220	unsigned long flags;
221	unsigned long set_mask, clear_mask;
222
223	spin_lock_irqsave(&bgc->lock, flags);
224
225	bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);
226
227	bgc->data |= set_mask;
228	bgc->data &= ~clear_mask;
229
230	bgc->write_reg(reg, bgc->data);
231
232	spin_unlock_irqrestore(&bgc->lock, flags);
233}
234
235static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
236			       unsigned long *bits)
237{
238	struct bgpio_chip *bgc = to_bgpio_chip(gc);
239
240	bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_dat);
241}
242
243static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
244				   unsigned long *bits)
245{
246	struct bgpio_chip *bgc = to_bgpio_chip(gc);
247
248	bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_set);
249}
250
251static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
252					  unsigned long *mask,
253					  unsigned long *bits)
254{
255	struct bgpio_chip *bgc = to_bgpio_chip(gc);
256	unsigned long set_mask, clear_mask;
257
258	bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);
259
260	if (set_mask)
261		bgc->write_reg(bgc->reg_set, set_mask);
262	if (clear_mask)
263		bgc->write_reg(bgc->reg_clr, clear_mask);
264}
265
266static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
267{
268	return 0;
269}
270
271static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
272				int val)
273{
274	gc->set(gc, gpio, val);
275
276	return 0;
277}
278
279static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
280{
281	struct bgpio_chip *bgc = to_bgpio_chip(gc);
282	unsigned long flags;
283
284	spin_lock_irqsave(&bgc->lock, flags);
285
286	bgc->dir &= ~bgc->pin2mask(bgc, gpio);
287	bgc->write_reg(bgc->reg_dir, bgc->dir);
288
289	spin_unlock_irqrestore(&bgc->lock, flags);
290
291	return 0;
292}
293
294static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
295{
296	struct bgpio_chip *bgc = to_bgpio_chip(gc);
297	unsigned long flags;
298
299	gc->set(gc, gpio, val);
300
301	spin_lock_irqsave(&bgc->lock, flags);
302
303	bgc->dir |= bgc->pin2mask(bgc, gpio);
304	bgc->write_reg(bgc->reg_dir, bgc->dir);
305
306	spin_unlock_irqrestore(&bgc->lock, flags);
307
308	return 0;
309}
310
311static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
312{
313	struct bgpio_chip *bgc = to_bgpio_chip(gc);
314	unsigned long flags;
315
316	spin_lock_irqsave(&bgc->lock, flags);
317
318	bgc->dir |= bgc->pin2mask(bgc, gpio);
319	bgc->write_reg(bgc->reg_dir, bgc->dir);
320
321	spin_unlock_irqrestore(&bgc->lock, flags);
322
323	return 0;
324}
325
326static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
327{
328	struct bgpio_chip *bgc = to_bgpio_chip(gc);
329	unsigned long flags;
330
331	gc->set(gc, gpio, val);
332
333	spin_lock_irqsave(&bgc->lock, flags);
334
335	bgc->dir &= ~bgc->pin2mask(bgc, gpio);
336	bgc->write_reg(bgc->reg_dir, bgc->dir);
337
338	spin_unlock_irqrestore(&bgc->lock, flags);
339
340	return 0;
341}
342
343static int bgpio_setup_accessors(struct device *dev,
344				 struct bgpio_chip *bgc,
345				 bool bit_be,
346				 bool byte_be)
347{
348
349	switch (bgc->bits) {
350	case 8:
351		bgc->read_reg	= bgpio_read8;
352		bgc->write_reg	= bgpio_write8;
353		break;
354	case 16:
355		if (byte_be) {
356			bgc->read_reg	= bgpio_read16be;
357			bgc->write_reg	= bgpio_write16be;
358		} else {
359			bgc->read_reg	= bgpio_read16;
360			bgc->write_reg	= bgpio_write16;
361		}
362		break;
363	case 32:
364		if (byte_be) {
365			bgc->read_reg	= bgpio_read32be;
366			bgc->write_reg	= bgpio_write32be;
367		} else {
368			bgc->read_reg	= bgpio_read32;
369			bgc->write_reg	= bgpio_write32;
370		}
371		break;
372#if BITS_PER_LONG >= 64
373	case 64:
374		if (byte_be) {
375			dev_err(dev,
376				"64 bit big endian byte order unsupported\n");
377			return -EINVAL;
378		} else {
379			bgc->read_reg	= bgpio_read64;
380			bgc->write_reg	= bgpio_write64;
381		}
382		break;
383#endif /* BITS_PER_LONG >= 64 */
384	default:
385		dev_err(dev, "unsupported data width %u bits\n", bgc->bits);
386		return -EINVAL;
387	}
388
389	bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
390
391	return 0;
392}
393
394/*
395 * Create the device and allocate the resources.  For setting GPIO's there are
396 * three supported configurations:
397 *
398 *	- single input/output register resource (named "dat").
399 *	- set/clear pair (named "set" and "clr").
400 *	- single output register resource and single input resource ("set" and
401 *	dat").
402 *
403 * For the single output register, this drives a 1 by setting a bit and a zero
404 * by clearing a bit.  For the set clr pair, this drives a 1 by setting a bit
405 * in the set register and clears it by setting a bit in the clear register.
406 * The configuration is detected by which resources are present.
407 *
408 * For setting the GPIO direction, there are three supported configurations:
409 *
410 *	- simple bidirection GPIO that requires no configuration.
411 *	- an output direction register (named "dirout") where a 1 bit
412 *	indicates the GPIO is an output.
413 *	- an input direction register (named "dirin") where a 1 bit indicates
414 *	the GPIO is an input.
415 */
416static int bgpio_setup_io(struct bgpio_chip *bgc,
417			  void __iomem *dat,
418			  void __iomem *set,
419			  void __iomem *clr)
420{
421
422	bgc->reg_dat = dat;
423	if (!bgc->reg_dat)
424		return -EINVAL;
425
426	if (set && clr) {
427		bgc->reg_set = set;
428		bgc->reg_clr = clr;
429		bgc->gc.set = bgpio_set_with_clear;
430		bgc->gc.set_multiple = bgpio_set_multiple_with_clear;
431	} else if (set && !clr) {
432		bgc->reg_set = set;
433		bgc->gc.set = bgpio_set_set;
434		bgc->gc.set_multiple = bgpio_set_multiple_set;
435	} else {
436		bgc->gc.set = bgpio_set;
437		bgc->gc.set_multiple = bgpio_set_multiple;
438	}
439
440	bgc->gc.get = bgpio_get;
441
442	return 0;
443}
444
445static int bgpio_setup_direction(struct bgpio_chip *bgc,
446				 void __iomem *dirout,
447				 void __iomem *dirin)
448{
449	if (dirout && dirin) {
450		return -EINVAL;
451	} else if (dirout) {
452		bgc->reg_dir = dirout;
453		bgc->gc.direction_output = bgpio_dir_out;
454		bgc->gc.direction_input = bgpio_dir_in;
455	} else if (dirin) {
456		bgc->reg_dir = dirin;
457		bgc->gc.direction_output = bgpio_dir_out_inv;
458		bgc->gc.direction_input = bgpio_dir_in_inv;
459	} else {
460		bgc->gc.direction_output = bgpio_simple_dir_out;
461		bgc->gc.direction_input = bgpio_simple_dir_in;
462	}
463
464	return 0;
465}
466
467static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
468{
469	if (gpio_pin < chip->ngpio)
470		return 0;
471
472	return -EINVAL;
473}
474
475int bgpio_remove(struct bgpio_chip *bgc)
476{
477	gpiochip_remove(&bgc->gc);
478	return 0;
479}
480EXPORT_SYMBOL_GPL(bgpio_remove);
481
482int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
483	       unsigned long sz, void __iomem *dat, void __iomem *set,
484	       void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
485	       unsigned long flags)
486{
487	int ret;
488
489	if (!is_power_of_2(sz))
490		return -EINVAL;
491
492	bgc->bits = sz * 8;
493	if (bgc->bits > BITS_PER_LONG)
494		return -EINVAL;
495
496	spin_lock_init(&bgc->lock);
497	bgc->gc.dev = dev;
498	bgc->gc.label = dev_name(dev);
499	bgc->gc.base = -1;
500	bgc->gc.ngpio = bgc->bits;
501	bgc->gc.request = bgpio_request;
502
503	ret = bgpio_setup_io(bgc, dat, set, clr);
504	if (ret)
505		return ret;
506
507	ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN,
508				    flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
509	if (ret)
510		return ret;
511
512	ret = bgpio_setup_direction(bgc, dirout, dirin);
513	if (ret)
514		return ret;
515
516	bgc->data = bgc->read_reg(bgc->reg_dat);
517	if (bgc->gc.set == bgpio_set_set &&
518			!(flags & BGPIOF_UNREADABLE_REG_SET))
519		bgc->data = bgc->read_reg(bgc->reg_set);
520	if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
521		bgc->dir = bgc->read_reg(bgc->reg_dir);
522
523	return ret;
524}
525EXPORT_SYMBOL_GPL(bgpio_init);
526
527#ifdef CONFIG_GPIO_GENERIC_PLATFORM
528
529static void __iomem *bgpio_map(struct platform_device *pdev,
530			       const char *name,
531			       resource_size_t sane_sz,
532			       int *err)
533{
534	struct device *dev = &pdev->dev;
535	struct resource *r;
536	resource_size_t start;
537	resource_size_t sz;
538	void __iomem *ret;
539
540	*err = 0;
541
542	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
543	if (!r)
544		return NULL;
545
546	sz = resource_size(r);
547	if (sz != sane_sz) {
548		*err = -EINVAL;
549		return NULL;
550	}
551
552	start = r->start;
553	if (!devm_request_mem_region(dev, start, sz, r->name)) {
554		*err = -EBUSY;
555		return NULL;
556	}
557
558	ret = devm_ioremap(dev, start, sz);
559	if (!ret) {
560		*err = -ENOMEM;
561		return NULL;
562	}
563
564	return ret;
565}
566
567static int bgpio_pdev_probe(struct platform_device *pdev)
568{
569	struct device *dev = &pdev->dev;
570	struct resource *r;
571	void __iomem *dat;
572	void __iomem *set;
573	void __iomem *clr;
574	void __iomem *dirout;
575	void __iomem *dirin;
576	unsigned long sz;
577	unsigned long flags = pdev->id_entry->driver_data;
578	int err;
579	struct bgpio_chip *bgc;
580	struct bgpio_pdata *pdata = dev_get_platdata(dev);
581
582	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
583	if (!r)
584		return -EINVAL;
585
586	sz = resource_size(r);
587
588	dat = bgpio_map(pdev, "dat", sz, &err);
589	if (!dat)
590		return err ? err : -EINVAL;
591
592	set = bgpio_map(pdev, "set", sz, &err);
593	if (err)
594		return err;
595
596	clr = bgpio_map(pdev, "clr", sz, &err);
597	if (err)
598		return err;
599
600	dirout = bgpio_map(pdev, "dirout", sz, &err);
601	if (err)
602		return err;
603
604	dirin = bgpio_map(pdev, "dirin", sz, &err);
605	if (err)
606		return err;
607
608	bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
609	if (!bgc)
610		return -ENOMEM;
611
612	err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
613	if (err)
614		return err;
615
616	if (pdata) {
617		if (pdata->label)
618			bgc->gc.label = pdata->label;
619		bgc->gc.base = pdata->base;
620		if (pdata->ngpio > 0)
621			bgc->gc.ngpio = pdata->ngpio;
622	}
623
624	platform_set_drvdata(pdev, bgc);
625
626	return gpiochip_add(&bgc->gc);
627}
628
629static int bgpio_pdev_remove(struct platform_device *pdev)
630{
631	struct bgpio_chip *bgc = platform_get_drvdata(pdev);
632
633	return bgpio_remove(bgc);
634}
635
636static const struct platform_device_id bgpio_id_table[] = {
637	{
638		.name		= "basic-mmio-gpio",
639		.driver_data	= 0,
640	}, {
641		.name		= "basic-mmio-gpio-be",
642		.driver_data	= BGPIOF_BIG_ENDIAN,
643	},
644	{ }
645};
646MODULE_DEVICE_TABLE(platform, bgpio_id_table);
647
648static struct platform_driver bgpio_driver = {
649	.driver = {
650		.name = "basic-mmio-gpio",
651	},
652	.id_table = bgpio_id_table,
653	.probe = bgpio_pdev_probe,
654	.remove = bgpio_pdev_remove,
655};
656
657module_platform_driver(bgpio_driver);
658
659#endif /* CONFIG_GPIO_GENERIC_PLATFORM */
660
661MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
662MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
663MODULE_LICENSE("GPL");
664