1/*
2 * GPIOs on MPC512x/8349/8572/8610 and compatible
3 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2.  This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/of_gpio.h>
17#include <linux/of_irq.h>
18#include <linux/of_platform.h>
19#include <linux/gpio.h>
20#include <linux/slab.h>
21#include <linux/irq.h>
22
23#define MPC8XXX_GPIO_PINS	32
24
25#define GPIO_DIR		0x00
26#define GPIO_ODR		0x04
27#define GPIO_DAT		0x08
28#define GPIO_IER		0x0c
29#define GPIO_IMR		0x10
30#define GPIO_ICR		0x14
31#define GPIO_ICR2		0x18
32
33struct mpc8xxx_gpio_chip {
34	struct of_mm_gpio_chip mm_gc;
35	spinlock_t lock;
36
37	/*
38	 * shadowed data register to be able to clear/set output pins in
39	 * open drain mode safely
40	 */
41	u32 data;
42	struct irq_domain *irq;
43	unsigned int irqn;
44	const void *of_dev_id_data;
45};
46
47static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
48{
49	return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
50}
51
52static inline struct mpc8xxx_gpio_chip *
53to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
54{
55	return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
56}
57
58static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
59{
60	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
61
62	mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
63}
64
65/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
66 * defined as output cannot be determined by reading GPDAT register,
67 * so we use shadow data register instead. The status of input pins
68 * is determined by reading GPDAT register.
69 */
70static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
71{
72	u32 val;
73	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
74	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
75	u32 out_mask, out_shadow;
76
77	out_mask = in_be32(mm->regs + GPIO_DIR);
78
79	val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
80	out_shadow = mpc8xxx_gc->data & out_mask;
81
82	return (val | out_shadow) & mpc8xxx_gpio2mask(gpio);
83}
84
85static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
86{
87	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
88
89	return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
90}
91
92static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
93{
94	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
95	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
96	unsigned long flags;
97
98	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
99
100	if (val)
101		mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
102	else
103		mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
104
105	out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
106
107	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
108}
109
110static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc,
111				      unsigned long *mask, unsigned long *bits)
112{
113	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
114	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
115	unsigned long flags;
116	int i;
117
118	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
119
120	for (i = 0; i < gc->ngpio; i++) {
121		if (*mask == 0)
122			break;
123		if (__test_and_clear_bit(i, mask)) {
124			if (test_bit(i, bits))
125				mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i);
126			else
127				mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i);
128		}
129	}
130
131	out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
132
133	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
134}
135
136static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
137{
138	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
139	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
140	unsigned long flags;
141
142	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
143
144	clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
145
146	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
147
148	return 0;
149}
150
151static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
152{
153	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
154	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
155	unsigned long flags;
156
157	mpc8xxx_gpio_set(gc, gpio, val);
158
159	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
160
161	setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
162
163	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
164
165	return 0;
166}
167
168static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
169{
170	/* GPIO 28..31 are input only on MPC5121 */
171	if (gpio >= 28)
172		return -EINVAL;
173
174	return mpc8xxx_gpio_dir_out(gc, gpio, val);
175}
176
177static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
178{
179	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
180	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
181
182	if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
183		return irq_create_mapping(mpc8xxx_gc->irq, offset);
184	else
185		return -ENXIO;
186}
187
188static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
189{
190	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
191	struct irq_chip *chip = irq_desc_get_chip(desc);
192	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
193	unsigned int mask;
194
195	mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
196	if (mask)
197		generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
198						     32 - ffs(mask)));
199	if (chip->irq_eoi)
200		chip->irq_eoi(&desc->irq_data);
201}
202
203static void mpc8xxx_irq_unmask(struct irq_data *d)
204{
205	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
206	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
207	unsigned long flags;
208
209	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
210
211	setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
212
213	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
214}
215
216static void mpc8xxx_irq_mask(struct irq_data *d)
217{
218	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
219	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
220	unsigned long flags;
221
222	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
223
224	clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
225
226	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
227}
228
229static void mpc8xxx_irq_ack(struct irq_data *d)
230{
231	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
232	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
233
234	out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
235}
236
237static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
238{
239	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
240	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
241	unsigned long flags;
242
243	switch (flow_type) {
244	case IRQ_TYPE_EDGE_FALLING:
245		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
246		setbits32(mm->regs + GPIO_ICR,
247			  mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
248		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
249		break;
250
251	case IRQ_TYPE_EDGE_BOTH:
252		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
253		clrbits32(mm->regs + GPIO_ICR,
254			  mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
255		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
256		break;
257
258	default:
259		return -EINVAL;
260	}
261
262	return 0;
263}
264
265static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
266{
267	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
268	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
269	unsigned long gpio = irqd_to_hwirq(d);
270	void __iomem *reg;
271	unsigned int shift;
272	unsigned long flags;
273
274	if (gpio < 16) {
275		reg = mm->regs + GPIO_ICR;
276		shift = (15 - gpio) * 2;
277	} else {
278		reg = mm->regs + GPIO_ICR2;
279		shift = (15 - (gpio % 16)) * 2;
280	}
281
282	switch (flow_type) {
283	case IRQ_TYPE_EDGE_FALLING:
284	case IRQ_TYPE_LEVEL_LOW:
285		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
286		clrsetbits_be32(reg, 3 << shift, 2 << shift);
287		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
288		break;
289
290	case IRQ_TYPE_EDGE_RISING:
291	case IRQ_TYPE_LEVEL_HIGH:
292		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
293		clrsetbits_be32(reg, 3 << shift, 1 << shift);
294		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
295		break;
296
297	case IRQ_TYPE_EDGE_BOTH:
298		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
299		clrbits32(reg, 3 << shift);
300		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
301		break;
302
303	default:
304		return -EINVAL;
305	}
306
307	return 0;
308}
309
310static struct irq_chip mpc8xxx_irq_chip = {
311	.name		= "mpc8xxx-gpio",
312	.irq_unmask	= mpc8xxx_irq_unmask,
313	.irq_mask	= mpc8xxx_irq_mask,
314	.irq_ack	= mpc8xxx_irq_ack,
315	.irq_set_type	= mpc8xxx_irq_set_type,
316};
317
318static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
319				irq_hw_number_t hwirq)
320{
321	struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
322
323	if (mpc8xxx_gc->of_dev_id_data)
324		mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
325
326	irq_set_chip_data(irq, h->host_data);
327	irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);
328
329	return 0;
330}
331
332static struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
333	.map	= mpc8xxx_gpio_irq_map,
334	.xlate	= irq_domain_xlate_twocell,
335};
336
337static struct of_device_id mpc8xxx_gpio_ids[] = {
338	{ .compatible = "fsl,mpc8349-gpio", },
339	{ .compatible = "fsl,mpc8572-gpio", },
340	{ .compatible = "fsl,mpc8610-gpio", },
341	{ .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
342	{ .compatible = "fsl,pq3-gpio",     },
343	{ .compatible = "fsl,qoriq-gpio",   },
344	{}
345};
346
347static int mpc8xxx_probe(struct platform_device *pdev)
348{
349	struct device_node *np = pdev->dev.of_node;
350	struct mpc8xxx_gpio_chip *mpc8xxx_gc;
351	struct of_mm_gpio_chip *mm_gc;
352	struct gpio_chip *gc;
353	const struct of_device_id *id;
354	int ret;
355
356	mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
357	if (!mpc8xxx_gc)
358		return -ENOMEM;
359
360	platform_set_drvdata(pdev, mpc8xxx_gc);
361
362	spin_lock_init(&mpc8xxx_gc->lock);
363
364	mm_gc = &mpc8xxx_gc->mm_gc;
365	gc = &mm_gc->gc;
366
367	mm_gc->save_regs = mpc8xxx_gpio_save_regs;
368	gc->ngpio = MPC8XXX_GPIO_PINS;
369	gc->direction_input = mpc8xxx_gpio_dir_in;
370	gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
371		mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
372	gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
373		mpc8572_gpio_get : mpc8xxx_gpio_get;
374	gc->set = mpc8xxx_gpio_set;
375	gc->set_multiple = mpc8xxx_gpio_set_multiple;
376	gc->to_irq = mpc8xxx_gpio_to_irq;
377
378	ret = of_mm_gpiochip_add(np, mm_gc);
379	if (ret)
380		return ret;
381
382	mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
383	if (mpc8xxx_gc->irqn == NO_IRQ)
384		return 0;
385
386	mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
387					&mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
388	if (!mpc8xxx_gc->irq)
389		return 0;
390
391	id = of_match_node(mpc8xxx_gpio_ids, np);
392	if (id)
393		mpc8xxx_gc->of_dev_id_data = id->data;
394
395	/* ack and mask all irqs */
396	out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
397	out_be32(mm_gc->regs + GPIO_IMR, 0);
398
399	irq_set_handler_data(mpc8xxx_gc->irqn, mpc8xxx_gc);
400	irq_set_chained_handler(mpc8xxx_gc->irqn, mpc8xxx_gpio_irq_cascade);
401
402	return 0;
403}
404
405static int mpc8xxx_remove(struct platform_device *pdev)
406{
407	struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
408
409	if (mpc8xxx_gc->irq) {
410		irq_set_handler_data(mpc8xxx_gc->irqn, NULL);
411		irq_set_chained_handler(mpc8xxx_gc->irqn, NULL);
412		irq_domain_remove(mpc8xxx_gc->irq);
413	}
414
415	of_mm_gpiochip_remove(&mpc8xxx_gc->mm_gc);
416
417	return 0;
418}
419
420static struct platform_driver mpc8xxx_plat_driver = {
421	.probe		= mpc8xxx_probe,
422	.remove		= mpc8xxx_remove,
423	.driver		= {
424		.name = "gpio-mpc8xxx",
425		.of_match_table	= mpc8xxx_gpio_ids,
426	},
427};
428
429static int __init mpc8xxx_init(void)
430{
431	return platform_driver_register(&mpc8xxx_plat_driver);
432}
433
434arch_initcall(mpc8xxx_init);
435