1/*
2 *  This program is free software; you can redistribute it and/or modify it
3 *  under the terms of the GNU General Public License version 2 as published
4 *  by the Free Software Foundation.
5 *
6 *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
7 *
8 */
9
10#include <linux/slab.h>
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/types.h>
14#include <linux/of_platform.h>
15#include <linux/mutex.h>
16#include <linux/gpio.h>
17#include <linux/io.h>
18#include <linux/of_gpio.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21
22#include <lantiq_soc.h>
23
24/*
25 * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
26 * peripheral controller used to drive external shift register cascades. At most
27 * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
28 * to drive the 2 LSBs of the cascade automatically.
29 */
30
31/* control register 0 */
32#define XWAY_STP_CON0		0x00
33/* control register 1 */
34#define XWAY_STP_CON1		0x04
35/* data register 0 */
36#define XWAY_STP_CPU0		0x08
37/* data register 1 */
38#define XWAY_STP_CPU1		0x0C
39/* access register */
40#define XWAY_STP_AR		0x10
41
42/* software or hardware update select bit */
43#define XWAY_STP_CON_SWU	BIT(31)
44
45/* automatic update rates */
46#define XWAY_STP_2HZ		0
47#define XWAY_STP_4HZ		BIT(23)
48#define XWAY_STP_8HZ		BIT(24)
49#define XWAY_STP_10HZ		(BIT(24) | BIT(23))
50#define XWAY_STP_SPEED_MASK	(0xf << 23)
51
52/* clock source for automatic update */
53#define XWAY_STP_UPD_FPI	BIT(31)
54#define XWAY_STP_UPD_MASK	(BIT(31) | BIT(30))
55
56/* let the adsl core drive the 2 LSBs */
57#define XWAY_STP_ADSL_SHIFT	24
58#define XWAY_STP_ADSL_MASK	0x3
59
60/* 2 groups of 3 bits can be driven by the phys */
61#define XWAY_STP_PHY_MASK	0x3
62#define XWAY_STP_PHY1_SHIFT	27
63#define XWAY_STP_PHY2_SHIFT	15
64
65/* STP has 3 groups of 8 bits */
66#define XWAY_STP_GROUP0		BIT(0)
67#define XWAY_STP_GROUP1		BIT(1)
68#define XWAY_STP_GROUP2		BIT(2)
69#define XWAY_STP_GROUP_MASK	(0x7)
70
71/* Edge configuration bits */
72#define XWAY_STP_FALLING	BIT(26)
73#define XWAY_STP_EDGE_MASK	BIT(26)
74
75#define xway_stp_r32(m, reg)		__raw_readl(m + reg)
76#define xway_stp_w32(m, val, reg)	__raw_writel(val, m + reg)
77#define xway_stp_w32_mask(m, clear, set, reg) \
78		ltq_w32((ltq_r32(m + reg) & ~(clear)) | (set), \
79		m + reg)
80
81struct xway_stp {
82	struct gpio_chip gc;
83	void __iomem *virt;
84	u32 edge;	/* rising or falling edge triggered shift register */
85	u32 shadow;	/* shadow the shift registers state */
86	u8 groups;	/* we can drive 1-3 groups of 8bit each */
87	u8 dsl;		/* the 2 LSBs can be driven by the dsl core */
88	u8 phy1;	/* 3 bits can be driven by phy1 */
89	u8 phy2;	/* 3 bits can be driven by phy2 */
90	u8 reserved;	/* mask out the hw driven bits in gpio_request */
91};
92
93/**
94 * xway_stp_set() - gpio_chip->set - set gpios.
95 * @gc:     Pointer to gpio_chip device structure.
96 * @gpio:   GPIO signal number.
97 * @val:    Value to be written to specified signal.
98 *
99 * Set the shadow value and call ltq_ebu_apply.
100 */
101static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
102{
103	struct xway_stp *chip =
104		container_of(gc, struct xway_stp, gc);
105
106	if (val)
107		chip->shadow |= BIT(gpio);
108	else
109		chip->shadow &= ~BIT(gpio);
110	xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
111	xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
112}
113
114/**
115 * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
116 * @gc:     Pointer to gpio_chip device structure.
117 * @gpio:   GPIO signal number.
118 * @val:    Value to be written to specified signal.
119 *
120 * Same as xway_stp_set, always returns 0.
121 */
122static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
123{
124	xway_stp_set(gc, gpio, val);
125
126	return 0;
127}
128
129/**
130 * xway_stp_request() - gpio_chip->request
131 * @gc:     Pointer to gpio_chip device structure.
132 * @gpio:   GPIO signal number.
133 *
134 * We mask out the HW driven pins
135 */
136static int xway_stp_request(struct gpio_chip *gc, unsigned gpio)
137{
138	struct xway_stp *chip =
139		container_of(gc, struct xway_stp, gc);
140
141	if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
142		dev_err(gc->dev, "GPIO %d is driven by hardware\n", gpio);
143		return -ENODEV;
144	}
145
146	return 0;
147}
148
149/**
150 * xway_stp_hw_init() - Configure the STP unit and enable the clock gate
151 * @virt: pointer to the remapped register range
152 */
153static int xway_stp_hw_init(struct xway_stp *chip)
154{
155	/* sane defaults */
156	xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
157	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
158	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
159	xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
160	xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);
161
162	/* apply edge trigger settings for the shift register */
163	xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
164				chip->edge, XWAY_STP_CON0);
165
166	/* apply led group settings */
167	xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
168				chip->groups, XWAY_STP_CON1);
169
170	/* tell the hardware which pins are controlled by the dsl modem */
171	xway_stp_w32_mask(chip->virt,
172			XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT,
173			chip->dsl << XWAY_STP_ADSL_SHIFT,
174			XWAY_STP_CON0);
175
176	/* tell the hardware which pins are controlled by the phys */
177	xway_stp_w32_mask(chip->virt,
178			XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT,
179			chip->phy1 << XWAY_STP_PHY1_SHIFT,
180			XWAY_STP_CON0);
181	xway_stp_w32_mask(chip->virt,
182			XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT,
183			chip->phy2 << XWAY_STP_PHY2_SHIFT,
184			XWAY_STP_CON1);
185
186	/* mask out the hw driven bits in gpio_request */
187	chip->reserved = (chip->phy2 << 5) | (chip->phy1 << 2) | chip->dsl;
188
189	/*
190	 * if we have pins that are driven by hw, we need to tell the stp what
191	 * clock to use as a timer.
192	 */
193	if (chip->reserved)
194		xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
195			XWAY_STP_UPD_FPI, XWAY_STP_CON1);
196
197	return 0;
198}
199
200static int xway_stp_probe(struct platform_device *pdev)
201{
202	struct resource *res;
203	const __be32 *shadow, *groups, *dsl, *phy;
204	struct xway_stp *chip;
205	struct clk *clk;
206	int ret = 0;
207
208	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
209	if (!chip)
210		return -ENOMEM;
211
212	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
213	chip->virt = devm_ioremap_resource(&pdev->dev, res);
214	if (IS_ERR(chip->virt))
215		return PTR_ERR(chip->virt);
216
217	chip->gc.dev = &pdev->dev;
218	chip->gc.label = "stp-xway";
219	chip->gc.direction_output = xway_stp_dir_out;
220	chip->gc.set = xway_stp_set;
221	chip->gc.request = xway_stp_request;
222	chip->gc.base = -1;
223	chip->gc.owner = THIS_MODULE;
224
225	/* store the shadow value if one was passed by the devicetree */
226	shadow = of_get_property(pdev->dev.of_node, "lantiq,shadow", NULL);
227	if (shadow)
228		chip->shadow = be32_to_cpu(*shadow);
229
230	/* find out which gpio groups should be enabled */
231	groups = of_get_property(pdev->dev.of_node, "lantiq,groups", NULL);
232	if (groups)
233		chip->groups = be32_to_cpu(*groups) & XWAY_STP_GROUP_MASK;
234	else
235		chip->groups = XWAY_STP_GROUP0;
236	chip->gc.ngpio = fls(chip->groups) * 8;
237
238	/* find out which gpios are controlled by the dsl core */
239	dsl = of_get_property(pdev->dev.of_node, "lantiq,dsl", NULL);
240	if (dsl)
241		chip->dsl = be32_to_cpu(*dsl) & XWAY_STP_ADSL_MASK;
242
243	/* find out which gpios are controlled by the phys */
244	if (of_machine_is_compatible("lantiq,ar9") ||
245			of_machine_is_compatible("lantiq,gr9") ||
246			of_machine_is_compatible("lantiq,vr9")) {
247		phy = of_get_property(pdev->dev.of_node, "lantiq,phy1", NULL);
248		if (phy)
249			chip->phy1 = be32_to_cpu(*phy) & XWAY_STP_PHY_MASK;
250		phy = of_get_property(pdev->dev.of_node, "lantiq,phy2", NULL);
251		if (phy)
252			chip->phy2 = be32_to_cpu(*phy) & XWAY_STP_PHY_MASK;
253	}
254
255	/* check which edge trigger we should use, default to a falling edge */
256	if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))
257		chip->edge = XWAY_STP_FALLING;
258
259	clk = clk_get(&pdev->dev, NULL);
260	if (IS_ERR(clk)) {
261		dev_err(&pdev->dev, "Failed to get clock\n");
262		return PTR_ERR(clk);
263	}
264	clk_enable(clk);
265
266	ret = xway_stp_hw_init(chip);
267	if (!ret)
268		ret = gpiochip_add(&chip->gc);
269
270	if (!ret)
271		dev_info(&pdev->dev, "Init done\n");
272
273	return ret;
274}
275
276static const struct of_device_id xway_stp_match[] = {
277	{ .compatible = "lantiq,gpio-stp-xway" },
278	{},
279};
280MODULE_DEVICE_TABLE(of, xway_stp_match);
281
282static struct platform_driver xway_stp_driver = {
283	.probe = xway_stp_probe,
284	.driver = {
285		.name = "gpio-stp-xway",
286		.of_match_table = xway_stp_match,
287	},
288};
289
290static int __init xway_stp_init(void)
291{
292	return platform_driver_register(&xway_stp_driver);
293}
294
295subsys_initcall(xway_stp_init);
296