1/* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24/** 25 * DOC: Panel Self Refresh (PSR/SRD) 26 * 27 * Since Haswell Display controller supports Panel Self-Refresh on display 28 * panels witch have a remote frame buffer (RFB) implemented according to PSR 29 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 30 * when system is idle but display is on as it eliminates display refresh 31 * request to DDR memory completely as long as the frame buffer for that 32 * display is unchanged. 33 * 34 * Panel Self Refresh must be supported by both Hardware (source) and 35 * Panel (sink). 36 * 37 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 38 * to power down the link and memory controller. For DSI panels the same idea 39 * is called "manual mode". 40 * 41 * The implementation uses the hardware-based PSR support which automatically 42 * enters/exits self-refresh mode. The hardware takes care of sending the 43 * required DP aux message and could even retrain the link (that part isn't 44 * enabled yet though). The hardware also keeps track of any frontbuffer 45 * changes to know when to exit self-refresh mode again. Unfortunately that 46 * part doesn't work too well, hence why the i915 PSR support uses the 47 * software frontbuffer tracking to make sure it doesn't miss a screen 48 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 49 * get called by the frontbuffer tracking code. Note that because of locking 50 * issues the self-refresh re-enable code is done from a work queue, which 51 * must be correctly synchronized/cancelled when shutting down the pipe." 52 */ 53 54#include <drm/drmP.h> 55 56#include "intel_drv.h" 57#include "i915_drv.h" 58 59static bool is_edp_psr(struct intel_dp *intel_dp) 60{ 61 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; 62} 63 64static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe) 65{ 66 struct drm_i915_private *dev_priv = dev->dev_private; 67 uint32_t val; 68 69 val = I915_READ(VLV_PSRSTAT(pipe)) & 70 VLV_EDP_PSR_CURR_STATE_MASK; 71 return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) || 72 (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE); 73} 74 75static void intel_psr_write_vsc(struct intel_dp *intel_dp, 76 struct edp_vsc_psr *vsc_psr) 77{ 78 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 79 struct drm_device *dev = dig_port->base.base.dev; 80 struct drm_i915_private *dev_priv = dev->dev_private; 81 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 82 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder); 83 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config->cpu_transcoder); 84 uint32_t *data = (uint32_t *) vsc_psr; 85 unsigned int i; 86 87 /* As per BSPec (Pipe Video Data Island Packet), we need to disable 88 the video DIP being updated before program video DIP data buffer 89 registers for DIP being updated. */ 90 I915_WRITE(ctl_reg, 0); 91 POSTING_READ(ctl_reg); 92 93 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { 94 if (i < sizeof(struct edp_vsc_psr)) 95 I915_WRITE(data_reg + i, *data++); 96 else 97 I915_WRITE(data_reg + i, 0); 98 } 99 100 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); 101 POSTING_READ(ctl_reg); 102} 103 104static void vlv_psr_setup_vsc(struct intel_dp *intel_dp) 105{ 106 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 107 struct drm_device *dev = intel_dig_port->base.base.dev; 108 struct drm_i915_private *dev_priv = dev->dev_private; 109 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 110 enum pipe pipe = to_intel_crtc(crtc)->pipe; 111 uint32_t val; 112 113 /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */ 114 val = I915_READ(VLV_VSCSDP(pipe)); 115 val &= ~VLV_EDP_PSR_SDP_FREQ_MASK; 116 val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME; 117 I915_WRITE(VLV_VSCSDP(pipe), val); 118} 119 120static void hsw_psr_setup_vsc(struct intel_dp *intel_dp) 121{ 122 struct edp_vsc_psr psr_vsc; 123 124 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 125 memset(&psr_vsc, 0, sizeof(psr_vsc)); 126 psr_vsc.sdp_header.HB0 = 0; 127 psr_vsc.sdp_header.HB1 = 0x7; 128 psr_vsc.sdp_header.HB2 = 0x2; 129 psr_vsc.sdp_header.HB3 = 0x8; 130 intel_psr_write_vsc(intel_dp, &psr_vsc); 131} 132 133static void vlv_psr_enable_sink(struct intel_dp *intel_dp) 134{ 135 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 136 DP_PSR_ENABLE); 137} 138 139static void hsw_psr_enable_sink(struct intel_dp *intel_dp) 140{ 141 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 142 struct drm_device *dev = dig_port->base.base.dev; 143 struct drm_i915_private *dev_priv = dev->dev_private; 144 uint32_t aux_clock_divider; 145 uint32_t aux_data_reg, aux_ctl_reg; 146 int precharge = 0x3; 147 static const uint8_t aux_msg[] = { 148 [0] = DP_AUX_NATIVE_WRITE << 4, 149 [1] = DP_SET_POWER >> 8, 150 [2] = DP_SET_POWER & 0xff, 151 [3] = 1 - 1, 152 [4] = DP_SET_POWER_D0, 153 }; 154 int i; 155 156 BUILD_BUG_ON(sizeof(aux_msg) > 20); 157 158 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 159 160 /* Enable PSR in sink */ 161 if (dev_priv->psr.link_standby) 162 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 163 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); 164 else 165 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 166 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); 167 168 aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ? 169 DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev); 170 aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ? 171 DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev); 172 173 /* Setup AUX registers */ 174 for (i = 0; i < sizeof(aux_msg); i += 4) 175 I915_WRITE(aux_data_reg + i, 176 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); 177 178 if (INTEL_INFO(dev)->gen >= 9) { 179 uint32_t val; 180 181 val = I915_READ(aux_ctl_reg); 182 val &= ~DP_AUX_CH_CTL_TIME_OUT_MASK; 183 val |= DP_AUX_CH_CTL_TIME_OUT_1600us; 184 val &= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK; 185 val |= (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 186 /* Use hardcoded data values for PSR */ 187 val &= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL; 188 I915_WRITE(aux_ctl_reg, val); 189 } else { 190 I915_WRITE(aux_ctl_reg, 191 DP_AUX_CH_CTL_TIME_OUT_400us | 192 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 193 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 194 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 195 } 196} 197 198static void vlv_psr_enable_source(struct intel_dp *intel_dp) 199{ 200 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 201 struct drm_device *dev = dig_port->base.base.dev; 202 struct drm_i915_private *dev_priv = dev->dev_private; 203 struct drm_crtc *crtc = dig_port->base.base.crtc; 204 enum pipe pipe = to_intel_crtc(crtc)->pipe; 205 206 /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */ 207 I915_WRITE(VLV_PSRCTL(pipe), 208 VLV_EDP_PSR_MODE_SW_TIMER | 209 VLV_EDP_PSR_SRC_TRANSMITTER_STATE | 210 VLV_EDP_PSR_ENABLE); 211} 212 213static void vlv_psr_activate(struct intel_dp *intel_dp) 214{ 215 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 216 struct drm_device *dev = dig_port->base.base.dev; 217 struct drm_i915_private *dev_priv = dev->dev_private; 218 struct drm_crtc *crtc = dig_port->base.base.crtc; 219 enum pipe pipe = to_intel_crtc(crtc)->pipe; 220 221 /* Let's do the transition from PSR_state 1 to PSR_state 2 222 * that is PSR transition to active - static frame transmission. 223 * Then Hardware is responsible for the transition to PSR_state 3 224 * that is PSR active - no Remote Frame Buffer (RFB) update. 225 */ 226 I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | 227 VLV_EDP_PSR_ACTIVE_ENTRY); 228} 229 230static void hsw_psr_enable_source(struct intel_dp *intel_dp) 231{ 232 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 233 struct drm_device *dev = dig_port->base.base.dev; 234 struct drm_i915_private *dev_priv = dev->dev_private; 235 uint32_t max_sleep_time = 0x1f; 236 /* Lately it was identified that depending on panel idle frame count 237 * calculated at HW can be off by 1. So let's use what came 238 * from VBT + 1 and at minimum 2 to be on the safe side. 239 */ 240 uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ? 241 dev_priv->vbt.psr.idle_frames + 1 : 2; 242 uint32_t val = 0x0; 243 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 244 245 if (dev_priv->psr.link_standby) { 246 val |= EDP_PSR_LINK_STANDBY; 247 val |= EDP_PSR_TP2_TP3_TIME_0us; 248 val |= EDP_PSR_TP1_TIME_0us; 249 val |= EDP_PSR_SKIP_AUX_EXIT; 250 } else 251 val |= EDP_PSR_LINK_DISABLE; 252 253 I915_WRITE(EDP_PSR_CTL(dev), val | 254 (IS_BROADWELL(dev) ? 0 : link_entry_time) | 255 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | 256 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | 257 EDP_PSR_ENABLE); 258} 259 260static bool intel_psr_match_conditions(struct intel_dp *intel_dp) 261{ 262 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 263 struct drm_device *dev = dig_port->base.base.dev; 264 struct drm_i915_private *dev_priv = dev->dev_private; 265 struct drm_crtc *crtc = dig_port->base.base.crtc; 266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 267 268 lockdep_assert_held(&dev_priv->psr.lock); 269 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 270 WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); 271 272 dev_priv->psr.source_ok = false; 273 274 if (IS_HASWELL(dev) && dig_port->port != PORT_A) { 275 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); 276 return false; 277 } 278 279 if (!i915.enable_psr) { 280 DRM_DEBUG_KMS("PSR disable by flag\n"); 281 return false; 282 } 283 284 if (IS_HASWELL(dev) && 285 I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) & 286 S3D_ENABLE) { 287 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 288 return false; 289 } 290 291 if (IS_HASWELL(dev) && 292 intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 293 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 294 return false; 295 } 296 297 dev_priv->psr.source_ok = true; 298 return true; 299} 300 301static void intel_psr_activate(struct intel_dp *intel_dp) 302{ 303 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 304 struct drm_device *dev = intel_dig_port->base.base.dev; 305 struct drm_i915_private *dev_priv = dev->dev_private; 306 307 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); 308 WARN_ON(dev_priv->psr.active); 309 lockdep_assert_held(&dev_priv->psr.lock); 310 311 /* Enable/Re-enable PSR on the host */ 312 if (HAS_DDI(dev)) 313 /* On HSW+ after we enable PSR on source it will activate it 314 * as soon as it match configure idle_frame count. So 315 * we just actually enable it here on activation time. 316 */ 317 hsw_psr_enable_source(intel_dp); 318 else 319 vlv_psr_activate(intel_dp); 320 321 dev_priv->psr.active = true; 322} 323 324/** 325 * intel_psr_enable - Enable PSR 326 * @intel_dp: Intel DP 327 * 328 * This function can only be called after the pipe is fully trained and enabled. 329 */ 330void intel_psr_enable(struct intel_dp *intel_dp) 331{ 332 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 333 struct drm_device *dev = intel_dig_port->base.base.dev; 334 struct drm_i915_private *dev_priv = dev->dev_private; 335 336 if (!HAS_PSR(dev)) { 337 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 338 return; 339 } 340 341 if (!is_edp_psr(intel_dp)) { 342 DRM_DEBUG_KMS("PSR not supported by this panel\n"); 343 return; 344 } 345 346 mutex_lock(&dev_priv->psr.lock); 347 if (dev_priv->psr.enabled) { 348 DRM_DEBUG_KMS("PSR already in use\n"); 349 goto unlock; 350 } 351 352 if (!intel_psr_match_conditions(intel_dp)) 353 goto unlock; 354 355 /* First we check VBT, but we must respect sink and source 356 * known restrictions */ 357 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; 358 if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) || 359 (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)) 360 dev_priv->psr.link_standby = true; 361 362 dev_priv->psr.busy_frontbuffer_bits = 0; 363 364 if (HAS_DDI(dev)) { 365 hsw_psr_setup_vsc(intel_dp); 366 367 /* Avoid continuous PSR exit by masking memup and hpd */ 368 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | 369 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 370 371 /* Enable PSR on the panel */ 372 hsw_psr_enable_sink(intel_dp); 373 374 if (INTEL_INFO(dev)->gen >= 9) 375 intel_psr_activate(intel_dp); 376 } else { 377 vlv_psr_setup_vsc(intel_dp); 378 379 /* Enable PSR on the panel */ 380 vlv_psr_enable_sink(intel_dp); 381 382 /* On HSW+ enable_source also means go to PSR entry/active 383 * state as soon as idle_frame achieved and here would be 384 * to soon. However on VLV enable_source just enable PSR 385 * but let it on inactive state. So we might do this prior 386 * to active transition, i.e. here. 387 */ 388 vlv_psr_enable_source(intel_dp); 389 } 390 391 dev_priv->psr.enabled = intel_dp; 392unlock: 393 mutex_unlock(&dev_priv->psr.lock); 394} 395 396static void vlv_psr_disable(struct intel_dp *intel_dp) 397{ 398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 399 struct drm_device *dev = intel_dig_port->base.base.dev; 400 struct drm_i915_private *dev_priv = dev->dev_private; 401 struct intel_crtc *intel_crtc = 402 to_intel_crtc(intel_dig_port->base.base.crtc); 403 uint32_t val; 404 405 if (dev_priv->psr.active) { 406 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */ 407 if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) & 408 VLV_EDP_PSR_IN_TRANS) == 0, 1)) 409 WARN(1, "PSR transition took longer than expected\n"); 410 411 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe)); 412 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; 413 val &= ~VLV_EDP_PSR_ENABLE; 414 val &= ~VLV_EDP_PSR_MODE_MASK; 415 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val); 416 417 dev_priv->psr.active = false; 418 } else { 419 WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe)); 420 } 421} 422 423static void hsw_psr_disable(struct intel_dp *intel_dp) 424{ 425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 426 struct drm_device *dev = intel_dig_port->base.base.dev; 427 struct drm_i915_private *dev_priv = dev->dev_private; 428 429 if (dev_priv->psr.active) { 430 I915_WRITE(EDP_PSR_CTL(dev), 431 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); 432 433 /* Wait till PSR is idle */ 434 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & 435 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) 436 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 437 438 dev_priv->psr.active = false; 439 } else { 440 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); 441 } 442} 443 444/** 445 * intel_psr_disable - Disable PSR 446 * @intel_dp: Intel DP 447 * 448 * This function needs to be called before disabling pipe. 449 */ 450void intel_psr_disable(struct intel_dp *intel_dp) 451{ 452 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 453 struct drm_device *dev = intel_dig_port->base.base.dev; 454 struct drm_i915_private *dev_priv = dev->dev_private; 455 456 mutex_lock(&dev_priv->psr.lock); 457 if (!dev_priv->psr.enabled) { 458 mutex_unlock(&dev_priv->psr.lock); 459 return; 460 } 461 462 if (HAS_DDI(dev)) 463 hsw_psr_disable(intel_dp); 464 else 465 vlv_psr_disable(intel_dp); 466 467 dev_priv->psr.enabled = NULL; 468 mutex_unlock(&dev_priv->psr.lock); 469 470 cancel_delayed_work_sync(&dev_priv->psr.work); 471} 472 473static void intel_psr_work(struct work_struct *work) 474{ 475 struct drm_i915_private *dev_priv = 476 container_of(work, typeof(*dev_priv), psr.work.work); 477 struct intel_dp *intel_dp = dev_priv->psr.enabled; 478 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 479 enum pipe pipe = to_intel_crtc(crtc)->pipe; 480 481 /* We have to make sure PSR is ready for re-enable 482 * otherwise it keeps disabled until next full enable/disable cycle. 483 * PSR might take some time to get fully disabled 484 * and be ready for re-enable. 485 */ 486 if (HAS_DDI(dev_priv->dev)) { 487 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) & 488 EDP_PSR_STATUS_STATE_MASK) == 0, 50)) { 489 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); 490 return; 491 } 492 } else { 493 if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) & 494 VLV_EDP_PSR_IN_TRANS) == 0, 1)) { 495 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); 496 return; 497 } 498 } 499 mutex_lock(&dev_priv->psr.lock); 500 intel_dp = dev_priv->psr.enabled; 501 502 if (!intel_dp) 503 goto unlock; 504 505 /* 506 * The delayed work can race with an invalidate hence we need to 507 * recheck. Since psr_flush first clears this and then reschedules we 508 * won't ever miss a flush when bailing out here. 509 */ 510 if (dev_priv->psr.busy_frontbuffer_bits) 511 goto unlock; 512 513 intel_psr_activate(intel_dp); 514unlock: 515 mutex_unlock(&dev_priv->psr.lock); 516} 517 518static void intel_psr_exit(struct drm_device *dev) 519{ 520 struct drm_i915_private *dev_priv = dev->dev_private; 521 struct intel_dp *intel_dp = dev_priv->psr.enabled; 522 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 523 enum pipe pipe = to_intel_crtc(crtc)->pipe; 524 u32 val; 525 526 if (!dev_priv->psr.active) 527 return; 528 529 if (HAS_DDI(dev)) { 530 val = I915_READ(EDP_PSR_CTL(dev)); 531 532 WARN_ON(!(val & EDP_PSR_ENABLE)); 533 534 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); 535 } else { 536 val = I915_READ(VLV_PSRCTL(pipe)); 537 538 /* Here we do the transition from PSR_state 3 to PSR_state 5 539 * directly once PSR State 4 that is active with single frame 540 * update can be skipped. PSR_state 5 that is PSR exit then 541 * Hardware is responsible to transition back to PSR_state 1 542 * that is PSR inactive. Same state after 543 * vlv_edp_psr_enable_source. 544 */ 545 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; 546 I915_WRITE(VLV_PSRCTL(pipe), val); 547 548 /* Send AUX wake up - Spec says after transitioning to PSR 549 * active we have to send AUX wake up by writing 01h in DPCD 550 * 600h of sink device. 551 * XXX: This might slow down the transition, but without this 552 * HW doesn't complete the transition to PSR_state 1 and we 553 * never get the screen updated. 554 */ 555 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 556 DP_SET_POWER_D0); 557 } 558 559 dev_priv->psr.active = false; 560} 561 562/** 563 * intel_psr_invalidate - Invalidade PSR 564 * @dev: DRM device 565 * @frontbuffer_bits: frontbuffer plane tracking bits 566 * 567 * Since the hardware frontbuffer tracking has gaps we need to integrate 568 * with the software frontbuffer tracking. This function gets called every 569 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 570 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 571 * 572 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 573 */ 574void intel_psr_invalidate(struct drm_device *dev, 575 unsigned frontbuffer_bits) 576{ 577 struct drm_i915_private *dev_priv = dev->dev_private; 578 struct drm_crtc *crtc; 579 enum pipe pipe; 580 581 mutex_lock(&dev_priv->psr.lock); 582 if (!dev_priv->psr.enabled) { 583 mutex_unlock(&dev_priv->psr.lock); 584 return; 585 } 586 587 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; 588 pipe = to_intel_crtc(crtc)->pipe; 589 590 intel_psr_exit(dev); 591 592 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 593 594 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; 595 mutex_unlock(&dev_priv->psr.lock); 596} 597 598/** 599 * intel_psr_flush - Flush PSR 600 * @dev: DRM device 601 * @frontbuffer_bits: frontbuffer plane tracking bits 602 * 603 * Since the hardware frontbuffer tracking has gaps we need to integrate 604 * with the software frontbuffer tracking. This function gets called every 605 * time frontbuffer rendering has completed and flushed out to memory. PSR 606 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 607 * 608 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 609 */ 610void intel_psr_flush(struct drm_device *dev, 611 unsigned frontbuffer_bits) 612{ 613 struct drm_i915_private *dev_priv = dev->dev_private; 614 struct drm_crtc *crtc; 615 enum pipe pipe; 616 617 mutex_lock(&dev_priv->psr.lock); 618 if (!dev_priv->psr.enabled) { 619 mutex_unlock(&dev_priv->psr.lock); 620 return; 621 } 622 623 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; 624 pipe = to_intel_crtc(crtc)->pipe; 625 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; 626 627 /* 628 * On Haswell sprite plane updates don't result in a psr invalidating 629 * signal in the hardware. Which means we need to manually fake this in 630 * software for all flushes, not just when we've seen a preceding 631 * invalidation through frontbuffer rendering. 632 */ 633 if (IS_HASWELL(dev) && 634 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe))) 635 intel_psr_exit(dev); 636 637 /* 638 * On Valleyview and Cherryview we don't use hardware tracking so 639 * any plane updates or cursor moves don't result in a PSR 640 * invalidating. Which means we need to manually fake this in 641 * software for all flushes, not just when we've seen a preceding 642 * invalidation through frontbuffer rendering. */ 643 if (!HAS_DDI(dev)) 644 intel_psr_exit(dev); 645 646 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) 647 schedule_delayed_work(&dev_priv->psr.work, 648 msecs_to_jiffies(100)); 649 mutex_unlock(&dev_priv->psr.lock); 650} 651 652/** 653 * intel_psr_init - Init basic PSR work and mutex. 654 * @dev: DRM device 655 * 656 * This function is called only once at driver load to initialize basic 657 * PSR stuff. 658 */ 659void intel_psr_init(struct drm_device *dev) 660{ 661 struct drm_i915_private *dev_priv = dev->dev_private; 662 663 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work); 664 mutex_init(&dev_priv->psr.lock); 665} 666