1/* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/delay.h> 31#include <linux/export.h> 32#include <drm/drmP.h> 33#include <drm/drm_atomic_helper.h> 34#include <drm/drm_crtc.h> 35#include <drm/drm_edid.h> 36#include "intel_drv.h" 37#include <drm/i915_drm.h> 38#include "i915_drv.h" 39#include "intel_sdvo_regs.h" 40 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 45 46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 47 SDVO_TV_MASK) 48 49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 54 55 56static const char *tv_format_names[] = { 57 "NTSC_M" , "NTSC_J" , "NTSC_443", 58 "PAL_B" , "PAL_D" , "PAL_G" , 59 "PAL_H" , "PAL_I" , "PAL_M" , 60 "PAL_N" , "PAL_NC" , "PAL_60" , 61 "SECAM_B" , "SECAM_D" , "SECAM_G" , 62 "SECAM_K" , "SECAM_K1", "SECAM_L" , 63 "SECAM_60" 64}; 65 66#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) 67 68struct intel_sdvo { 69 struct intel_encoder base; 70 71 struct i2c_adapter *i2c; 72 u8 slave_addr; 73 74 struct i2c_adapter ddc; 75 76 /* Register for the SDVO device: SDVOB or SDVOC */ 77 uint32_t sdvo_reg; 78 79 /* Active outputs controlled by this SDVO output */ 80 uint16_t controlled_output; 81 82 /* 83 * Capabilities of the SDVO device returned by 84 * intel_sdvo_get_capabilities() 85 */ 86 struct intel_sdvo_caps caps; 87 88 /* Pixel clock limitations reported by the SDVO device, in kHz */ 89 int pixel_clock_min, pixel_clock_max; 90 91 /* 92 * For multiple function SDVO device, 93 * this is for current attached outputs. 94 */ 95 uint16_t attached_output; 96 97 /* 98 * Hotplug activation bits for this device 99 */ 100 uint16_t hotplug_active; 101 102 /** 103 * This is used to select the color range of RBG outputs in HDMI mode. 104 * It is only valid when using TMDS encoding and 8 bit per color mode. 105 */ 106 uint32_t color_range; 107 bool color_range_auto; 108 109 /** 110 * This is set if we're going to treat the device as TV-out. 111 * 112 * While we have these nice friendly flags for output types that ought 113 * to decide this for us, the S-Video output on our HDMI+S-Video card 114 * shows up as RGB1 (VGA). 115 */ 116 bool is_tv; 117 118 /* On different gens SDVOB is at different places. */ 119 bool is_sdvob; 120 121 /* This is for current tv format name */ 122 int tv_format_index; 123 124 /** 125 * This is set if we treat the device as HDMI, instead of DVI. 126 */ 127 bool is_hdmi; 128 bool has_hdmi_monitor; 129 bool has_hdmi_audio; 130 bool rgb_quant_range_selectable; 131 132 /** 133 * This is set if we detect output of sdvo device as LVDS and 134 * have a valid fixed mode to use with the panel. 135 */ 136 bool is_lvds; 137 138 /** 139 * This is sdvo fixed pannel mode pointer 140 */ 141 struct drm_display_mode *sdvo_lvds_fixed_mode; 142 143 /* DDC bus used by this SDVO encoder */ 144 uint8_t ddc_bus; 145 146 /* 147 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 148 */ 149 uint8_t dtd_sdvo_flags; 150}; 151 152struct intel_sdvo_connector { 153 struct intel_connector base; 154 155 /* Mark the type of connector */ 156 uint16_t output_flag; 157 158 enum hdmi_force_audio force_audio; 159 160 /* This contains all current supported TV format */ 161 u8 tv_format_supported[TV_FORMAT_NUM]; 162 int format_supported_num; 163 struct drm_property *tv_format; 164 165 /* add the property for the SDVO-TV */ 166 struct drm_property *left; 167 struct drm_property *right; 168 struct drm_property *top; 169 struct drm_property *bottom; 170 struct drm_property *hpos; 171 struct drm_property *vpos; 172 struct drm_property *contrast; 173 struct drm_property *saturation; 174 struct drm_property *hue; 175 struct drm_property *sharpness; 176 struct drm_property *flicker_filter; 177 struct drm_property *flicker_filter_adaptive; 178 struct drm_property *flicker_filter_2d; 179 struct drm_property *tv_chroma_filter; 180 struct drm_property *tv_luma_filter; 181 struct drm_property *dot_crawl; 182 183 /* add the property for the SDVO-TV/LVDS */ 184 struct drm_property *brightness; 185 186 /* Add variable to record current setting for the above property */ 187 u32 left_margin, right_margin, top_margin, bottom_margin; 188 189 /* this is to get the range of margin.*/ 190 u32 max_hscan, max_vscan; 191 u32 max_hpos, cur_hpos; 192 u32 max_vpos, cur_vpos; 193 u32 cur_brightness, max_brightness; 194 u32 cur_contrast, max_contrast; 195 u32 cur_saturation, max_saturation; 196 u32 cur_hue, max_hue; 197 u32 cur_sharpness, max_sharpness; 198 u32 cur_flicker_filter, max_flicker_filter; 199 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; 200 u32 cur_flicker_filter_2d, max_flicker_filter_2d; 201 u32 cur_tv_chroma_filter, max_tv_chroma_filter; 202 u32 cur_tv_luma_filter, max_tv_luma_filter; 203 u32 cur_dot_crawl, max_dot_crawl; 204}; 205 206static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 207{ 208 return container_of(encoder, struct intel_sdvo, base); 209} 210 211static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) 212{ 213 return to_sdvo(intel_attached_encoder(connector)); 214} 215 216static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) 217{ 218 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); 219} 220 221static bool 222intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); 223static bool 224intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 225 struct intel_sdvo_connector *intel_sdvo_connector, 226 int type); 227static bool 228intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 229 struct intel_sdvo_connector *intel_sdvo_connector); 230 231/** 232 * Writes the SDVOB or SDVOC with the given value, but always writes both 233 * SDVOB and SDVOC to work around apparent hardware issues (according to 234 * comments in the BIOS). 235 */ 236static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 237{ 238 struct drm_device *dev = intel_sdvo->base.base.dev; 239 struct drm_i915_private *dev_priv = dev->dev_private; 240 u32 bval = val, cval = val; 241 int i; 242 243 if (intel_sdvo->sdvo_reg == PCH_SDVOB) { 244 I915_WRITE(intel_sdvo->sdvo_reg, val); 245 I915_READ(intel_sdvo->sdvo_reg); 246 return; 247 } 248 249 if (intel_sdvo->sdvo_reg == GEN3_SDVOB) 250 cval = I915_READ(GEN3_SDVOC); 251 else 252 bval = I915_READ(GEN3_SDVOB); 253 254 /* 255 * Write the registers twice for luck. Sometimes, 256 * writing them only once doesn't appear to 'stick'. 257 * The BIOS does this too. Yay, magic 258 */ 259 for (i = 0; i < 2; i++) 260 { 261 I915_WRITE(GEN3_SDVOB, bval); 262 I915_READ(GEN3_SDVOB); 263 I915_WRITE(GEN3_SDVOC, cval); 264 I915_READ(GEN3_SDVOC); 265 } 266} 267 268static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 269{ 270 struct i2c_msg msgs[] = { 271 { 272 .addr = intel_sdvo->slave_addr, 273 .flags = 0, 274 .len = 1, 275 .buf = &addr, 276 }, 277 { 278 .addr = intel_sdvo->slave_addr, 279 .flags = I2C_M_RD, 280 .len = 1, 281 .buf = ch, 282 } 283 }; 284 int ret; 285 286 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 287 return true; 288 289 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 290 return false; 291} 292 293#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} 294/** Mapping of command numbers to names, for debug output */ 295static const struct _sdvo_cmd_name { 296 u8 cmd; 297 const char *name; 298} sdvo_cmd_names[] = { 299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), 302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), 303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), 304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), 305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), 306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), 307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), 308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), 309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), 310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), 311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), 312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), 313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), 314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), 315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), 318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), 322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), 324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), 325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), 329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), 330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), 331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), 335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 342 343 /* Add the op code for SDVO enhancements */ 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), 345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), 347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), 353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), 354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), 355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), 356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), 357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), 358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), 359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), 360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), 361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), 362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), 363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), 365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), 369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), 371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), 372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), 373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), 374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), 375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), 376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), 377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), 378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), 379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), 380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), 381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), 382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), 383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), 384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), 385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), 386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), 387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), 388 389 /* HDMI op code */ 390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), 392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), 393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), 394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), 395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), 396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), 397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), 398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), 399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), 400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), 401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), 402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), 403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), 404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), 405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), 406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), 407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), 408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), 409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 410}; 411 412#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") 413 414static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 415 const void *args, int args_len) 416{ 417 int i, pos = 0; 418#define BUF_LEN 256 419 char buffer[BUF_LEN]; 420 421#define BUF_PRINT(args...) \ 422 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 423 424 425 for (i = 0; i < args_len; i++) { 426 BUF_PRINT("%02X ", ((u8 *)args)[i]); 427 } 428 for (; i < 8; i++) { 429 BUF_PRINT(" "); 430 } 431 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 432 if (cmd == sdvo_cmd_names[i].cmd) { 433 BUF_PRINT("(%s)", sdvo_cmd_names[i].name); 434 break; 435 } 436 } 437 if (i == ARRAY_SIZE(sdvo_cmd_names)) { 438 BUF_PRINT("(%02X)", cmd); 439 } 440 BUG_ON(pos >= BUF_LEN - 1); 441#undef BUF_PRINT 442#undef BUF_LEN 443 444 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 445} 446 447static const char *cmd_status_names[] = { 448 "Power on", 449 "Success", 450 "Not supported", 451 "Invalid arg", 452 "Pending", 453 "Target not specified", 454 "Scaling not supported" 455}; 456 457static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 458 const void *args, int args_len) 459{ 460 u8 *buf, status; 461 struct i2c_msg *msgs; 462 int i, ret = true; 463 464 /* Would be simpler to allocate both in one go ? */ 465 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 466 if (!buf) 467 return false; 468 469 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 470 if (!msgs) { 471 kfree(buf); 472 return false; 473 } 474 475 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 476 477 for (i = 0; i < args_len; i++) { 478 msgs[i].addr = intel_sdvo->slave_addr; 479 msgs[i].flags = 0; 480 msgs[i].len = 2; 481 msgs[i].buf = buf + 2 *i; 482 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 483 buf[2*i + 1] = ((u8*)args)[i]; 484 } 485 msgs[i].addr = intel_sdvo->slave_addr; 486 msgs[i].flags = 0; 487 msgs[i].len = 2; 488 msgs[i].buf = buf + 2*i; 489 buf[2*i + 0] = SDVO_I2C_OPCODE; 490 buf[2*i + 1] = cmd; 491 492 /* the following two are to read the response */ 493 status = SDVO_I2C_CMD_STATUS; 494 msgs[i+1].addr = intel_sdvo->slave_addr; 495 msgs[i+1].flags = 0; 496 msgs[i+1].len = 1; 497 msgs[i+1].buf = &status; 498 499 msgs[i+2].addr = intel_sdvo->slave_addr; 500 msgs[i+2].flags = I2C_M_RD; 501 msgs[i+2].len = 1; 502 msgs[i+2].buf = &status; 503 504 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 505 if (ret < 0) { 506 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 507 ret = false; 508 goto out; 509 } 510 if (ret != i+3) { 511 /* failure in I2C transfer */ 512 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 513 ret = false; 514 } 515 516out: 517 kfree(msgs); 518 kfree(buf); 519 return ret; 520} 521 522static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 523 void *response, int response_len) 524{ 525 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 526 u8 status; 527 int i, pos = 0; 528#define BUF_LEN 256 529 char buffer[BUF_LEN]; 530 531 532 /* 533 * The documentation states that all commands will be 534 * processed within 15µs, and that we need only poll 535 * the status byte a maximum of 3 times in order for the 536 * command to be complete. 537 * 538 * Check 5 times in case the hardware failed to read the docs. 539 * 540 * Also beware that the first response by many devices is to 541 * reply PENDING and stall for time. TVs are notorious for 542 * requiring longer than specified to complete their replies. 543 * Originally (in the DDX long ago), the delay was only ever 15ms 544 * with an additional delay of 30ms applied for TVs added later after 545 * many experiments. To accommodate both sets of delays, we do a 546 * sequence of slow checks if the device is falling behind and fails 547 * to reply within 5*15µs. 548 */ 549 if (!intel_sdvo_read_byte(intel_sdvo, 550 SDVO_I2C_CMD_STATUS, 551 &status)) 552 goto log_fail; 553 554 while ((status == SDVO_CMD_STATUS_PENDING || 555 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 556 if (retry < 10) 557 msleep(15); 558 else 559 udelay(15); 560 561 if (!intel_sdvo_read_byte(intel_sdvo, 562 SDVO_I2C_CMD_STATUS, 563 &status)) 564 goto log_fail; 565 } 566 567#define BUF_PRINT(args...) \ 568 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 569 570 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 571 BUF_PRINT("(%s)", cmd_status_names[status]); 572 else 573 BUF_PRINT("(??? %d)", status); 574 575 if (status != SDVO_CMD_STATUS_SUCCESS) 576 goto log_fail; 577 578 /* Read the command response */ 579 for (i = 0; i < response_len; i++) { 580 if (!intel_sdvo_read_byte(intel_sdvo, 581 SDVO_I2C_RETURN_0 + i, 582 &((u8 *)response)[i])) 583 goto log_fail; 584 BUF_PRINT(" %02X", ((u8 *)response)[i]); 585 } 586 BUG_ON(pos >= BUF_LEN - 1); 587#undef BUF_PRINT 588#undef BUF_LEN 589 590 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 591 return true; 592 593log_fail: 594 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo)); 595 return false; 596} 597 598static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) 599{ 600 if (mode->clock >= 100000) 601 return 1; 602 else if (mode->clock >= 50000) 603 return 2; 604 else 605 return 4; 606} 607 608static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 609 u8 ddc_bus) 610{ 611 /* This must be the immediately preceding write before the i2c xfer */ 612 return intel_sdvo_write_cmd(intel_sdvo, 613 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 614 &ddc_bus, 1); 615} 616 617static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 618{ 619 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 620 return false; 621 622 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 623} 624 625static bool 626intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 627{ 628 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 629 return false; 630 631 return intel_sdvo_read_response(intel_sdvo, value, len); 632} 633 634static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 635{ 636 struct intel_sdvo_set_target_input_args targets = {0}; 637 return intel_sdvo_set_value(intel_sdvo, 638 SDVO_CMD_SET_TARGET_INPUT, 639 &targets, sizeof(targets)); 640} 641 642/** 643 * Return whether each input is trained. 644 * 645 * This function is making an assumption about the layout of the response, 646 * which should be checked against the docs. 647 */ 648static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 649{ 650 struct intel_sdvo_get_trained_inputs_response response; 651 652 BUILD_BUG_ON(sizeof(response) != 1); 653 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 654 &response, sizeof(response))) 655 return false; 656 657 *input_1 = response.input0_trained; 658 *input_2 = response.input1_trained; 659 return true; 660} 661 662static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 663 u16 outputs) 664{ 665 return intel_sdvo_set_value(intel_sdvo, 666 SDVO_CMD_SET_ACTIVE_OUTPUTS, 667 &outputs, sizeof(outputs)); 668} 669 670static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 671 u16 *outputs) 672{ 673 return intel_sdvo_get_value(intel_sdvo, 674 SDVO_CMD_GET_ACTIVE_OUTPUTS, 675 outputs, sizeof(*outputs)); 676} 677 678static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 679 int mode) 680{ 681 u8 state = SDVO_ENCODER_STATE_ON; 682 683 switch (mode) { 684 case DRM_MODE_DPMS_ON: 685 state = SDVO_ENCODER_STATE_ON; 686 break; 687 case DRM_MODE_DPMS_STANDBY: 688 state = SDVO_ENCODER_STATE_STANDBY; 689 break; 690 case DRM_MODE_DPMS_SUSPEND: 691 state = SDVO_ENCODER_STATE_SUSPEND; 692 break; 693 case DRM_MODE_DPMS_OFF: 694 state = SDVO_ENCODER_STATE_OFF; 695 break; 696 } 697 698 return intel_sdvo_set_value(intel_sdvo, 699 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 700} 701 702static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 703 int *clock_min, 704 int *clock_max) 705{ 706 struct intel_sdvo_pixel_clock_range clocks; 707 708 BUILD_BUG_ON(sizeof(clocks) != 4); 709 if (!intel_sdvo_get_value(intel_sdvo, 710 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 711 &clocks, sizeof(clocks))) 712 return false; 713 714 /* Convert the values from units of 10 kHz to kHz. */ 715 *clock_min = clocks.min * 10; 716 *clock_max = clocks.max * 10; 717 return true; 718} 719 720static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 721 u16 outputs) 722{ 723 return intel_sdvo_set_value(intel_sdvo, 724 SDVO_CMD_SET_TARGET_OUTPUT, 725 &outputs, sizeof(outputs)); 726} 727 728static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 729 struct intel_sdvo_dtd *dtd) 730{ 731 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 732 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 733} 734 735static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 736 struct intel_sdvo_dtd *dtd) 737{ 738 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 739 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 740} 741 742static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 743 struct intel_sdvo_dtd *dtd) 744{ 745 return intel_sdvo_set_timing(intel_sdvo, 746 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 747} 748 749static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 750 struct intel_sdvo_dtd *dtd) 751{ 752 return intel_sdvo_set_timing(intel_sdvo, 753 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 754} 755 756static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 757 struct intel_sdvo_dtd *dtd) 758{ 759 return intel_sdvo_get_timing(intel_sdvo, 760 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 761} 762 763static bool 764intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 765 uint16_t clock, 766 uint16_t width, 767 uint16_t height) 768{ 769 struct intel_sdvo_preferred_input_timing_args args; 770 771 memset(&args, 0, sizeof(args)); 772 args.clock = clock; 773 args.width = width; 774 args.height = height; 775 args.interlace = 0; 776 777 if (intel_sdvo->is_lvds && 778 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || 779 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) 780 args.scaled = 1; 781 782 return intel_sdvo_set_value(intel_sdvo, 783 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 784 &args, sizeof(args)); 785} 786 787static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 788 struct intel_sdvo_dtd *dtd) 789{ 790 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 791 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 792 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 793 &dtd->part1, sizeof(dtd->part1)) && 794 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 795 &dtd->part2, sizeof(dtd->part2)); 796} 797 798static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 799{ 800 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 801} 802 803static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 804 const struct drm_display_mode *mode) 805{ 806 uint16_t width, height; 807 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; 808 uint16_t h_sync_offset, v_sync_offset; 809 int mode_clock; 810 811 memset(dtd, 0, sizeof(*dtd)); 812 813 width = mode->hdisplay; 814 height = mode->vdisplay; 815 816 /* do some mode translations */ 817 h_blank_len = mode->htotal - mode->hdisplay; 818 h_sync_len = mode->hsync_end - mode->hsync_start; 819 820 v_blank_len = mode->vtotal - mode->vdisplay; 821 v_sync_len = mode->vsync_end - mode->vsync_start; 822 823 h_sync_offset = mode->hsync_start - mode->hdisplay; 824 v_sync_offset = mode->vsync_start - mode->vdisplay; 825 826 mode_clock = mode->clock; 827 mode_clock /= 10; 828 dtd->part1.clock = mode_clock; 829 830 dtd->part1.h_active = width & 0xff; 831 dtd->part1.h_blank = h_blank_len & 0xff; 832 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 833 ((h_blank_len >> 8) & 0xf); 834 dtd->part1.v_active = height & 0xff; 835 dtd->part1.v_blank = v_blank_len & 0xff; 836 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 837 ((v_blank_len >> 8) & 0xf); 838 839 dtd->part2.h_sync_off = h_sync_offset & 0xff; 840 dtd->part2.h_sync_width = h_sync_len & 0xff; 841 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 842 (v_sync_len & 0xf); 843 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 844 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 845 ((v_sync_len & 0x30) >> 4); 846 847 dtd->part2.dtd_flags = 0x18; 848 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 849 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 850 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 851 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 852 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 853 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 854 855 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 856} 857 858static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 859 const struct intel_sdvo_dtd *dtd) 860{ 861 struct drm_display_mode mode = {}; 862 863 mode.hdisplay = dtd->part1.h_active; 864 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 865 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 866 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 867 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 868 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 869 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 870 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 871 872 mode.vdisplay = dtd->part1.v_active; 873 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 874 mode.vsync_start = mode.vdisplay; 875 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 876 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 877 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 878 mode.vsync_end = mode.vsync_start + 879 (dtd->part2.v_sync_off_width & 0xf); 880 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 881 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 882 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 883 884 mode.clock = dtd->part1.clock * 10; 885 886 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 887 mode.flags |= DRM_MODE_FLAG_INTERLACE; 888 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 889 mode.flags |= DRM_MODE_FLAG_PHSYNC; 890 else 891 mode.flags |= DRM_MODE_FLAG_NHSYNC; 892 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 893 mode.flags |= DRM_MODE_FLAG_PVSYNC; 894 else 895 mode.flags |= DRM_MODE_FLAG_NVSYNC; 896 897 drm_mode_set_crtcinfo(&mode, 0); 898 899 drm_mode_copy(pmode, &mode); 900} 901 902static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 903{ 904 struct intel_sdvo_encode encode; 905 906 BUILD_BUG_ON(sizeof(encode) != 2); 907 return intel_sdvo_get_value(intel_sdvo, 908 SDVO_CMD_GET_SUPP_ENCODE, 909 &encode, sizeof(encode)); 910} 911 912static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 913 uint8_t mode) 914{ 915 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 916} 917 918static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 919 uint8_t mode) 920{ 921 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 922} 923 924#if 0 925static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 926{ 927 int i, j; 928 uint8_t set_buf_index[2]; 929 uint8_t av_split; 930 uint8_t buf_size; 931 uint8_t buf[48]; 932 uint8_t *pos; 933 934 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 935 936 for (i = 0; i <= av_split; i++) { 937 set_buf_index[0] = i; set_buf_index[1] = 0; 938 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 939 set_buf_index, 2); 940 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 941 intel_sdvo_read_response(encoder, &buf_size, 1); 942 943 pos = buf; 944 for (j = 0; j <= buf_size; j += 8) { 945 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 946 NULL, 0); 947 intel_sdvo_read_response(encoder, pos, 8); 948 pos += 8; 949 } 950 } 951} 952#endif 953 954static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 955 unsigned if_index, uint8_t tx_rate, 956 const uint8_t *data, unsigned length) 957{ 958 uint8_t set_buf_index[2] = { if_index, 0 }; 959 uint8_t hbuf_size, tmp[8]; 960 int i; 961 962 if (!intel_sdvo_set_value(intel_sdvo, 963 SDVO_CMD_SET_HBUF_INDEX, 964 set_buf_index, 2)) 965 return false; 966 967 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 968 &hbuf_size, 1)) 969 return false; 970 971 /* Buffer size is 0 based, hooray! */ 972 hbuf_size++; 973 974 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", 975 if_index, length, hbuf_size); 976 977 for (i = 0; i < hbuf_size; i += 8) { 978 memset(tmp, 0, 8); 979 if (i < length) 980 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 981 982 if (!intel_sdvo_set_value(intel_sdvo, 983 SDVO_CMD_SET_HBUF_DATA, 984 tmp, 8)) 985 return false; 986 } 987 988 return intel_sdvo_set_value(intel_sdvo, 989 SDVO_CMD_SET_HBUF_TXRATE, 990 &tx_rate, 1); 991} 992 993static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 994 const struct drm_display_mode *adjusted_mode) 995{ 996 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 997 struct drm_crtc *crtc = intel_sdvo->base.base.crtc; 998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 999 union hdmi_infoframe frame; 1000 int ret; 1001 ssize_t len; 1002 1003 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 1004 adjusted_mode); 1005 if (ret < 0) { 1006 DRM_ERROR("couldn't fill AVI infoframe\n"); 1007 return false; 1008 } 1009 1010 if (intel_sdvo->rgb_quant_range_selectable) { 1011 if (intel_crtc->config->limited_color_range) 1012 frame.avi.quantization_range = 1013 HDMI_QUANTIZATION_RANGE_LIMITED; 1014 else 1015 frame.avi.quantization_range = 1016 HDMI_QUANTIZATION_RANGE_FULL; 1017 } 1018 1019 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data)); 1020 if (len < 0) 1021 return false; 1022 1023 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1024 SDVO_HBUF_TX_VSYNC, 1025 sdvo_data, sizeof(sdvo_data)); 1026} 1027 1028static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) 1029{ 1030 struct intel_sdvo_tv_format format; 1031 uint32_t format_map; 1032 1033 format_map = 1 << intel_sdvo->tv_format_index; 1034 memset(&format, 0, sizeof(format)); 1035 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1036 1037 BUILD_BUG_ON(sizeof(format) != 6); 1038 return intel_sdvo_set_value(intel_sdvo, 1039 SDVO_CMD_SET_TV_FORMAT, 1040 &format, sizeof(format)); 1041} 1042 1043static bool 1044intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1045 const struct drm_display_mode *mode) 1046{ 1047 struct intel_sdvo_dtd output_dtd; 1048 1049 if (!intel_sdvo_set_target_output(intel_sdvo, 1050 intel_sdvo->attached_output)) 1051 return false; 1052 1053 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1054 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1055 return false; 1056 1057 return true; 1058} 1059 1060/* Asks the sdvo controller for the preferred input mode given the output mode. 1061 * Unfortunately we have to set up the full output mode to do that. */ 1062static bool 1063intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1064 const struct drm_display_mode *mode, 1065 struct drm_display_mode *adjusted_mode) 1066{ 1067 struct intel_sdvo_dtd input_dtd; 1068 1069 /* Reset the input timing to the screen. Assume always input 0. */ 1070 if (!intel_sdvo_set_target_input(intel_sdvo)) 1071 return false; 1072 1073 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1074 mode->clock / 10, 1075 mode->hdisplay, 1076 mode->vdisplay)) 1077 return false; 1078 1079 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1080 &input_dtd)) 1081 return false; 1082 1083 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1084 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1085 1086 return true; 1087} 1088 1089static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1090{ 1091 unsigned dotclock = pipe_config->port_clock; 1092 struct dpll *clock = &pipe_config->dpll; 1093 1094 /* SDVO TV has fixed PLL values depend on its clock range, 1095 this mirrors vbios setting. */ 1096 if (dotclock >= 100000 && dotclock < 140500) { 1097 clock->p1 = 2; 1098 clock->p2 = 10; 1099 clock->n = 3; 1100 clock->m1 = 16; 1101 clock->m2 = 8; 1102 } else if (dotclock >= 140500 && dotclock <= 200000) { 1103 clock->p1 = 1; 1104 clock->p2 = 10; 1105 clock->n = 6; 1106 clock->m1 = 12; 1107 clock->m2 = 8; 1108 } else { 1109 WARN(1, "SDVO TV clock out of range: %i\n", dotclock); 1110 } 1111 1112 pipe_config->clock_set = true; 1113} 1114 1115static bool intel_sdvo_compute_config(struct intel_encoder *encoder, 1116 struct intel_crtc_state *pipe_config) 1117{ 1118 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1119 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1120 struct drm_display_mode *mode = &pipe_config->base.mode; 1121 1122 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1123 pipe_config->pipe_bpp = 8*3; 1124 1125 if (HAS_PCH_SPLIT(encoder->base.dev)) 1126 pipe_config->has_pch_encoder = true; 1127 1128 /* We need to construct preferred input timings based on our 1129 * output timings. To do that, we have to set the output 1130 * timings, even though this isn't really the right place in 1131 * the sequence to do it. Oh well. 1132 */ 1133 if (intel_sdvo->is_tv) { 1134 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1135 return false; 1136 1137 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1138 mode, 1139 adjusted_mode); 1140 pipe_config->sdvo_tv_clock = true; 1141 } else if (intel_sdvo->is_lvds) { 1142 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1143 intel_sdvo->sdvo_lvds_fixed_mode)) 1144 return false; 1145 1146 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1147 mode, 1148 adjusted_mode); 1149 } 1150 1151 /* Make the CRTC code factor in the SDVO pixel multiplier. The 1152 * SDVO device will factor out the multiplier during mode_set. 1153 */ 1154 pipe_config->pixel_multiplier = 1155 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1156 1157 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; 1158 1159 if (intel_sdvo->color_range_auto) { 1160 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1161 /* FIXME: This bit is only valid when using TMDS encoding and 8 1162 * bit per color mode. */ 1163 if (pipe_config->has_hdmi_sink && 1164 drm_match_cea_mode(adjusted_mode) > 1) 1165 pipe_config->limited_color_range = true; 1166 } else { 1167 if (pipe_config->has_hdmi_sink && 1168 intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235) 1169 pipe_config->limited_color_range = true; 1170 } 1171 1172 /* Clock computation needs to happen after pixel multiplier. */ 1173 if (intel_sdvo->is_tv) 1174 i9xx_adjust_sdvo_tv_clock(pipe_config); 1175 1176 return true; 1177} 1178 1179static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) 1180{ 1181 struct drm_device *dev = intel_encoder->base.dev; 1182 struct drm_i915_private *dev_priv = dev->dev_private; 1183 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); 1184 struct drm_display_mode *adjusted_mode = 1185 &crtc->config->base.adjusted_mode; 1186 struct drm_display_mode *mode = &crtc->config->base.mode; 1187 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1188 u32 sdvox; 1189 struct intel_sdvo_in_out_map in_out; 1190 struct intel_sdvo_dtd input_dtd, output_dtd; 1191 int rate; 1192 1193 if (!mode) 1194 return; 1195 1196 /* First, set the input mapping for the first input to our controlled 1197 * output. This is only correct if we're a single-input device, in 1198 * which case the first input is the output from the appropriate SDVO 1199 * channel on the motherboard. In a two-input device, the first input 1200 * will be SDVOB and the second SDVOC. 1201 */ 1202 in_out.in0 = intel_sdvo->attached_output; 1203 in_out.in1 = 0; 1204 1205 intel_sdvo_set_value(intel_sdvo, 1206 SDVO_CMD_SET_IN_OUT_MAP, 1207 &in_out, sizeof(in_out)); 1208 1209 /* Set the output timings to the screen */ 1210 if (!intel_sdvo_set_target_output(intel_sdvo, 1211 intel_sdvo->attached_output)) 1212 return; 1213 1214 /* lvds has a special fixed output timing. */ 1215 if (intel_sdvo->is_lvds) 1216 intel_sdvo_get_dtd_from_mode(&output_dtd, 1217 intel_sdvo->sdvo_lvds_fixed_mode); 1218 else 1219 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1220 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1221 DRM_INFO("Setting output timings on %s failed\n", 1222 SDVO_NAME(intel_sdvo)); 1223 1224 /* Set the input timing to the screen. Assume always input 0. */ 1225 if (!intel_sdvo_set_target_input(intel_sdvo)) 1226 return; 1227 1228 if (crtc->config->has_hdmi_sink) { 1229 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1230 intel_sdvo_set_colorimetry(intel_sdvo, 1231 SDVO_COLORIMETRY_RGB256); 1232 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); 1233 } else 1234 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1235 1236 if (intel_sdvo->is_tv && 1237 !intel_sdvo_set_tv_format(intel_sdvo)) 1238 return; 1239 1240 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1241 1242 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) 1243 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1244 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1245 DRM_INFO("Setting input timings on %s failed\n", 1246 SDVO_NAME(intel_sdvo)); 1247 1248 switch (crtc->config->pixel_multiplier) { 1249 default: 1250 WARN(1, "unknown pixel multiplier specified\n"); 1251 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1252 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1253 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1254 } 1255 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1256 return; 1257 1258 /* Set the SDVO control regs. */ 1259 if (INTEL_INFO(dev)->gen >= 4) { 1260 /* The real mode polarity is set by the SDVO commands, using 1261 * struct intel_sdvo_dtd. */ 1262 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1263 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) 1264 sdvox |= HDMI_COLOR_RANGE_16_235; 1265 if (INTEL_INFO(dev)->gen < 5) 1266 sdvox |= SDVO_BORDER_ENABLE; 1267 } else { 1268 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1269 switch (intel_sdvo->sdvo_reg) { 1270 case GEN3_SDVOB: 1271 sdvox &= SDVOB_PRESERVE_MASK; 1272 break; 1273 case GEN3_SDVOC: 1274 sdvox &= SDVOC_PRESERVE_MASK; 1275 break; 1276 } 1277 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1278 } 1279 1280 if (INTEL_PCH_TYPE(dev) >= PCH_CPT) 1281 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1282 else 1283 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1284 1285 if (intel_sdvo->has_hdmi_audio) 1286 sdvox |= SDVO_AUDIO_ENABLE; 1287 1288 if (INTEL_INFO(dev)->gen >= 4) { 1289 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1290 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 1291 /* done in crtc_mode_set as it lives inside the dpll register */ 1292 } else { 1293 sdvox |= (crtc->config->pixel_multiplier - 1) 1294 << SDVO_PORT_MULTIPLY_SHIFT; 1295 } 1296 1297 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1298 INTEL_INFO(dev)->gen < 5) 1299 sdvox |= SDVO_STALL_SELECT; 1300 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1301} 1302 1303static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1304{ 1305 struct intel_sdvo_connector *intel_sdvo_connector = 1306 to_intel_sdvo_connector(&connector->base); 1307 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); 1308 u16 active_outputs = 0; 1309 1310 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1311 1312 if (active_outputs & intel_sdvo_connector->output_flag) 1313 return true; 1314 else 1315 return false; 1316} 1317 1318static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1319 enum pipe *pipe) 1320{ 1321 struct drm_device *dev = encoder->base.dev; 1322 struct drm_i915_private *dev_priv = dev->dev_private; 1323 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1324 u16 active_outputs = 0; 1325 u32 tmp; 1326 1327 tmp = I915_READ(intel_sdvo->sdvo_reg); 1328 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1329 1330 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) 1331 return false; 1332 1333 if (HAS_PCH_CPT(dev)) 1334 *pipe = PORT_TO_PIPE_CPT(tmp); 1335 else 1336 *pipe = PORT_TO_PIPE(tmp); 1337 1338 return true; 1339} 1340 1341static void intel_sdvo_get_config(struct intel_encoder *encoder, 1342 struct intel_crtc_state *pipe_config) 1343{ 1344 struct drm_device *dev = encoder->base.dev; 1345 struct drm_i915_private *dev_priv = dev->dev_private; 1346 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1347 struct intel_sdvo_dtd dtd; 1348 int encoder_pixel_multiplier = 0; 1349 int dotclock; 1350 u32 flags = 0, sdvox; 1351 u8 val; 1352 bool ret; 1353 1354 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1355 1356 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1357 if (!ret) { 1358 /* Some sdvo encoders are not spec compliant and don't 1359 * implement the mandatory get_timings function. */ 1360 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); 1361 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1362 } else { 1363 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1364 flags |= DRM_MODE_FLAG_PHSYNC; 1365 else 1366 flags |= DRM_MODE_FLAG_NHSYNC; 1367 1368 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1369 flags |= DRM_MODE_FLAG_PVSYNC; 1370 else 1371 flags |= DRM_MODE_FLAG_NVSYNC; 1372 } 1373 1374 pipe_config->base.adjusted_mode.flags |= flags; 1375 1376 /* 1377 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1378 * the sdvo port register, on all other platforms it is part of the dpll 1379 * state. Since the general pipe state readout happens before the 1380 * encoder->get_config we so already have a valid pixel multplier on all 1381 * other platfroms. 1382 */ 1383 if (IS_I915G(dev) || IS_I915GM(dev)) { 1384 pipe_config->pixel_multiplier = 1385 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1386 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1387 } 1388 1389 dotclock = pipe_config->port_clock; 1390 if (pipe_config->pixel_multiplier) 1391 dotclock /= pipe_config->pixel_multiplier; 1392 1393 if (HAS_PCH_SPLIT(dev)) 1394 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1395 1396 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1397 1398 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1399 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1400 &val, 1)) { 1401 switch (val) { 1402 case SDVO_CLOCK_RATE_MULT_1X: 1403 encoder_pixel_multiplier = 1; 1404 break; 1405 case SDVO_CLOCK_RATE_MULT_2X: 1406 encoder_pixel_multiplier = 2; 1407 break; 1408 case SDVO_CLOCK_RATE_MULT_4X: 1409 encoder_pixel_multiplier = 4; 1410 break; 1411 } 1412 } 1413 1414 if (sdvox & HDMI_COLOR_RANGE_16_235) 1415 pipe_config->limited_color_range = true; 1416 1417 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1418 &val, 1)) { 1419 if (val == SDVO_ENCODE_HDMI) 1420 pipe_config->has_hdmi_sink = true; 1421 } 1422 1423 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1424 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1425 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1426} 1427 1428static void intel_disable_sdvo(struct intel_encoder *encoder) 1429{ 1430 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1431 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1432 u32 temp; 1433 1434 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1435 if (0) 1436 intel_sdvo_set_encoder_power_state(intel_sdvo, 1437 DRM_MODE_DPMS_OFF); 1438 1439 temp = I915_READ(intel_sdvo->sdvo_reg); 1440 if ((temp & SDVO_ENABLE) != 0) { 1441 /* HW workaround for IBX, we need to move the port to 1442 * transcoder A before disabling it. */ 1443 if (HAS_PCH_IBX(encoder->base.dev)) { 1444 struct drm_crtc *crtc = encoder->base.crtc; 1445 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; 1446 1447 if (temp & SDVO_PIPE_B_SELECT) { 1448 temp &= ~SDVO_PIPE_B_SELECT; 1449 I915_WRITE(intel_sdvo->sdvo_reg, temp); 1450 POSTING_READ(intel_sdvo->sdvo_reg); 1451 1452 /* Again we need to write this twice. */ 1453 I915_WRITE(intel_sdvo->sdvo_reg, temp); 1454 POSTING_READ(intel_sdvo->sdvo_reg); 1455 1456 /* Transcoder selection bits only update 1457 * effectively on vblank. */ 1458 if (crtc) 1459 intel_wait_for_vblank(encoder->base.dev, pipe); 1460 else 1461 msleep(50); 1462 } 1463 } 1464 1465 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); 1466 } 1467} 1468 1469static void intel_enable_sdvo(struct intel_encoder *encoder) 1470{ 1471 struct drm_device *dev = encoder->base.dev; 1472 struct drm_i915_private *dev_priv = dev->dev_private; 1473 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1474 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1475 u32 temp; 1476 bool input1, input2; 1477 int i; 1478 bool success; 1479 1480 temp = I915_READ(intel_sdvo->sdvo_reg); 1481 if ((temp & SDVO_ENABLE) == 0) { 1482 /* HW workaround for IBX, we need to move the port 1483 * to transcoder A before disabling it, so restore it here. */ 1484 if (HAS_PCH_IBX(dev)) 1485 temp |= SDVO_PIPE_SEL(intel_crtc->pipe); 1486 1487 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); 1488 } 1489 for (i = 0; i < 2; i++) 1490 intel_wait_for_vblank(dev, intel_crtc->pipe); 1491 1492 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1493 /* Warn if the device reported failure to sync. 1494 * A lot of SDVO devices fail to notify of sync, but it's 1495 * a given it the status is a success, we succeeded. 1496 */ 1497 if (success && !input1) { 1498 DRM_DEBUG_KMS("First %s output reported failure to " 1499 "sync\n", SDVO_NAME(intel_sdvo)); 1500 } 1501 1502 if (0) 1503 intel_sdvo_set_encoder_power_state(intel_sdvo, 1504 DRM_MODE_DPMS_ON); 1505 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1506} 1507 1508/* Special dpms function to support cloning between dvo/sdvo/crt. */ 1509static void intel_sdvo_dpms(struct drm_connector *connector, int mode) 1510{ 1511 struct drm_crtc *crtc; 1512 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1513 1514 /* dvo supports only 2 dpms states. */ 1515 if (mode != DRM_MODE_DPMS_ON) 1516 mode = DRM_MODE_DPMS_OFF; 1517 1518 if (mode == connector->dpms) 1519 return; 1520 1521 connector->dpms = mode; 1522 1523 /* Only need to change hw state when actually enabled */ 1524 crtc = intel_sdvo->base.base.crtc; 1525 if (!crtc) { 1526 intel_sdvo->base.connectors_active = false; 1527 return; 1528 } 1529 1530 /* We set active outputs manually below in case pipe dpms doesn't change 1531 * due to cloning. */ 1532 if (mode != DRM_MODE_DPMS_ON) { 1533 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1534 if (0) 1535 intel_sdvo_set_encoder_power_state(intel_sdvo, mode); 1536 1537 intel_sdvo->base.connectors_active = false; 1538 1539 intel_crtc_update_dpms(crtc); 1540 } else { 1541 intel_sdvo->base.connectors_active = true; 1542 1543 intel_crtc_update_dpms(crtc); 1544 1545 if (0) 1546 intel_sdvo_set_encoder_power_state(intel_sdvo, mode); 1547 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1548 } 1549 1550 intel_modeset_check_state(connector->dev); 1551} 1552 1553static enum drm_mode_status 1554intel_sdvo_mode_valid(struct drm_connector *connector, 1555 struct drm_display_mode *mode) 1556{ 1557 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1558 1559 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1560 return MODE_NO_DBLESCAN; 1561 1562 if (intel_sdvo->pixel_clock_min > mode->clock) 1563 return MODE_CLOCK_LOW; 1564 1565 if (intel_sdvo->pixel_clock_max < mode->clock) 1566 return MODE_CLOCK_HIGH; 1567 1568 if (intel_sdvo->is_lvds) { 1569 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) 1570 return MODE_PANEL; 1571 1572 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) 1573 return MODE_PANEL; 1574 } 1575 1576 return MODE_OK; 1577} 1578 1579static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1580{ 1581 BUILD_BUG_ON(sizeof(*caps) != 8); 1582 if (!intel_sdvo_get_value(intel_sdvo, 1583 SDVO_CMD_GET_DEVICE_CAPS, 1584 caps, sizeof(*caps))) 1585 return false; 1586 1587 DRM_DEBUG_KMS("SDVO capabilities:\n" 1588 " vendor_id: %d\n" 1589 " device_id: %d\n" 1590 " device_rev_id: %d\n" 1591 " sdvo_version_major: %d\n" 1592 " sdvo_version_minor: %d\n" 1593 " sdvo_inputs_mask: %d\n" 1594 " smooth_scaling: %d\n" 1595 " sharp_scaling: %d\n" 1596 " up_scaling: %d\n" 1597 " down_scaling: %d\n" 1598 " stall_support: %d\n" 1599 " output_flags: %d\n", 1600 caps->vendor_id, 1601 caps->device_id, 1602 caps->device_rev_id, 1603 caps->sdvo_version_major, 1604 caps->sdvo_version_minor, 1605 caps->sdvo_inputs_mask, 1606 caps->smooth_scaling, 1607 caps->sharp_scaling, 1608 caps->up_scaling, 1609 caps->down_scaling, 1610 caps->stall_support, 1611 caps->output_flags); 1612 1613 return true; 1614} 1615 1616static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 1617{ 1618 struct drm_device *dev = intel_sdvo->base.base.dev; 1619 uint16_t hotplug; 1620 1621 if (!I915_HAS_HOTPLUG(dev)) 1622 return 0; 1623 1624 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 1625 * on the line. */ 1626 if (IS_I945G(dev) || IS_I945GM(dev)) 1627 return 0; 1628 1629 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1630 &hotplug, sizeof(hotplug))) 1631 return 0; 1632 1633 return hotplug; 1634} 1635 1636static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 1637{ 1638 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1639 1640 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 1641 &intel_sdvo->hotplug_active, 2); 1642} 1643 1644static bool 1645intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1646{ 1647 /* Is there more than one type of output? */ 1648 return hweight16(intel_sdvo->caps.output_flags) > 1; 1649} 1650 1651static struct edid * 1652intel_sdvo_get_edid(struct drm_connector *connector) 1653{ 1654 struct intel_sdvo *sdvo = intel_attached_sdvo(connector); 1655 return drm_get_edid(connector, &sdvo->ddc); 1656} 1657 1658/* Mac mini hack -- use the same DDC as the analog connector */ 1659static struct edid * 1660intel_sdvo_get_analog_edid(struct drm_connector *connector) 1661{ 1662 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1663 1664 return drm_get_edid(connector, 1665 intel_gmbus_get_adapter(dev_priv, 1666 dev_priv->vbt.crt_ddc_pin)); 1667} 1668 1669static enum drm_connector_status 1670intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 1671{ 1672 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1673 enum drm_connector_status status; 1674 struct edid *edid; 1675 1676 edid = intel_sdvo_get_edid(connector); 1677 1678 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 1679 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 1680 1681 /* 1682 * Don't use the 1 as the argument of DDC bus switch to get 1683 * the EDID. It is used for SDVO SPD ROM. 1684 */ 1685 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 1686 intel_sdvo->ddc_bus = ddc; 1687 edid = intel_sdvo_get_edid(connector); 1688 if (edid) 1689 break; 1690 } 1691 /* 1692 * If we found the EDID on the other bus, 1693 * assume that is the correct DDC bus. 1694 */ 1695 if (edid == NULL) 1696 intel_sdvo->ddc_bus = saved_ddc; 1697 } 1698 1699 /* 1700 * When there is no edid and no monitor is connected with VGA 1701 * port, try to use the CRT ddc to read the EDID for DVI-connector. 1702 */ 1703 if (edid == NULL) 1704 edid = intel_sdvo_get_analog_edid(connector); 1705 1706 status = connector_status_unknown; 1707 if (edid != NULL) { 1708 /* DDC bus is shared, match EDID to connector type */ 1709 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 1710 status = connector_status_connected; 1711 if (intel_sdvo->is_hdmi) { 1712 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 1713 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 1714 intel_sdvo->rgb_quant_range_selectable = 1715 drm_rgb_quant_range_selectable(edid); 1716 } 1717 } else 1718 status = connector_status_disconnected; 1719 kfree(edid); 1720 } 1721 1722 if (status == connector_status_connected) { 1723 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1724 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) 1725 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); 1726 } 1727 1728 return status; 1729} 1730 1731static bool 1732intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 1733 struct edid *edid) 1734{ 1735 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1736 bool connector_is_digital = !!IS_DIGITAL(sdvo); 1737 1738 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 1739 connector_is_digital, monitor_is_digital); 1740 return connector_is_digital == monitor_is_digital; 1741} 1742 1743static enum drm_connector_status 1744intel_sdvo_detect(struct drm_connector *connector, bool force) 1745{ 1746 uint16_t response; 1747 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1748 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1749 enum drm_connector_status ret; 1750 1751 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1752 connector->base.id, connector->name); 1753 1754 if (!intel_sdvo_get_value(intel_sdvo, 1755 SDVO_CMD_GET_ATTACHED_DISPLAYS, 1756 &response, 2)) 1757 return connector_status_unknown; 1758 1759 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 1760 response & 0xff, response >> 8, 1761 intel_sdvo_connector->output_flag); 1762 1763 if (response == 0) 1764 return connector_status_disconnected; 1765 1766 intel_sdvo->attached_output = response; 1767 1768 intel_sdvo->has_hdmi_monitor = false; 1769 intel_sdvo->has_hdmi_audio = false; 1770 intel_sdvo->rgb_quant_range_selectable = false; 1771 1772 if ((intel_sdvo_connector->output_flag & response) == 0) 1773 ret = connector_status_disconnected; 1774 else if (IS_TMDS(intel_sdvo_connector)) 1775 ret = intel_sdvo_tmds_sink_detect(connector); 1776 else { 1777 struct edid *edid; 1778 1779 /* if we have an edid check it matches the connection */ 1780 edid = intel_sdvo_get_edid(connector); 1781 if (edid == NULL) 1782 edid = intel_sdvo_get_analog_edid(connector); 1783 if (edid != NULL) { 1784 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 1785 edid)) 1786 ret = connector_status_connected; 1787 else 1788 ret = connector_status_disconnected; 1789 1790 kfree(edid); 1791 } else 1792 ret = connector_status_connected; 1793 } 1794 1795 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1796 if (ret == connector_status_connected) { 1797 intel_sdvo->is_tv = false; 1798 intel_sdvo->is_lvds = false; 1799 1800 if (response & SDVO_TV_MASK) 1801 intel_sdvo->is_tv = true; 1802 if (response & SDVO_LVDS_MASK) 1803 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; 1804 } 1805 1806 return ret; 1807} 1808 1809static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1810{ 1811 struct edid *edid; 1812 1813 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1814 connector->base.id, connector->name); 1815 1816 /* set the bus switch and get the modes */ 1817 edid = intel_sdvo_get_edid(connector); 1818 1819 /* 1820 * Mac mini hack. On this device, the DVI-I connector shares one DDC 1821 * link between analog and digital outputs. So, if the regular SDVO 1822 * DDC fails, check to see if the analog output is disconnected, in 1823 * which case we'll look there for the digital DDC data. 1824 */ 1825 if (edid == NULL) 1826 edid = intel_sdvo_get_analog_edid(connector); 1827 1828 if (edid != NULL) { 1829 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 1830 edid)) { 1831 drm_mode_connector_update_edid_property(connector, edid); 1832 drm_add_edid_modes(connector, edid); 1833 } 1834 1835 kfree(edid); 1836 } 1837} 1838 1839/* 1840 * Set of SDVO TV modes. 1841 * Note! This is in reply order (see loop in get_tv_modes). 1842 * XXX: all 60Hz refresh? 1843 */ 1844static const struct drm_display_mode sdvo_tv_modes[] = { 1845 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 1846 416, 0, 200, 201, 232, 233, 0, 1847 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1848 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 1849 416, 0, 240, 241, 272, 273, 0, 1850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1851 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 1852 496, 0, 300, 301, 332, 333, 0, 1853 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1854 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 1855 736, 0, 350, 351, 382, 383, 0, 1856 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1857 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 1858 736, 0, 400, 401, 432, 433, 0, 1859 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1860 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 1861 736, 0, 480, 481, 512, 513, 0, 1862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1863 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 1864 800, 0, 480, 481, 512, 513, 0, 1865 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1866 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 1867 800, 0, 576, 577, 608, 609, 0, 1868 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1869 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 1870 816, 0, 350, 351, 382, 383, 0, 1871 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1872 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 1873 816, 0, 400, 401, 432, 433, 0, 1874 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1875 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 1876 816, 0, 480, 481, 512, 513, 0, 1877 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1878 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 1879 816, 0, 540, 541, 572, 573, 0, 1880 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1881 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 1882 816, 0, 576, 577, 608, 609, 0, 1883 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1884 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 1885 864, 0, 576, 577, 608, 609, 0, 1886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1887 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 1888 896, 0, 600, 601, 632, 633, 0, 1889 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1890 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 1891 928, 0, 624, 625, 656, 657, 0, 1892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1893 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 1894 1016, 0, 766, 767, 798, 799, 0, 1895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1896 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 1897 1120, 0, 768, 769, 800, 801, 0, 1898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1899 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 1900 1376, 0, 1024, 1025, 1056, 1057, 0, 1901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1902}; 1903 1904static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 1905{ 1906 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1907 struct intel_sdvo_sdtv_resolution_request tv_res; 1908 uint32_t reply = 0, format_map = 0; 1909 int i; 1910 1911 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1912 connector->base.id, connector->name); 1913 1914 /* Read the list of supported input resolutions for the selected TV 1915 * format. 1916 */ 1917 format_map = 1 << intel_sdvo->tv_format_index; 1918 memcpy(&tv_res, &format_map, 1919 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 1920 1921 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 1922 return; 1923 1924 BUILD_BUG_ON(sizeof(tv_res) != 3); 1925 if (!intel_sdvo_write_cmd(intel_sdvo, 1926 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1927 &tv_res, sizeof(tv_res))) 1928 return; 1929 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 1930 return; 1931 1932 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 1933 if (reply & (1 << i)) { 1934 struct drm_display_mode *nmode; 1935 nmode = drm_mode_duplicate(connector->dev, 1936 &sdvo_tv_modes[i]); 1937 if (nmode) 1938 drm_mode_probed_add(connector, nmode); 1939 } 1940} 1941 1942static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1943{ 1944 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1945 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1946 struct drm_display_mode *newmode; 1947 1948 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1949 connector->base.id, connector->name); 1950 1951 /* 1952 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 1953 * SDVO->LVDS transcoders can't cope with the EDID mode. 1954 */ 1955 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { 1956 newmode = drm_mode_duplicate(connector->dev, 1957 dev_priv->vbt.sdvo_lvds_vbt_mode); 1958 if (newmode != NULL) { 1959 /* Guarantee the mode is preferred */ 1960 newmode->type = (DRM_MODE_TYPE_PREFERRED | 1961 DRM_MODE_TYPE_DRIVER); 1962 drm_mode_probed_add(connector, newmode); 1963 } 1964 } 1965 1966 /* 1967 * Attempt to get the mode list from DDC. 1968 * Assume that the preferred modes are 1969 * arranged in priority order. 1970 */ 1971 intel_ddc_get_modes(connector, &intel_sdvo->ddc); 1972 1973 list_for_each_entry(newmode, &connector->probed_modes, head) { 1974 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1975 intel_sdvo->sdvo_lvds_fixed_mode = 1976 drm_mode_duplicate(connector->dev, newmode); 1977 1978 intel_sdvo->is_lvds = true; 1979 break; 1980 } 1981 } 1982} 1983 1984static int intel_sdvo_get_modes(struct drm_connector *connector) 1985{ 1986 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1987 1988 if (IS_TV(intel_sdvo_connector)) 1989 intel_sdvo_get_tv_modes(connector); 1990 else if (IS_LVDS(intel_sdvo_connector)) 1991 intel_sdvo_get_lvds_modes(connector); 1992 else 1993 intel_sdvo_get_ddc_modes(connector); 1994 1995 return !list_empty(&connector->probed_modes); 1996} 1997 1998static void intel_sdvo_destroy(struct drm_connector *connector) 1999{ 2000 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2001 2002 drm_connector_cleanup(connector); 2003 kfree(intel_sdvo_connector); 2004} 2005 2006static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) 2007{ 2008 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 2009 struct edid *edid; 2010 bool has_audio = false; 2011 2012 if (!intel_sdvo->is_hdmi) 2013 return false; 2014 2015 edid = intel_sdvo_get_edid(connector); 2016 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) 2017 has_audio = drm_detect_monitor_audio(edid); 2018 kfree(edid); 2019 2020 return has_audio; 2021} 2022 2023static int 2024intel_sdvo_set_property(struct drm_connector *connector, 2025 struct drm_property *property, 2026 uint64_t val) 2027{ 2028 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 2029 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2030 struct drm_i915_private *dev_priv = connector->dev->dev_private; 2031 uint16_t temp_value; 2032 uint8_t cmd; 2033 int ret; 2034 2035 ret = drm_object_property_set_value(&connector->base, property, val); 2036 if (ret) 2037 return ret; 2038 2039 if (property == dev_priv->force_audio_property) { 2040 int i = val; 2041 bool has_audio; 2042 2043 if (i == intel_sdvo_connector->force_audio) 2044 return 0; 2045 2046 intel_sdvo_connector->force_audio = i; 2047 2048 if (i == HDMI_AUDIO_AUTO) 2049 has_audio = intel_sdvo_detect_hdmi_audio(connector); 2050 else 2051 has_audio = (i == HDMI_AUDIO_ON); 2052 2053 if (has_audio == intel_sdvo->has_hdmi_audio) 2054 return 0; 2055 2056 intel_sdvo->has_hdmi_audio = has_audio; 2057 goto done; 2058 } 2059 2060 if (property == dev_priv->broadcast_rgb_property) { 2061 bool old_auto = intel_sdvo->color_range_auto; 2062 uint32_t old_range = intel_sdvo->color_range; 2063 2064 switch (val) { 2065 case INTEL_BROADCAST_RGB_AUTO: 2066 intel_sdvo->color_range_auto = true; 2067 break; 2068 case INTEL_BROADCAST_RGB_FULL: 2069 intel_sdvo->color_range_auto = false; 2070 intel_sdvo->color_range = 0; 2071 break; 2072 case INTEL_BROADCAST_RGB_LIMITED: 2073 intel_sdvo->color_range_auto = false; 2074 /* FIXME: this bit is only valid when using TMDS 2075 * encoding and 8 bit per color mode. */ 2076 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; 2077 break; 2078 default: 2079 return -EINVAL; 2080 } 2081 2082 if (old_auto == intel_sdvo->color_range_auto && 2083 old_range == intel_sdvo->color_range) 2084 return 0; 2085 2086 goto done; 2087 } 2088 2089#define CHECK_PROPERTY(name, NAME) \ 2090 if (intel_sdvo_connector->name == property) { \ 2091 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ 2092 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ 2093 cmd = SDVO_CMD_SET_##NAME; \ 2094 intel_sdvo_connector->cur_##name = temp_value; \ 2095 goto set_value; \ 2096 } 2097 2098 if (property == intel_sdvo_connector->tv_format) { 2099 if (val >= TV_FORMAT_NUM) 2100 return -EINVAL; 2101 2102 if (intel_sdvo->tv_format_index == 2103 intel_sdvo_connector->tv_format_supported[val]) 2104 return 0; 2105 2106 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; 2107 goto done; 2108 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { 2109 temp_value = val; 2110 if (intel_sdvo_connector->left == property) { 2111 drm_object_property_set_value(&connector->base, 2112 intel_sdvo_connector->right, val); 2113 if (intel_sdvo_connector->left_margin == temp_value) 2114 return 0; 2115 2116 intel_sdvo_connector->left_margin = temp_value; 2117 intel_sdvo_connector->right_margin = temp_value; 2118 temp_value = intel_sdvo_connector->max_hscan - 2119 intel_sdvo_connector->left_margin; 2120 cmd = SDVO_CMD_SET_OVERSCAN_H; 2121 goto set_value; 2122 } else if (intel_sdvo_connector->right == property) { 2123 drm_object_property_set_value(&connector->base, 2124 intel_sdvo_connector->left, val); 2125 if (intel_sdvo_connector->right_margin == temp_value) 2126 return 0; 2127 2128 intel_sdvo_connector->left_margin = temp_value; 2129 intel_sdvo_connector->right_margin = temp_value; 2130 temp_value = intel_sdvo_connector->max_hscan - 2131 intel_sdvo_connector->left_margin; 2132 cmd = SDVO_CMD_SET_OVERSCAN_H; 2133 goto set_value; 2134 } else if (intel_sdvo_connector->top == property) { 2135 drm_object_property_set_value(&connector->base, 2136 intel_sdvo_connector->bottom, val); 2137 if (intel_sdvo_connector->top_margin == temp_value) 2138 return 0; 2139 2140 intel_sdvo_connector->top_margin = temp_value; 2141 intel_sdvo_connector->bottom_margin = temp_value; 2142 temp_value = intel_sdvo_connector->max_vscan - 2143 intel_sdvo_connector->top_margin; 2144 cmd = SDVO_CMD_SET_OVERSCAN_V; 2145 goto set_value; 2146 } else if (intel_sdvo_connector->bottom == property) { 2147 drm_object_property_set_value(&connector->base, 2148 intel_sdvo_connector->top, val); 2149 if (intel_sdvo_connector->bottom_margin == temp_value) 2150 return 0; 2151 2152 intel_sdvo_connector->top_margin = temp_value; 2153 intel_sdvo_connector->bottom_margin = temp_value; 2154 temp_value = intel_sdvo_connector->max_vscan - 2155 intel_sdvo_connector->top_margin; 2156 cmd = SDVO_CMD_SET_OVERSCAN_V; 2157 goto set_value; 2158 } 2159 CHECK_PROPERTY(hpos, HPOS) 2160 CHECK_PROPERTY(vpos, VPOS) 2161 CHECK_PROPERTY(saturation, SATURATION) 2162 CHECK_PROPERTY(contrast, CONTRAST) 2163 CHECK_PROPERTY(hue, HUE) 2164 CHECK_PROPERTY(brightness, BRIGHTNESS) 2165 CHECK_PROPERTY(sharpness, SHARPNESS) 2166 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) 2167 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) 2168 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) 2169 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) 2170 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) 2171 CHECK_PROPERTY(dot_crawl, DOT_CRAWL) 2172 } 2173 2174 return -EINVAL; /* unknown property */ 2175 2176set_value: 2177 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) 2178 return -EIO; 2179 2180 2181done: 2182 if (intel_sdvo->base.base.crtc) 2183 intel_crtc_restore_mode(intel_sdvo->base.base.crtc); 2184 2185 return 0; 2186#undef CHECK_PROPERTY 2187} 2188 2189static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2190 .dpms = intel_sdvo_dpms, 2191 .detect = intel_sdvo_detect, 2192 .fill_modes = drm_helper_probe_single_connector_modes, 2193 .set_property = intel_sdvo_set_property, 2194 .atomic_get_property = intel_connector_atomic_get_property, 2195 .destroy = intel_sdvo_destroy, 2196 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2197 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2198}; 2199 2200static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2201 .get_modes = intel_sdvo_get_modes, 2202 .mode_valid = intel_sdvo_mode_valid, 2203 .best_encoder = intel_best_encoder, 2204}; 2205 2206static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2207{ 2208 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); 2209 2210 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) 2211 drm_mode_destroy(encoder->dev, 2212 intel_sdvo->sdvo_lvds_fixed_mode); 2213 2214 i2c_del_adapter(&intel_sdvo->ddc); 2215 intel_encoder_destroy(encoder); 2216} 2217 2218static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2219 .destroy = intel_sdvo_enc_destroy, 2220}; 2221 2222static void 2223intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2224{ 2225 uint16_t mask = 0; 2226 unsigned int num_bits; 2227 2228 /* Make a mask of outputs less than or equal to our own priority in the 2229 * list. 2230 */ 2231 switch (sdvo->controlled_output) { 2232 case SDVO_OUTPUT_LVDS1: 2233 mask |= SDVO_OUTPUT_LVDS1; 2234 case SDVO_OUTPUT_LVDS0: 2235 mask |= SDVO_OUTPUT_LVDS0; 2236 case SDVO_OUTPUT_TMDS1: 2237 mask |= SDVO_OUTPUT_TMDS1; 2238 case SDVO_OUTPUT_TMDS0: 2239 mask |= SDVO_OUTPUT_TMDS0; 2240 case SDVO_OUTPUT_RGB1: 2241 mask |= SDVO_OUTPUT_RGB1; 2242 case SDVO_OUTPUT_RGB0: 2243 mask |= SDVO_OUTPUT_RGB0; 2244 break; 2245 } 2246 2247 /* Count bits to find what number we are in the priority list. */ 2248 mask &= sdvo->caps.output_flags; 2249 num_bits = hweight16(mask); 2250 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2251 if (num_bits > 3) 2252 num_bits = 3; 2253 2254 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2255 sdvo->ddc_bus = 1 << num_bits; 2256} 2257 2258/** 2259 * Choose the appropriate DDC bus for control bus switch command for this 2260 * SDVO output based on the controlled output. 2261 * 2262 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2263 * outputs, then LVDS outputs. 2264 */ 2265static void 2266intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2267 struct intel_sdvo *sdvo, u32 reg) 2268{ 2269 struct sdvo_device_mapping *mapping; 2270 2271 if (sdvo->is_sdvob) 2272 mapping = &(dev_priv->sdvo_mappings[0]); 2273 else 2274 mapping = &(dev_priv->sdvo_mappings[1]); 2275 2276 if (mapping->initialized) 2277 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2278 else 2279 intel_sdvo_guess_ddc_bus(sdvo); 2280} 2281 2282static void 2283intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2284 struct intel_sdvo *sdvo, u32 reg) 2285{ 2286 struct sdvo_device_mapping *mapping; 2287 u8 pin; 2288 2289 if (sdvo->is_sdvob) 2290 mapping = &dev_priv->sdvo_mappings[0]; 2291 else 2292 mapping = &dev_priv->sdvo_mappings[1]; 2293 2294 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin)) 2295 pin = mapping->i2c_pin; 2296 else 2297 pin = GMBUS_PORT_DPB; 2298 2299 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2300 2301 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2302 * our code totally fails once we start using gmbus. Hence fall back to 2303 * bit banging for now. */ 2304 intel_gmbus_force_bit(sdvo->i2c, true); 2305} 2306 2307/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2308static void 2309intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2310{ 2311 intel_gmbus_force_bit(sdvo->i2c, false); 2312} 2313 2314static bool 2315intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) 2316{ 2317 return intel_sdvo_check_supp_encode(intel_sdvo); 2318} 2319 2320static u8 2321intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) 2322{ 2323 struct drm_i915_private *dev_priv = dev->dev_private; 2324 struct sdvo_device_mapping *my_mapping, *other_mapping; 2325 2326 if (sdvo->is_sdvob) { 2327 my_mapping = &dev_priv->sdvo_mappings[0]; 2328 other_mapping = &dev_priv->sdvo_mappings[1]; 2329 } else { 2330 my_mapping = &dev_priv->sdvo_mappings[1]; 2331 other_mapping = &dev_priv->sdvo_mappings[0]; 2332 } 2333 2334 /* If the BIOS described our SDVO device, take advantage of it. */ 2335 if (my_mapping->slave_addr) 2336 return my_mapping->slave_addr; 2337 2338 /* If the BIOS only described a different SDVO device, use the 2339 * address that it isn't using. 2340 */ 2341 if (other_mapping->slave_addr) { 2342 if (other_mapping->slave_addr == 0x70) 2343 return 0x72; 2344 else 2345 return 0x70; 2346 } 2347 2348 /* No SDVO device info is found for another DVO port, 2349 * so use mapping assumption we had before BIOS parsing. 2350 */ 2351 if (sdvo->is_sdvob) 2352 return 0x70; 2353 else 2354 return 0x72; 2355} 2356 2357static void 2358intel_sdvo_connector_unregister(struct intel_connector *intel_connector) 2359{ 2360 struct drm_connector *drm_connector; 2361 struct intel_sdvo *sdvo_encoder; 2362 2363 drm_connector = &intel_connector->base; 2364 sdvo_encoder = intel_attached_sdvo(&intel_connector->base); 2365 2366 sysfs_remove_link(&drm_connector->kdev->kobj, 2367 sdvo_encoder->ddc.dev.kobj.name); 2368 intel_connector_unregister(intel_connector); 2369} 2370 2371static int 2372intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2373 struct intel_sdvo *encoder) 2374{ 2375 struct drm_connector *drm_connector; 2376 int ret; 2377 2378 drm_connector = &connector->base.base; 2379 ret = drm_connector_init(encoder->base.base.dev, 2380 drm_connector, 2381 &intel_sdvo_connector_funcs, 2382 connector->base.base.connector_type); 2383 if (ret < 0) 2384 return ret; 2385 2386 drm_connector_helper_add(drm_connector, 2387 &intel_sdvo_connector_helper_funcs); 2388 2389 connector->base.base.interlace_allowed = 1; 2390 connector->base.base.doublescan_allowed = 0; 2391 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2392 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2393 connector->base.unregister = intel_sdvo_connector_unregister; 2394 2395 intel_connector_attach_encoder(&connector->base, &encoder->base); 2396 ret = drm_connector_register(drm_connector); 2397 if (ret < 0) 2398 goto err1; 2399 2400 ret = sysfs_create_link(&drm_connector->kdev->kobj, 2401 &encoder->ddc.dev.kobj, 2402 encoder->ddc.dev.kobj.name); 2403 if (ret < 0) 2404 goto err2; 2405 2406 return 0; 2407 2408err2: 2409 drm_connector_unregister(drm_connector); 2410err1: 2411 drm_connector_cleanup(drm_connector); 2412 2413 return ret; 2414} 2415 2416static void 2417intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2418 struct intel_sdvo_connector *connector) 2419{ 2420 struct drm_device *dev = connector->base.base.dev; 2421 2422 intel_attach_force_audio_property(&connector->base.base); 2423 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { 2424 intel_attach_broadcast_rgb_property(&connector->base.base); 2425 intel_sdvo->color_range_auto = true; 2426 } 2427} 2428 2429static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2430{ 2431 struct intel_sdvo_connector *sdvo_connector; 2432 2433 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); 2434 if (!sdvo_connector) 2435 return NULL; 2436 2437 if (intel_connector_init(&sdvo_connector->base) < 0) { 2438 kfree(sdvo_connector); 2439 return NULL; 2440 } 2441 2442 return sdvo_connector; 2443} 2444 2445static bool 2446intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) 2447{ 2448 struct drm_encoder *encoder = &intel_sdvo->base.base; 2449 struct drm_connector *connector; 2450 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2451 struct intel_connector *intel_connector; 2452 struct intel_sdvo_connector *intel_sdvo_connector; 2453 2454 DRM_DEBUG_KMS("initialising DVI device %d\n", device); 2455 2456 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2457 if (!intel_sdvo_connector) 2458 return false; 2459 2460 if (device == 0) { 2461 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 2462 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2463 } else if (device == 1) { 2464 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 2465 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2466 } 2467 2468 intel_connector = &intel_sdvo_connector->base; 2469 connector = &intel_connector->base; 2470 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2471 intel_sdvo_connector->output_flag) { 2472 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2473 /* Some SDVO devices have one-shot hotplug interrupts. 2474 * Ensure that they get re-enabled when an interrupt happens. 2475 */ 2476 intel_encoder->hot_plug = intel_sdvo_enable_hotplug; 2477 intel_sdvo_enable_hotplug(intel_encoder); 2478 } else { 2479 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2480 } 2481 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2482 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2483 2484 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { 2485 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2486 intel_sdvo->is_hdmi = true; 2487 } 2488 2489 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2490 kfree(intel_sdvo_connector); 2491 return false; 2492 } 2493 2494 if (intel_sdvo->is_hdmi) 2495 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2496 2497 return true; 2498} 2499 2500static bool 2501intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) 2502{ 2503 struct drm_encoder *encoder = &intel_sdvo->base.base; 2504 struct drm_connector *connector; 2505 struct intel_connector *intel_connector; 2506 struct intel_sdvo_connector *intel_sdvo_connector; 2507 2508 DRM_DEBUG_KMS("initialising TV type %d\n", type); 2509 2510 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2511 if (!intel_sdvo_connector) 2512 return false; 2513 2514 intel_connector = &intel_sdvo_connector->base; 2515 connector = &intel_connector->base; 2516 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2517 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2518 2519 intel_sdvo->controlled_output |= type; 2520 intel_sdvo_connector->output_flag = type; 2521 2522 intel_sdvo->is_tv = true; 2523 2524 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2525 kfree(intel_sdvo_connector); 2526 return false; 2527 } 2528 2529 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2530 goto err; 2531 2532 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2533 goto err; 2534 2535 return true; 2536 2537err: 2538 drm_connector_unregister(connector); 2539 intel_sdvo_destroy(connector); 2540 return false; 2541} 2542 2543static bool 2544intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) 2545{ 2546 struct drm_encoder *encoder = &intel_sdvo->base.base; 2547 struct drm_connector *connector; 2548 struct intel_connector *intel_connector; 2549 struct intel_sdvo_connector *intel_sdvo_connector; 2550 2551 DRM_DEBUG_KMS("initialising analog device %d\n", device); 2552 2553 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2554 if (!intel_sdvo_connector) 2555 return false; 2556 2557 intel_connector = &intel_sdvo_connector->base; 2558 connector = &intel_connector->base; 2559 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2560 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2561 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2562 2563 if (device == 0) { 2564 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2565 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2566 } else if (device == 1) { 2567 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2568 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2569 } 2570 2571 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2572 kfree(intel_sdvo_connector); 2573 return false; 2574 } 2575 2576 return true; 2577} 2578 2579static bool 2580intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) 2581{ 2582 struct drm_encoder *encoder = &intel_sdvo->base.base; 2583 struct drm_connector *connector; 2584 struct intel_connector *intel_connector; 2585 struct intel_sdvo_connector *intel_sdvo_connector; 2586 2587 DRM_DEBUG_KMS("initialising LVDS device %d\n", device); 2588 2589 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2590 if (!intel_sdvo_connector) 2591 return false; 2592 2593 intel_connector = &intel_sdvo_connector->base; 2594 connector = &intel_connector->base; 2595 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2596 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2597 2598 if (device == 0) { 2599 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2600 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2601 } else if (device == 1) { 2602 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2603 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2604 } 2605 2606 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2607 kfree(intel_sdvo_connector); 2608 return false; 2609 } 2610 2611 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2612 goto err; 2613 2614 return true; 2615 2616err: 2617 drm_connector_unregister(connector); 2618 intel_sdvo_destroy(connector); 2619 return false; 2620} 2621 2622static bool 2623intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) 2624{ 2625 intel_sdvo->is_tv = false; 2626 intel_sdvo->is_lvds = false; 2627 2628 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2629 2630 if (flags & SDVO_OUTPUT_TMDS0) 2631 if (!intel_sdvo_dvi_init(intel_sdvo, 0)) 2632 return false; 2633 2634 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2635 if (!intel_sdvo_dvi_init(intel_sdvo, 1)) 2636 return false; 2637 2638 /* TV has no XXX1 function block */ 2639 if (flags & SDVO_OUTPUT_SVID0) 2640 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) 2641 return false; 2642 2643 if (flags & SDVO_OUTPUT_CVBS0) 2644 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) 2645 return false; 2646 2647 if (flags & SDVO_OUTPUT_YPRPB0) 2648 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) 2649 return false; 2650 2651 if (flags & SDVO_OUTPUT_RGB0) 2652 if (!intel_sdvo_analog_init(intel_sdvo, 0)) 2653 return false; 2654 2655 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2656 if (!intel_sdvo_analog_init(intel_sdvo, 1)) 2657 return false; 2658 2659 if (flags & SDVO_OUTPUT_LVDS0) 2660 if (!intel_sdvo_lvds_init(intel_sdvo, 0)) 2661 return false; 2662 2663 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2664 if (!intel_sdvo_lvds_init(intel_sdvo, 1)) 2665 return false; 2666 2667 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2668 unsigned char bytes[2]; 2669 2670 intel_sdvo->controlled_output = 0; 2671 memcpy(bytes, &intel_sdvo->caps.output_flags, 2); 2672 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2673 SDVO_NAME(intel_sdvo), 2674 bytes[0], bytes[1]); 2675 return false; 2676 } 2677 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2678 2679 return true; 2680} 2681 2682static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 2683{ 2684 struct drm_device *dev = intel_sdvo->base.base.dev; 2685 struct drm_connector *connector, *tmp; 2686 2687 list_for_each_entry_safe(connector, tmp, 2688 &dev->mode_config.connector_list, head) { 2689 if (intel_attached_encoder(connector) == &intel_sdvo->base) { 2690 drm_connector_unregister(connector); 2691 intel_sdvo_destroy(connector); 2692 } 2693 } 2694} 2695 2696static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2697 struct intel_sdvo_connector *intel_sdvo_connector, 2698 int type) 2699{ 2700 struct drm_device *dev = intel_sdvo->base.base.dev; 2701 struct intel_sdvo_tv_format format; 2702 uint32_t format_map, i; 2703 2704 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2705 return false; 2706 2707 BUILD_BUG_ON(sizeof(format) != 6); 2708 if (!intel_sdvo_get_value(intel_sdvo, 2709 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2710 &format, sizeof(format))) 2711 return false; 2712 2713 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2714 2715 if (format_map == 0) 2716 return false; 2717 2718 intel_sdvo_connector->format_supported_num = 0; 2719 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2720 if (format_map & (1 << i)) 2721 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 2722 2723 2724 intel_sdvo_connector->tv_format = 2725 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2726 "mode", intel_sdvo_connector->format_supported_num); 2727 if (!intel_sdvo_connector->tv_format) 2728 return false; 2729 2730 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2731 drm_property_add_enum( 2732 intel_sdvo_connector->tv_format, i, 2733 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 2734 2735 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; 2736 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 2737 intel_sdvo_connector->tv_format, 0); 2738 return true; 2739 2740} 2741 2742#define ENHANCEMENT(name, NAME) do { \ 2743 if (enhancements.name) { \ 2744 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 2745 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 2746 return false; \ 2747 intel_sdvo_connector->max_##name = data_value[0]; \ 2748 intel_sdvo_connector->cur_##name = response; \ 2749 intel_sdvo_connector->name = \ 2750 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 2751 if (!intel_sdvo_connector->name) return false; \ 2752 drm_object_attach_property(&connector->base, \ 2753 intel_sdvo_connector->name, \ 2754 intel_sdvo_connector->cur_##name); \ 2755 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 2756 data_value[0], data_value[1], response); \ 2757 } \ 2758} while (0) 2759 2760static bool 2761intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 2762 struct intel_sdvo_connector *intel_sdvo_connector, 2763 struct intel_sdvo_enhancements_reply enhancements) 2764{ 2765 struct drm_device *dev = intel_sdvo->base.base.dev; 2766 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2767 uint16_t response, data_value[2]; 2768 2769 /* when horizontal overscan is supported, Add the left/right property */ 2770 if (enhancements.overscan_h) { 2771 if (!intel_sdvo_get_value(intel_sdvo, 2772 SDVO_CMD_GET_MAX_OVERSCAN_H, 2773 &data_value, 4)) 2774 return false; 2775 2776 if (!intel_sdvo_get_value(intel_sdvo, 2777 SDVO_CMD_GET_OVERSCAN_H, 2778 &response, 2)) 2779 return false; 2780 2781 intel_sdvo_connector->max_hscan = data_value[0]; 2782 intel_sdvo_connector->left_margin = data_value[0] - response; 2783 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; 2784 intel_sdvo_connector->left = 2785 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 2786 if (!intel_sdvo_connector->left) 2787 return false; 2788 2789 drm_object_attach_property(&connector->base, 2790 intel_sdvo_connector->left, 2791 intel_sdvo_connector->left_margin); 2792 2793 intel_sdvo_connector->right = 2794 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 2795 if (!intel_sdvo_connector->right) 2796 return false; 2797 2798 drm_object_attach_property(&connector->base, 2799 intel_sdvo_connector->right, 2800 intel_sdvo_connector->right_margin); 2801 DRM_DEBUG_KMS("h_overscan: max %d, " 2802 "default %d, current %d\n", 2803 data_value[0], data_value[1], response); 2804 } 2805 2806 if (enhancements.overscan_v) { 2807 if (!intel_sdvo_get_value(intel_sdvo, 2808 SDVO_CMD_GET_MAX_OVERSCAN_V, 2809 &data_value, 4)) 2810 return false; 2811 2812 if (!intel_sdvo_get_value(intel_sdvo, 2813 SDVO_CMD_GET_OVERSCAN_V, 2814 &response, 2)) 2815 return false; 2816 2817 intel_sdvo_connector->max_vscan = data_value[0]; 2818 intel_sdvo_connector->top_margin = data_value[0] - response; 2819 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; 2820 intel_sdvo_connector->top = 2821 drm_property_create_range(dev, 0, 2822 "top_margin", 0, data_value[0]); 2823 if (!intel_sdvo_connector->top) 2824 return false; 2825 2826 drm_object_attach_property(&connector->base, 2827 intel_sdvo_connector->top, 2828 intel_sdvo_connector->top_margin); 2829 2830 intel_sdvo_connector->bottom = 2831 drm_property_create_range(dev, 0, 2832 "bottom_margin", 0, data_value[0]); 2833 if (!intel_sdvo_connector->bottom) 2834 return false; 2835 2836 drm_object_attach_property(&connector->base, 2837 intel_sdvo_connector->bottom, 2838 intel_sdvo_connector->bottom_margin); 2839 DRM_DEBUG_KMS("v_overscan: max %d, " 2840 "default %d, current %d\n", 2841 data_value[0], data_value[1], response); 2842 } 2843 2844 ENHANCEMENT(hpos, HPOS); 2845 ENHANCEMENT(vpos, VPOS); 2846 ENHANCEMENT(saturation, SATURATION); 2847 ENHANCEMENT(contrast, CONTRAST); 2848 ENHANCEMENT(hue, HUE); 2849 ENHANCEMENT(sharpness, SHARPNESS); 2850 ENHANCEMENT(brightness, BRIGHTNESS); 2851 ENHANCEMENT(flicker_filter, FLICKER_FILTER); 2852 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 2853 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); 2854 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); 2855 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); 2856 2857 if (enhancements.dot_crawl) { 2858 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 2859 return false; 2860 2861 intel_sdvo_connector->max_dot_crawl = 1; 2862 intel_sdvo_connector->cur_dot_crawl = response & 0x1; 2863 intel_sdvo_connector->dot_crawl = 2864 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 2865 if (!intel_sdvo_connector->dot_crawl) 2866 return false; 2867 2868 drm_object_attach_property(&connector->base, 2869 intel_sdvo_connector->dot_crawl, 2870 intel_sdvo_connector->cur_dot_crawl); 2871 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 2872 } 2873 2874 return true; 2875} 2876 2877static bool 2878intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 2879 struct intel_sdvo_connector *intel_sdvo_connector, 2880 struct intel_sdvo_enhancements_reply enhancements) 2881{ 2882 struct drm_device *dev = intel_sdvo->base.base.dev; 2883 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2884 uint16_t response, data_value[2]; 2885 2886 ENHANCEMENT(brightness, BRIGHTNESS); 2887 2888 return true; 2889} 2890#undef ENHANCEMENT 2891 2892static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 2893 struct intel_sdvo_connector *intel_sdvo_connector) 2894{ 2895 union { 2896 struct intel_sdvo_enhancements_reply reply; 2897 uint16_t response; 2898 } enhancements; 2899 2900 BUILD_BUG_ON(sizeof(enhancements) != 2); 2901 2902 enhancements.response = 0; 2903 intel_sdvo_get_value(intel_sdvo, 2904 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2905 &enhancements, sizeof(enhancements)); 2906 if (enhancements.response == 0) { 2907 DRM_DEBUG_KMS("No enhancement is supported\n"); 2908 return true; 2909 } 2910 2911 if (IS_TV(intel_sdvo_connector)) 2912 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2913 else if (IS_LVDS(intel_sdvo_connector)) 2914 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2915 else 2916 return true; 2917} 2918 2919static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 2920 struct i2c_msg *msgs, 2921 int num) 2922{ 2923 struct intel_sdvo *sdvo = adapter->algo_data; 2924 2925 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 2926 return -EIO; 2927 2928 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 2929} 2930 2931static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 2932{ 2933 struct intel_sdvo *sdvo = adapter->algo_data; 2934 return sdvo->i2c->algo->functionality(sdvo->i2c); 2935} 2936 2937static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 2938 .master_xfer = intel_sdvo_ddc_proxy_xfer, 2939 .functionality = intel_sdvo_ddc_proxy_func 2940}; 2941 2942static bool 2943intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, 2944 struct drm_device *dev) 2945{ 2946 sdvo->ddc.owner = THIS_MODULE; 2947 sdvo->ddc.class = I2C_CLASS_DDC; 2948 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); 2949 sdvo->ddc.dev.parent = &dev->pdev->dev; 2950 sdvo->ddc.algo_data = sdvo; 2951 sdvo->ddc.algo = &intel_sdvo_ddc_proxy; 2952 2953 return i2c_add_adapter(&sdvo->ddc) == 0; 2954} 2955 2956bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) 2957{ 2958 struct drm_i915_private *dev_priv = dev->dev_private; 2959 struct intel_encoder *intel_encoder; 2960 struct intel_sdvo *intel_sdvo; 2961 int i; 2962 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 2963 if (!intel_sdvo) 2964 return false; 2965 2966 intel_sdvo->sdvo_reg = sdvo_reg; 2967 intel_sdvo->is_sdvob = is_sdvob; 2968 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; 2969 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); 2970 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) 2971 goto err_i2c_bus; 2972 2973 /* encoder type will be decided later */ 2974 intel_encoder = &intel_sdvo->base; 2975 intel_encoder->type = INTEL_OUTPUT_SDVO; 2976 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); 2977 2978 /* Read the regs to test if we can talk to the device */ 2979 for (i = 0; i < 0x40; i++) { 2980 u8 byte; 2981 2982 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 2983 DRM_DEBUG_KMS("No SDVO device found on %s\n", 2984 SDVO_NAME(intel_sdvo)); 2985 goto err; 2986 } 2987 } 2988 2989 intel_encoder->compute_config = intel_sdvo_compute_config; 2990 intel_encoder->disable = intel_disable_sdvo; 2991 intel_encoder->pre_enable = intel_sdvo_pre_enable; 2992 intel_encoder->enable = intel_enable_sdvo; 2993 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 2994 intel_encoder->get_config = intel_sdvo_get_config; 2995 2996 /* In default case sdvo lvds is false */ 2997 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 2998 goto err; 2999 3000 if (intel_sdvo_output_setup(intel_sdvo, 3001 intel_sdvo->caps.output_flags) != true) { 3002 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", 3003 SDVO_NAME(intel_sdvo)); 3004 /* Output_setup can leave behind connectors! */ 3005 goto err_output; 3006 } 3007 3008 /* Only enable the hotplug irq if we need it, to work around noisy 3009 * hotplug lines. 3010 */ 3011 if (intel_sdvo->hotplug_active) { 3012 intel_encoder->hpd_pin = 3013 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C; 3014 } 3015 3016 /* 3017 * Cloning SDVO with anything is often impossible, since the SDVO 3018 * encoder can request a special input timing mode. And even if that's 3019 * not the case we have evidence that cloning a plain unscaled mode with 3020 * VGA doesn't really work. Furthermore the cloning flags are way too 3021 * simplistic anyway to express such constraints, so just give up on 3022 * cloning for SDVO encoders. 3023 */ 3024 intel_sdvo->base.cloneable = 0; 3025 3026 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); 3027 3028 /* Set the input timing to the screen. Assume always input 0. */ 3029 if (!intel_sdvo_set_target_input(intel_sdvo)) 3030 goto err_output; 3031 3032 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3033 &intel_sdvo->pixel_clock_min, 3034 &intel_sdvo->pixel_clock_max)) 3035 goto err_output; 3036 3037 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 3038 "clock range %dMHz - %dMHz, " 3039 "input 1: %c, input 2: %c, " 3040 "output 1: %c, output 2: %c\n", 3041 SDVO_NAME(intel_sdvo), 3042 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3043 intel_sdvo->caps.device_rev_id, 3044 intel_sdvo->pixel_clock_min / 1000, 3045 intel_sdvo->pixel_clock_max / 1000, 3046 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3047 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3048 /* check currently supported outputs */ 3049 intel_sdvo->caps.output_flags & 3050 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 3051 intel_sdvo->caps.output_flags & 3052 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 3053 return true; 3054 3055err_output: 3056 intel_sdvo_output_cleanup(intel_sdvo); 3057 3058err: 3059 drm_encoder_cleanup(&intel_encoder->base); 3060 i2c_del_adapter(&intel_sdvo->ddc); 3061err_i2c_bus: 3062 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3063 kfree(intel_sdvo); 3064 3065 return false; 3066} 3067