1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "priv.h"
25
26#include <core/client.h>
27#include <core/gpuobj.h>
28#include <subdev/fb.h>
29
30#include <nvif/class.h>
31#include <nvif/unpack.h>
32
33struct gf110_dmaobj_priv {
34	struct nvkm_dmaobj base;
35	u32 flags0;
36};
37
38static int
39gf110_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
40		  struct nvkm_gpuobj **pgpuobj)
41{
42	struct gf110_dmaobj_priv *priv = (void *)dmaobj;
43	int ret;
44
45	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
46		switch (nv_mclass(parent->parent)) {
47		case GF110_DISP_CORE_CHANNEL_DMA:
48		case GK104_DISP_CORE_CHANNEL_DMA:
49		case GK110_DISP_CORE_CHANNEL_DMA:
50		case GM107_DISP_CORE_CHANNEL_DMA:
51		case GM204_DISP_CORE_CHANNEL_DMA:
52		case GF110_DISP_BASE_CHANNEL_DMA:
53		case GK104_DISP_BASE_CHANNEL_DMA:
54		case GK110_DISP_BASE_CHANNEL_DMA:
55		case GF110_DISP_OVERLAY_CONTROL_DMA:
56		case GK104_DISP_OVERLAY_CONTROL_DMA:
57			break;
58		default:
59			return -EINVAL;
60		}
61	} else
62		return 0;
63
64	ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
65	if (ret == 0) {
66		nv_wo32(*pgpuobj, 0x00, priv->flags0);
67		nv_wo32(*pgpuobj, 0x04, priv->base.start >> 8);
68		nv_wo32(*pgpuobj, 0x08, priv->base.limit >> 8);
69		nv_wo32(*pgpuobj, 0x0c, 0x00000000);
70		nv_wo32(*pgpuobj, 0x10, 0x00000000);
71		nv_wo32(*pgpuobj, 0x14, 0x00000000);
72	}
73
74	return ret;
75}
76
77static int
78gf110_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
79		  struct nvkm_oclass *oclass, void *data, u32 size,
80		  struct nvkm_object **pobject)
81{
82	struct nvkm_dmaeng *dmaeng = (void *)engine;
83	union {
84		struct gf110_dma_v0 v0;
85	} *args;
86	struct gf110_dmaobj_priv *priv;
87	u32 kind, page;
88	int ret;
89
90	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
91	*pobject = nv_object(priv);
92	if (ret)
93		return ret;
94	args = data;
95
96	nv_ioctl(parent, "create gf110 dma size %d\n", size);
97	if (nvif_unpack(args->v0, 0, 0, false)) {
98		nv_ioctl(parent, "create gf100 dma vers %d page %d kind %02x\n",
99			 args->v0.version, args->v0.page, args->v0.kind);
100		kind = args->v0.kind;
101		page = args->v0.page;
102	} else
103	if (size == 0) {
104		if (priv->base.target != NV_MEM_TARGET_VM) {
105			kind = GF110_DMA_V0_KIND_PITCH;
106			page = GF110_DMA_V0_PAGE_SP;
107		} else {
108			kind = GF110_DMA_V0_KIND_VM;
109			page = GF110_DMA_V0_PAGE_LP;
110		}
111	} else
112		return ret;
113
114	if (page > 1)
115		return -EINVAL;
116	priv->flags0 = (kind << 20) | (page << 6);
117
118	switch (priv->base.target) {
119	case NV_MEM_TARGET_VRAM:
120		priv->flags0 |= 0x00000009;
121		break;
122	case NV_MEM_TARGET_VM:
123	case NV_MEM_TARGET_PCI:
124	case NV_MEM_TARGET_PCI_NOSNOOP:
125		/* XXX: don't currently know how to construct a real one
126		 *      of these.  we only use them to represent pushbufs
127		 *      on these chipsets, and the classes that use them
128		 *      deal with the target themselves.
129		 */
130		break;
131	default:
132		return -EINVAL;
133	}
134
135	return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
136}
137
138static struct nvkm_ofuncs
139gf110_dmaobj_ofuncs = {
140	.ctor =  gf110_dmaobj_ctor,
141	.dtor = _nvkm_dmaobj_dtor,
142	.init = _nvkm_dmaobj_init,
143	.fini = _nvkm_dmaobj_fini,
144};
145
146static struct nvkm_oclass
147gf110_dmaeng_sclass[] = {
148	{ NV_DMA_FROM_MEMORY, &gf110_dmaobj_ofuncs },
149	{ NV_DMA_TO_MEMORY, &gf110_dmaobj_ofuncs },
150	{ NV_DMA_IN_MEMORY, &gf110_dmaobj_ofuncs },
151	{}
152};
153
154struct nvkm_oclass *
155gf110_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
156	.base.handle = NV_ENGINE(DMAOBJ, 0xd0),
157	.base.ofuncs = &(struct nvkm_ofuncs) {
158		.ctor = _nvkm_dmaeng_ctor,
159		.dtor = _nvkm_dmaeng_dtor,
160		.init = _nvkm_dmaeng_init,
161		.fini = _nvkm_dmaeng_fini,
162	},
163	.sclass = gf110_dmaeng_sclass,
164	.bind = gf110_dmaobj_bind,
165}.base;
166