1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "priv.h"
25
26#include <core/device.h>
27#include <core/gpuobj.h>
28#include <subdev/fb.h>
29#include <subdev/mmu.h>
30
31struct gf100_bar_priv_vm {
32	struct nvkm_gpuobj *mem;
33	struct nvkm_gpuobj *pgd;
34	struct nvkm_vm *vm;
35};
36
37struct gf100_bar_priv {
38	struct nvkm_bar base;
39	spinlock_t lock;
40	struct gf100_bar_priv_vm bar[2];
41};
42
43static int
44gf100_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags,
45	       struct nvkm_vma *vma)
46{
47	struct gf100_bar_priv *priv = (void *)bar;
48	int ret;
49
50	ret = nvkm_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma);
51	if (ret)
52		return ret;
53
54	nvkm_vm_map(vma, mem);
55	return 0;
56}
57
58static int
59gf100_bar_umap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags,
60	       struct nvkm_vma *vma)
61{
62	struct gf100_bar_priv *priv = (void *)bar;
63	int ret;
64
65	ret = nvkm_vm_get(priv->bar[1].vm, mem->size << 12,
66			  mem->page_shift, flags, vma);
67	if (ret)
68		return ret;
69
70	nvkm_vm_map(vma, mem);
71	return 0;
72}
73
74static void
75gf100_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma)
76{
77	nvkm_vm_unmap(vma);
78	nvkm_vm_put(vma);
79}
80
81static int
82gf100_bar_ctor_vm(struct gf100_bar_priv *priv, struct gf100_bar_priv_vm *bar_vm,
83		  int bar_nr)
84{
85	struct nvkm_device *device = nv_device(&priv->base);
86	struct nvkm_vm *vm;
87	resource_size_t bar_len;
88	int ret;
89
90	ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
91			      &bar_vm->mem);
92	if (ret)
93		return ret;
94
95	ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
96			      &bar_vm->pgd);
97	if (ret)
98		return ret;
99
100	bar_len = nv_device_resource_len(device, bar_nr);
101
102	ret = nvkm_vm_new(device, 0, bar_len, 0, &vm);
103	if (ret)
104		return ret;
105
106	atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
107
108	/*
109	 * Bootstrap page table lookup.
110	 */
111	if (bar_nr == 3) {
112		ret = nvkm_gpuobj_new(nv_object(priv), NULL,
113				      (bar_len >> 12) * 8, 0x1000,
114				      NVOBJ_FLAG_ZERO_ALLOC,
115				      &vm->pgt[0].obj[0]);
116		vm->pgt[0].refcount[0] = 1;
117		if (ret)
118			return ret;
119	}
120
121	ret = nvkm_vm_ref(vm, &bar_vm->vm, bar_vm->pgd);
122	nvkm_vm_ref(NULL, &vm, NULL);
123	if (ret)
124		return ret;
125
126	nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr));
127	nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr));
128	nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1));
129	nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1));
130	return 0;
131}
132
133int
134gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
135	       struct nvkm_oclass *oclass, void *data, u32 size,
136	       struct nvkm_object **pobject)
137{
138	struct nvkm_device *device = nv_device(parent);
139	struct gf100_bar_priv *priv;
140	bool has_bar3 = nv_device_resource_len(device, 3) != 0;
141	int ret;
142
143	ret = nvkm_bar_create(parent, engine, oclass, &priv);
144	*pobject = nv_object(priv);
145	if (ret)
146		return ret;
147
148	/* BAR3 */
149	if (has_bar3) {
150		ret = gf100_bar_ctor_vm(priv, &priv->bar[0], 3);
151		if (ret)
152			return ret;
153	}
154
155	/* BAR1 */
156	ret = gf100_bar_ctor_vm(priv, &priv->bar[1], 1);
157	if (ret)
158		return ret;
159
160	if (has_bar3) {
161		priv->base.alloc = nvkm_bar_alloc;
162		priv->base.kmap = gf100_bar_kmap;
163	}
164	priv->base.umap = gf100_bar_umap;
165	priv->base.unmap = gf100_bar_unmap;
166	priv->base.flush = g84_bar_flush;
167	spin_lock_init(&priv->lock);
168	return 0;
169}
170
171void
172gf100_bar_dtor(struct nvkm_object *object)
173{
174	struct gf100_bar_priv *priv = (void *)object;
175
176	nvkm_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd);
177	nvkm_gpuobj_ref(NULL, &priv->bar[1].pgd);
178	nvkm_gpuobj_ref(NULL, &priv->bar[1].mem);
179
180	if (priv->bar[0].vm) {
181		nvkm_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]);
182		nvkm_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd);
183	}
184	nvkm_gpuobj_ref(NULL, &priv->bar[0].pgd);
185	nvkm_gpuobj_ref(NULL, &priv->bar[0].mem);
186
187	nvkm_bar_destroy(&priv->base);
188}
189
190int
191gf100_bar_init(struct nvkm_object *object)
192{
193	struct gf100_bar_priv *priv = (void *)object;
194	int ret;
195
196	ret = nvkm_bar_init(&priv->base);
197	if (ret)
198		return ret;
199
200	nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
201	nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
202
203	nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12);
204	if (priv->bar[0].mem)
205		nv_wr32(priv, 0x001714,
206			0xc0000000 | priv->bar[0].mem->addr >> 12);
207	return 0;
208}
209
210struct nvkm_oclass
211gf100_bar_oclass = {
212	.handle = NV_SUBDEV(BAR, 0xc0),
213	.ofuncs = &(struct nvkm_ofuncs) {
214		.ctor = gf100_bar_ctor,
215		.dtor = gf100_bar_dtor,
216		.init = gf100_bar_init,
217		.fini = _nvkm_bar_fini,
218	},
219};
220