1/* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24#include <subdev/bios.h> 25#include <subdev/bios/bit.h> 26#include <subdev/bios/timing.h> 27 28u16 29nvbios_timingTe(struct nvkm_bios *bios, 30 u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) 31{ 32 struct bit_entry bit_P; 33 u16 timing = 0x0000; 34 35 if (!bit_entry(bios, 'P', &bit_P)) { 36 if (bit_P.version == 1) 37 timing = nv_ro16(bios, bit_P.offset + 4); 38 else 39 if (bit_P.version == 2) 40 timing = nv_ro16(bios, bit_P.offset + 8); 41 42 if (timing) { 43 *ver = nv_ro08(bios, timing + 0); 44 switch (*ver) { 45 case 0x10: 46 *hdr = nv_ro08(bios, timing + 1); 47 *cnt = nv_ro08(bios, timing + 2); 48 *len = nv_ro08(bios, timing + 3); 49 *snr = 0; 50 *ssz = 0; 51 return timing; 52 case 0x20: 53 *hdr = nv_ro08(bios, timing + 1); 54 *cnt = nv_ro08(bios, timing + 5); 55 *len = nv_ro08(bios, timing + 2); 56 *snr = nv_ro08(bios, timing + 4); 57 *ssz = nv_ro08(bios, timing + 3); 58 return timing; 59 default: 60 break; 61 } 62 } 63 } 64 65 return 0x0000; 66} 67 68u16 69nvbios_timingEe(struct nvkm_bios *bios, int idx, 70 u8 *ver, u8 *hdr, u8 *cnt, u8 *len) 71{ 72 u8 snr, ssz; 73 u16 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); 74 if (timing && idx < *cnt) { 75 timing += *hdr + idx * (*len + (snr * ssz)); 76 *hdr = *len; 77 *cnt = snr; 78 *len = ssz; 79 return timing; 80 } 81 return 0x0000; 82} 83 84u16 85nvbios_timingEp(struct nvkm_bios *bios, int idx, 86 u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p) 87{ 88 u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp; 89 p->timing_ver = *ver; 90 p->timing_hdr = *hdr; 91 switch (!!data * *ver) { 92 case 0x10: 93 p->timing_10_WR = nv_ro08(bios, data + 0x00); 94 p->timing_10_WTR = nv_ro08(bios, data + 0x01); 95 p->timing_10_CL = nv_ro08(bios, data + 0x02); 96 p->timing_10_RC = nv_ro08(bios, data + 0x03); 97 p->timing_10_RFC = nv_ro08(bios, data + 0x05); 98 p->timing_10_RAS = nv_ro08(bios, data + 0x07); 99 p->timing_10_RP = nv_ro08(bios, data + 0x09); 100 p->timing_10_RCDRD = nv_ro08(bios, data + 0x0a); 101 p->timing_10_RCDWR = nv_ro08(bios, data + 0x0b); 102 p->timing_10_RRD = nv_ro08(bios, data + 0x0c); 103 p->timing_10_13 = nv_ro08(bios, data + 0x0d); 104 p->timing_10_ODT = nv_ro08(bios, data + 0x0e) & 0x07; 105 106 p->timing_10_24 = 0xff; 107 p->timing_10_21 = 0; 108 p->timing_10_20 = 0; 109 p->timing_10_CWL = 0; 110 p->timing_10_18 = 0; 111 p->timing_10_16 = 0; 112 113 switch (min_t(u8, *hdr, 25)) { 114 case 25: 115 p->timing_10_24 = nv_ro08(bios, data + 0x18); 116 case 24: 117 case 23: 118 case 22: 119 p->timing_10_21 = nv_ro08(bios, data + 0x15); 120 case 21: 121 p->timing_10_20 = nv_ro08(bios, data + 0x14); 122 case 20: 123 p->timing_10_CWL = nv_ro08(bios, data + 0x13); 124 case 19: 125 p->timing_10_18 = nv_ro08(bios, data + 0x12); 126 case 18: 127 case 17: 128 p->timing_10_16 = nv_ro08(bios, data + 0x10); 129 } 130 131 break; 132 case 0x20: 133 p->timing[0] = nv_ro32(bios, data + 0x00); 134 p->timing[1] = nv_ro32(bios, data + 0x04); 135 p->timing[2] = nv_ro32(bios, data + 0x08); 136 p->timing[3] = nv_ro32(bios, data + 0x0c); 137 p->timing[4] = nv_ro32(bios, data + 0x10); 138 p->timing[5] = nv_ro32(bios, data + 0x14); 139 p->timing[6] = nv_ro32(bios, data + 0x18); 140 p->timing[7] = nv_ro32(bios, data + 0x1c); 141 p->timing[8] = nv_ro32(bios, data + 0x20); 142 p->timing[9] = nv_ro32(bios, data + 0x24); 143 p->timing[10] = nv_ro32(bios, data + 0x28); 144 p->timing_20_2e_03 = (nv_ro08(bios, data + 0x2e) & 0x03) >> 0; 145 p->timing_20_2e_30 = (nv_ro08(bios, data + 0x2e) & 0x30) >> 4; 146 p->timing_20_2e_c0 = (nv_ro08(bios, data + 0x2e) & 0xc0) >> 6; 147 p->timing_20_2f_03 = (nv_ro08(bios, data + 0x2f) & 0x03) >> 0; 148 temp = nv_ro16(bios, data + 0x2c); 149 p->timing_20_2c_003f = (temp & 0x003f) >> 0; 150 p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6; 151 p->timing_20_30_07 = (nv_ro08(bios, data + 0x30) & 0x07) >> 0; 152 p->timing_20_30_f8 = (nv_ro08(bios, data + 0x30) & 0xf8) >> 3; 153 temp = nv_ro16(bios, data + 0x31); 154 p->timing_20_31_0007 = (temp & 0x0007) >> 0; 155 p->timing_20_31_0078 = (temp & 0x0078) >> 3; 156 p->timing_20_31_0780 = (temp & 0x0780) >> 7; 157 p->timing_20_31_0800 = (temp & 0x0800) >> 11; 158 p->timing_20_31_7000 = (temp & 0x7000) >> 12; 159 p->timing_20_31_8000 = (temp & 0x8000) >> 15; 160 break; 161 default: 162 data = 0; 163 break; 164 } 165 return data; 166} 167