1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "nv50.h"
25
26#include <core/client.h>
27#include <core/device.h>
28#include <core/engctx.h>
29#include <core/enum.h>
30
31int
32nv50_fb_memtype[0x80] = {
33	1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
34	1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0,
35	1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0,
36	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
37	1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0,
38	0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
39	1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2,
40	1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0
41};
42
43bool
44nv50_fb_memtype_valid(struct nvkm_fb *pfb, u32 memtype)
45{
46	return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0;
47}
48
49static const struct nvkm_enum vm_dispatch_subclients[] = {
50	{ 0x00000000, "GRCTX", NULL },
51	{ 0x00000001, "NOTIFY", NULL },
52	{ 0x00000002, "QUERY", NULL },
53	{ 0x00000003, "COND", NULL },
54	{ 0x00000004, "M2M_IN", NULL },
55	{ 0x00000005, "M2M_OUT", NULL },
56	{ 0x00000006, "M2M_NOTIFY", NULL },
57	{}
58};
59
60static const struct nvkm_enum vm_ccache_subclients[] = {
61	{ 0x00000000, "CB", NULL },
62	{ 0x00000001, "TIC", NULL },
63	{ 0x00000002, "TSC", NULL },
64	{}
65};
66
67static const struct nvkm_enum vm_prop_subclients[] = {
68	{ 0x00000000, "RT0", NULL },
69	{ 0x00000001, "RT1", NULL },
70	{ 0x00000002, "RT2", NULL },
71	{ 0x00000003, "RT3", NULL },
72	{ 0x00000004, "RT4", NULL },
73	{ 0x00000005, "RT5", NULL },
74	{ 0x00000006, "RT6", NULL },
75	{ 0x00000007, "RT7", NULL },
76	{ 0x00000008, "ZETA", NULL },
77	{ 0x00000009, "LOCAL", NULL },
78	{ 0x0000000a, "GLOBAL", NULL },
79	{ 0x0000000b, "STACK", NULL },
80	{ 0x0000000c, "DST2D", NULL },
81	{}
82};
83
84static const struct nvkm_enum vm_pfifo_subclients[] = {
85	{ 0x00000000, "PUSHBUF", NULL },
86	{ 0x00000001, "SEMAPHORE", NULL },
87	{}
88};
89
90static const struct nvkm_enum vm_bar_subclients[] = {
91	{ 0x00000000, "FB", NULL },
92	{ 0x00000001, "IN", NULL },
93	{}
94};
95
96static const struct nvkm_enum vm_client[] = {
97	{ 0x00000000, "STRMOUT", NULL },
98	{ 0x00000003, "DISPATCH", vm_dispatch_subclients },
99	{ 0x00000004, "PFIFO_WRITE", NULL },
100	{ 0x00000005, "CCACHE", vm_ccache_subclients },
101	{ 0x00000006, "PMSPPP", NULL },
102	{ 0x00000007, "CLIPID", NULL },
103	{ 0x00000008, "PFIFO_READ", NULL },
104	{ 0x00000009, "VFETCH", NULL },
105	{ 0x0000000a, "TEXTURE", NULL },
106	{ 0x0000000b, "PROP", vm_prop_subclients },
107	{ 0x0000000c, "PVP", NULL },
108	{ 0x0000000d, "PBSP", NULL },
109	{ 0x0000000e, "PCRYPT", NULL },
110	{ 0x0000000f, "PCOUNTER", NULL },
111	{ 0x00000011, "PDAEMON", NULL },
112	{}
113};
114
115static const struct nvkm_enum vm_engine[] = {
116	{ 0x00000000, "PGRAPH", NULL, NVDEV_ENGINE_GR },
117	{ 0x00000001, "PVP", NULL, NVDEV_ENGINE_VP },
118	{ 0x00000004, "PEEPHOLE", NULL },
119	{ 0x00000005, "PFIFO", vm_pfifo_subclients, NVDEV_ENGINE_FIFO },
120	{ 0x00000006, "BAR", vm_bar_subclients },
121	{ 0x00000008, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
122	{ 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG },
123	{ 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP },
124	{ 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CIPHER },
125	{ 0x0000000b, "PCOUNTER", NULL },
126	{ 0x0000000c, "SEMAPHORE_BG", NULL },
127	{ 0x0000000d, "PCE0", NULL, NVDEV_ENGINE_CE0 },
128	{ 0x0000000e, "PDAEMON", NULL },
129	{}
130};
131
132static const struct nvkm_enum vm_fault[] = {
133	{ 0x00000000, "PT_NOT_PRESENT", NULL },
134	{ 0x00000001, "PT_TOO_SHORT", NULL },
135	{ 0x00000002, "PAGE_NOT_PRESENT", NULL },
136	{ 0x00000003, "PAGE_SYSTEM_ONLY", NULL },
137	{ 0x00000004, "PAGE_READ_ONLY", NULL },
138	{ 0x00000006, "NULL_DMAOBJ", NULL },
139	{ 0x00000007, "WRONG_MEMTYPE", NULL },
140	{ 0x0000000b, "VRAM_LIMIT", NULL },
141	{ 0x0000000f, "DMAOBJ_LIMIT", NULL },
142	{}
143};
144
145static void
146nv50_fb_intr(struct nvkm_subdev *subdev)
147{
148	struct nvkm_device *device = nv_device(subdev);
149	struct nvkm_engine *engine;
150	struct nv50_fb_priv *priv = (void *)subdev;
151	const struct nvkm_enum *en, *cl;
152	struct nvkm_object *engctx = NULL;
153	u32 trap[6], idx, chan;
154	u8 st0, st1, st2, st3;
155	int i;
156
157	idx = nv_rd32(priv, 0x100c90);
158	if (!(idx & 0x80000000))
159		return;
160	idx &= 0x00ffffff;
161
162	for (i = 0; i < 6; i++) {
163		nv_wr32(priv, 0x100c90, idx | i << 24);
164		trap[i] = nv_rd32(priv, 0x100c94);
165	}
166	nv_wr32(priv, 0x100c90, idx | 0x80000000);
167
168	/* decode status bits into something more useful */
169	if (device->chipset  < 0xa3 ||
170	    device->chipset == 0xaa || device->chipset == 0xac) {
171		st0 = (trap[0] & 0x0000000f) >> 0;
172		st1 = (trap[0] & 0x000000f0) >> 4;
173		st2 = (trap[0] & 0x00000f00) >> 8;
174		st3 = (trap[0] & 0x0000f000) >> 12;
175	} else {
176		st0 = (trap[0] & 0x000000ff) >> 0;
177		st1 = (trap[0] & 0x0000ff00) >> 8;
178		st2 = (trap[0] & 0x00ff0000) >> 16;
179		st3 = (trap[0] & 0xff000000) >> 24;
180	}
181	chan = (trap[2] << 16) | trap[1];
182
183	en = nvkm_enum_find(vm_engine, st0);
184
185	if (en && en->data2) {
186		const struct nvkm_enum *orig_en = en;
187		while (en->name && en->value == st0 && en->data2) {
188			engine = nvkm_engine(subdev, en->data2);
189			/*XXX: clean this up */
190			if (!engine && en->data2 == NVDEV_ENGINE_BSP)
191				engine = nvkm_engine(subdev, NVDEV_ENGINE_MSVLD);
192			if (!engine && en->data2 == NVDEV_ENGINE_CIPHER)
193				engine = nvkm_engine(subdev, NVDEV_ENGINE_SEC);
194			if (!engine && en->data2 == NVDEV_ENGINE_VP)
195				engine = nvkm_engine(subdev, NVDEV_ENGINE_MSPDEC);
196			if (engine) {
197				engctx = nvkm_engctx_get(engine, chan);
198				if (engctx)
199					break;
200			}
201			en++;
202		}
203		if (!engctx)
204			en = orig_en;
205	}
206
207	nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ",
208		 (trap[5] & 0x00000100) ? "read" : "write",
209		 trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan,
210		 nvkm_client_name(engctx));
211
212	nvkm_engctx_put(engctx);
213
214	if (en)
215		pr_cont("%s/", en->name);
216	else
217		pr_cont("%02x/", st0);
218
219	cl = nvkm_enum_find(vm_client, st2);
220	if (cl)
221		pr_cont("%s/", cl->name);
222	else
223		pr_cont("%02x/", st2);
224
225	if      (cl && cl->data) cl = nvkm_enum_find(cl->data, st3);
226	else if (en && en->data) cl = nvkm_enum_find(en->data, st3);
227	else                     cl = NULL;
228	if (cl)
229		pr_cont("%s", cl->name);
230	else
231		pr_cont("%02x", st3);
232
233	pr_cont(" reason: ");
234	en = nvkm_enum_find(vm_fault, st1);
235	if (en)
236		pr_cont("%s\n", en->name);
237	else
238		pr_cont("0x%08x\n", st1);
239}
240
241int
242nv50_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
243	     struct nvkm_oclass *oclass, void *data, u32 size,
244	     struct nvkm_object **pobject)
245{
246	struct nvkm_device *device = nv_device(parent);
247	struct nv50_fb_priv *priv;
248	int ret;
249
250	ret = nvkm_fb_create(parent, engine, oclass, &priv);
251	*pobject = nv_object(priv);
252	if (ret)
253		return ret;
254
255	priv->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
256	if (priv->r100c08_page) {
257		priv->r100c08 = dma_map_page(nv_device_base(device),
258					     priv->r100c08_page, 0, PAGE_SIZE,
259					     DMA_BIDIRECTIONAL);
260		if (dma_mapping_error(nv_device_base(device), priv->r100c08))
261			return -EFAULT;
262	} else {
263		nv_warn(priv, "failed 0x100c08 page alloc\n");
264	}
265
266	nv_subdev(priv)->intr = nv50_fb_intr;
267	return 0;
268}
269
270void
271nv50_fb_dtor(struct nvkm_object *object)
272{
273	struct nvkm_device *device = nv_device(object);
274	struct nv50_fb_priv *priv = (void *)object;
275
276	if (priv->r100c08_page) {
277		dma_unmap_page(nv_device_base(device), priv->r100c08, PAGE_SIZE,
278			       DMA_BIDIRECTIONAL);
279		__free_page(priv->r100c08_page);
280	}
281
282	nvkm_fb_destroy(&priv->base);
283}
284
285int
286nv50_fb_init(struct nvkm_object *object)
287{
288	struct nv50_fb_impl *impl = (void *)object->oclass;
289	struct nv50_fb_priv *priv = (void *)object;
290	int ret;
291
292	ret = nvkm_fb_init(&priv->base);
293	if (ret)
294		return ret;
295
296	/* Not a clue what this is exactly.  Without pointing it at a
297	 * scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
298	 * cause IOMMU "read from address 0" errors (rh#561267)
299	 */
300	nv_wr32(priv, 0x100c08, priv->r100c08 >> 8);
301
302	/* This is needed to get meaningful information from 100c90
303	 * on traps. No idea what these values mean exactly. */
304	nv_wr32(priv, 0x100c90, impl->trap);
305	return 0;
306}
307
308struct nvkm_oclass *
309nv50_fb_oclass = &(struct nv50_fb_impl) {
310	.base.base.handle = NV_SUBDEV(FB, 0x50),
311	.base.base.ofuncs = &(struct nvkm_ofuncs) {
312		.ctor = nv50_fb_ctor,
313		.dtor = nv50_fb_dtor,
314		.init = nv50_fb_init,
315		.fini = _nvkm_fb_fini,
316	},
317	.base.memtype = nv50_fb_memtype_valid,
318	.base.ram = &nv50_ram_oclass,
319	.trap = 0x000707ff,
320}.base.base;
321