1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include <subdev/mmu.h>
25#include <subdev/bar.h>
26#include <subdev/fb.h>
27#include <subdev/timer.h>
28
29#include <core/engine.h>
30#include <core/gpuobj.h>
31
32struct nv50_mmu_priv {
33	struct nvkm_mmu base;
34};
35
36static void
37nv50_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 pde, struct nvkm_gpuobj *pgt[2])
38{
39	u64 phys = 0xdeadcafe00000000ULL;
40	u32 coverage = 0;
41
42	if (pgt[0]) {
43		phys = 0x00000003 | pgt[0]->addr; /* present, 4KiB pages */
44		coverage = (pgt[0]->size >> 3) << 12;
45	} else
46	if (pgt[1]) {
47		phys = 0x00000001 | pgt[1]->addr; /* present */
48		coverage = (pgt[1]->size >> 3) << 16;
49	}
50
51	if (phys & 1) {
52		if (coverage <= 32 * 1024 * 1024)
53			phys |= 0x60;
54		else if (coverage <= 64 * 1024 * 1024)
55			phys |= 0x40;
56		else if (coverage <= 128 * 1024 * 1024)
57			phys |= 0x20;
58	}
59
60	nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys));
61	nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys));
62}
63
64static inline u64
65vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target)
66{
67	phys |= 1; /* present */
68	phys |= (u64)memtype << 40;
69	phys |= target << 4;
70	if (vma->access & NV_MEM_ACCESS_SYS)
71		phys |= (1 << 6);
72	if (!(vma->access & NV_MEM_ACCESS_WO))
73		phys |= (1 << 3);
74	return phys;
75}
76
77static void
78nv50_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
79	    struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
80{
81	u32 comp = (mem->memtype & 0x180) >> 7;
82	u32 block, target;
83	int i;
84
85	/* IGPs don't have real VRAM, re-target to stolen system memory */
86	target = 0;
87	if (nvkm_fb(vma->vm->mmu)->ram->stolen) {
88		phys += nvkm_fb(vma->vm->mmu)->ram->stolen;
89		target = 3;
90	}
91
92	phys  = vm_addr(vma, phys, mem->memtype, target);
93	pte <<= 3;
94	cnt <<= 3;
95
96	while (cnt) {
97		u32 offset_h = upper_32_bits(phys);
98		u32 offset_l = lower_32_bits(phys);
99
100		for (i = 7; i >= 0; i--) {
101			block = 1 << (i + 3);
102			if (cnt >= block && !(pte & (block - 1)))
103				break;
104		}
105		offset_l |= (i << 7);
106
107		phys += block << (vma->node->type - 3);
108		cnt  -= block;
109		if (comp) {
110			u32 tag = mem->tag->offset + ((delta >> 16) * comp);
111			offset_h |= (tag << 17);
112			delta    += block << (vma->node->type - 3);
113		}
114
115		while (block) {
116			nv_wo32(pgt, pte + 0, offset_l);
117			nv_wo32(pgt, pte + 4, offset_h);
118			pte += 8;
119			block -= 8;
120		}
121	}
122}
123
124static void
125nv50_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
126	       struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
127{
128	u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2;
129	pte <<= 3;
130	while (cnt--) {
131		u64 phys = vm_addr(vma, (u64)*list++, mem->memtype, target);
132		nv_wo32(pgt, pte + 0, lower_32_bits(phys));
133		nv_wo32(pgt, pte + 4, upper_32_bits(phys));
134		pte += 8;
135	}
136}
137
138static void
139nv50_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
140{
141	pte <<= 3;
142	while (cnt--) {
143		nv_wo32(pgt, pte + 0, 0x00000000);
144		nv_wo32(pgt, pte + 4, 0x00000000);
145		pte += 8;
146	}
147}
148
149static void
150nv50_vm_flush(struct nvkm_vm *vm)
151{
152	struct nv50_mmu_priv *priv = (void *)vm->mmu;
153	struct nvkm_bar *bar = nvkm_bar(priv);
154	struct nvkm_engine *engine;
155	int i, vme;
156
157	bar->flush(bar);
158
159	mutex_lock(&nv_subdev(priv)->mutex);
160	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
161		if (!atomic_read(&vm->engref[i]))
162			continue;
163
164		/* unfortunate hw bug workaround... */
165		engine = nvkm_engine(priv, i);
166		if (engine && engine->tlb_flush) {
167			engine->tlb_flush(engine);
168			continue;
169		}
170
171		switch (i) {
172		case NVDEV_ENGINE_GR    : vme = 0x00; break;
173		case NVDEV_ENGINE_VP    :
174		case NVDEV_ENGINE_MSPDEC: vme = 0x01; break;
175		case NVDEV_SUBDEV_BAR   : vme = 0x06; break;
176		case NVDEV_ENGINE_MSPPP :
177		case NVDEV_ENGINE_MPEG  : vme = 0x08; break;
178		case NVDEV_ENGINE_BSP   :
179		case NVDEV_ENGINE_MSVLD : vme = 0x09; break;
180		case NVDEV_ENGINE_CIPHER:
181		case NVDEV_ENGINE_SEC   : vme = 0x0a; break;
182		case NVDEV_ENGINE_CE0   : vme = 0x0d; break;
183		default:
184			continue;
185		}
186
187		nv_wr32(priv, 0x100c80, (vme << 16) | 1);
188		if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
189			nv_error(priv, "vm flush timeout: engine %d\n", vme);
190	}
191	mutex_unlock(&nv_subdev(priv)->mutex);
192}
193
194static int
195nv50_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length,
196	       u64 mm_offset, struct nvkm_vm **pvm)
197{
198	u32 block = (1 << (mmu->pgt_bits + 12));
199	if (block > length)
200		block = length;
201
202	return nvkm_vm_create(mmu, offset, length, mm_offset, block, pvm);
203}
204
205static int
206nv50_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
207	      struct nvkm_oclass *oclass, void *data, u32 size,
208	      struct nvkm_object **pobject)
209{
210	struct nv50_mmu_priv *priv;
211	int ret;
212
213	ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
214	*pobject = nv_object(priv);
215	if (ret)
216		return ret;
217
218	priv->base.limit = 1ULL << 40;
219	priv->base.dma_bits = 40;
220	priv->base.pgt_bits  = 29 - 12;
221	priv->base.spg_shift = 12;
222	priv->base.lpg_shift = 16;
223	priv->base.create = nv50_vm_create;
224	priv->base.map_pgt = nv50_vm_map_pgt;
225	priv->base.map = nv50_vm_map;
226	priv->base.map_sg = nv50_vm_map_sg;
227	priv->base.unmap = nv50_vm_unmap;
228	priv->base.flush = nv50_vm_flush;
229	return 0;
230}
231
232struct nvkm_oclass
233nv50_mmu_oclass = {
234	.handle = NV_SUBDEV(MMU, 0x50),
235	.ofuncs = &(struct nvkm_ofuncs) {
236		.ctor = nv50_mmu_ctor,
237		.dtor = _nvkm_mmu_dtor,
238		.init = _nvkm_mmu_init,
239		.fini = _nvkm_mmu_fini,
240	},
241};
242