1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#include "priv.h"
23
24#include <subdev/clk.h>
25#include <subdev/timer.h>
26#include <subdev/volt.h>
27
28#define BUSY_SLOT	0
29#define CLK_SLOT	7
30
31struct gk20a_pmu_dvfs_data {
32	int p_load_target;
33	int p_load_max;
34	int p_smooth;
35	unsigned int avg_load;
36};
37
38struct gk20a_pmu_priv {
39	struct nvkm_pmu base;
40	struct nvkm_alarm alarm;
41	struct gk20a_pmu_dvfs_data *data;
42};
43
44struct gk20a_pmu_dvfs_dev_status {
45	unsigned long total;
46	unsigned long busy;
47	int cur_state;
48};
49
50static int
51gk20a_pmu_dvfs_target(struct gk20a_pmu_priv *priv, int *state)
52{
53	struct nvkm_clk *clk = nvkm_clk(priv);
54
55	return nvkm_clk_astate(clk, *state, 0, false);
56}
57
58static int
59gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu_priv *priv, int *state)
60{
61	struct nvkm_clk *clk = nvkm_clk(priv);
62
63	*state = clk->pstate;
64	return 0;
65}
66
67static int
68gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu_priv *priv,
69				int *state, int load)
70{
71	struct gk20a_pmu_dvfs_data *data = priv->data;
72	struct nvkm_clk *clk = nvkm_clk(priv);
73	int cur_level, level;
74
75	/* For GK20A, the performance level is directly mapped to pstate */
76	level = cur_level = clk->pstate;
77
78	if (load > data->p_load_max) {
79		level = min(clk->state_nr - 1, level + (clk->state_nr / 3));
80	} else {
81		level += ((load - data->p_load_target) * 10 /
82				data->p_load_target) / 2;
83		level = max(0, level);
84		level = min(clk->state_nr - 1, level);
85	}
86
87	nv_trace(priv, "cur level = %d, new level = %d\n", cur_level, level);
88
89	*state = level;
90
91	if (level == cur_level)
92		return 0;
93	else
94		return 1;
95}
96
97static int
98gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu_priv *priv,
99			      struct gk20a_pmu_dvfs_dev_status *status)
100{
101	status->busy = nv_rd32(priv, 0x10a508 + (BUSY_SLOT * 0x10));
102	status->total= nv_rd32(priv, 0x10a508 + (CLK_SLOT * 0x10));
103	return 0;
104}
105
106static void
107gk20a_pmu_dvfs_reset_dev_status(struct gk20a_pmu_priv *priv)
108{
109	nv_wr32(priv, 0x10a508 + (BUSY_SLOT * 0x10), 0x80000000);
110	nv_wr32(priv, 0x10a508 + (CLK_SLOT * 0x10), 0x80000000);
111}
112
113static void
114gk20a_pmu_dvfs_work(struct nvkm_alarm *alarm)
115{
116	struct gk20a_pmu_priv *priv =
117		container_of(alarm, struct gk20a_pmu_priv, alarm);
118	struct gk20a_pmu_dvfs_data *data = priv->data;
119	struct gk20a_pmu_dvfs_dev_status status;
120	struct nvkm_clk *clk = nvkm_clk(priv);
121	struct nvkm_volt *volt = nvkm_volt(priv);
122	u32 utilization = 0;
123	int state, ret;
124
125	/*
126	 * The PMU is initialized before CLK and VOLT, so we have to make sure the
127	 * CLK and VOLT are ready here.
128	 */
129	if (!clk || !volt)
130		goto resched;
131
132	ret = gk20a_pmu_dvfs_get_dev_status(priv, &status);
133	if (ret) {
134		nv_warn(priv, "failed to get device status\n");
135		goto resched;
136	}
137
138	if (status.total)
139		utilization = div_u64((u64)status.busy * 100, status.total);
140
141	data->avg_load = (data->p_smooth * data->avg_load) + utilization;
142	data->avg_load /= data->p_smooth + 1;
143	nv_trace(priv, "utilization = %d %%, avg_load = %d %%\n",
144			utilization, data->avg_load);
145
146	ret = gk20a_pmu_dvfs_get_cur_state(priv, &state);
147	if (ret) {
148		nv_warn(priv, "failed to get current state\n");
149		goto resched;
150	}
151
152	if (gk20a_pmu_dvfs_get_target_state(priv, &state, data->avg_load)) {
153		nv_trace(priv, "set new state to %d\n", state);
154		gk20a_pmu_dvfs_target(priv, &state);
155	}
156
157resched:
158	gk20a_pmu_dvfs_reset_dev_status(priv);
159	nvkm_timer_alarm(priv, 100000000, alarm);
160}
161
162static int
163gk20a_pmu_fini(struct nvkm_object *object, bool suspend)
164{
165	struct nvkm_pmu *pmu = (void *)object;
166	struct gk20a_pmu_priv *priv = (void *)pmu;
167
168	nvkm_timer_alarm_cancel(priv, &priv->alarm);
169
170	return nvkm_subdev_fini(&pmu->base, suspend);
171}
172
173static int
174gk20a_pmu_init(struct nvkm_object *object)
175{
176	struct nvkm_pmu *pmu = (void *)object;
177	struct gk20a_pmu_priv *priv = (void *)pmu;
178	int ret;
179
180	ret = nvkm_subdev_init(&pmu->base);
181	if (ret)
182		return ret;
183
184	pmu->pgob = nvkm_pmu_pgob;
185
186	/* init pwr perf counter */
187	nv_wr32(pmu, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001);
188	nv_wr32(pmu, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002);
189	nv_wr32(pmu, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003);
190
191	nvkm_timer_alarm(pmu, 2000000000, &priv->alarm);
192	return ret;
193}
194
195static struct gk20a_pmu_dvfs_data
196gk20a_dvfs_data= {
197	.p_load_target = 70,
198	.p_load_max = 90,
199	.p_smooth = 1,
200};
201
202static int
203gk20a_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
204	       struct nvkm_oclass *oclass, void *data, u32 size,
205	       struct nvkm_object **pobject)
206{
207	struct gk20a_pmu_priv *priv;
208	int ret;
209
210	ret = nvkm_pmu_create(parent, engine, oclass, &priv);
211	*pobject = nv_object(priv);
212	if (ret)
213		return ret;
214
215	priv->data = &gk20a_dvfs_data;
216
217	nvkm_alarm_init(&priv->alarm, gk20a_pmu_dvfs_work);
218	return 0;
219}
220
221struct nvkm_oclass *
222gk20a_pmu_oclass = &(struct nvkm_pmu_impl) {
223	.base.handle = NV_SUBDEV(PMU, 0xea),
224	.base.ofuncs = &(struct nvkm_ofuncs) {
225		.ctor = gk20a_pmu_ctor,
226		.dtor = _nvkm_pmu_dtor,
227		.init = gk20a_pmu_init,
228		.fini = gk20a_pmu_fini,
229	},
230}.base;
231