1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#include <linux/console.h> 29#include <linux/slab.h> 30#include <drm/drmP.h> 31#include <drm/drm_crtc_helper.h> 32#include <drm/radeon_drm.h> 33#include <linux/vgaarb.h> 34#include <linux/vga_switcheroo.h> 35#include <linux/efi.h> 36#include "radeon_reg.h" 37#include "radeon.h" 38#include "atom.h" 39 40static const char radeon_family_name[][16] = { 41 "R100", 42 "RV100", 43 "RS100", 44 "RV200", 45 "RS200", 46 "R200", 47 "RV250", 48 "RS300", 49 "RV280", 50 "R300", 51 "R350", 52 "RV350", 53 "RV380", 54 "R420", 55 "R423", 56 "RV410", 57 "RS400", 58 "RS480", 59 "RS600", 60 "RS690", 61 "RS740", 62 "RV515", 63 "R520", 64 "RV530", 65 "RV560", 66 "RV570", 67 "R580", 68 "R600", 69 "RV610", 70 "RV630", 71 "RV670", 72 "RV620", 73 "RV635", 74 "RS780", 75 "RS880", 76 "RV770", 77 "RV730", 78 "RV710", 79 "RV740", 80 "CEDAR", 81 "REDWOOD", 82 "JUNIPER", 83 "CYPRESS", 84 "HEMLOCK", 85 "PALM", 86 "SUMO", 87 "SUMO2", 88 "BARTS", 89 "TURKS", 90 "CAICOS", 91 "CAYMAN", 92 "ARUBA", 93 "TAHITI", 94 "PITCAIRN", 95 "VERDE", 96 "OLAND", 97 "HAINAN", 98 "BONAIRE", 99 "KAVERI", 100 "KABINI", 101 "HAWAII", 102 "MULLINS", 103 "LAST", 104}; 105 106#define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) 107#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) 108 109struct radeon_px_quirk { 110 u32 chip_vendor; 111 u32 chip_device; 112 u32 subsys_vendor; 113 u32 subsys_device; 114 u32 px_quirk_flags; 115}; 116 117static struct radeon_px_quirk radeon_px_quirk_list[] = { 118 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) 119 * https://bugzilla.kernel.org/show_bug.cgi?id=74551 120 */ 121 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, 122 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU 123 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 124 */ 125 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, 126 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 127 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 128 */ 129 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 130 /* macbook pro 8.2 */ 131 { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP }, 132 { 0, 0, 0, 0, 0 }, 133}; 134 135bool radeon_is_px(struct drm_device *dev) 136{ 137 struct radeon_device *rdev = dev->dev_private; 138 139 if (rdev->flags & RADEON_IS_PX) 140 return true; 141 return false; 142} 143 144static void radeon_device_handle_px_quirks(struct radeon_device *rdev) 145{ 146 struct radeon_px_quirk *p = radeon_px_quirk_list; 147 148 /* Apply PX quirks */ 149 while (p && p->chip_device != 0) { 150 if (rdev->pdev->vendor == p->chip_vendor && 151 rdev->pdev->device == p->chip_device && 152 rdev->pdev->subsystem_vendor == p->subsys_vendor && 153 rdev->pdev->subsystem_device == p->subsys_device) { 154 rdev->px_quirk_flags = p->px_quirk_flags; 155 break; 156 } 157 ++p; 158 } 159 160 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) 161 rdev->flags &= ~RADEON_IS_PX; 162} 163 164/** 165 * radeon_program_register_sequence - program an array of registers. 166 * 167 * @rdev: radeon_device pointer 168 * @registers: pointer to the register array 169 * @array_size: size of the register array 170 * 171 * Programs an array or registers with and and or masks. 172 * This is a helper for setting golden registers. 173 */ 174void radeon_program_register_sequence(struct radeon_device *rdev, 175 const u32 *registers, 176 const u32 array_size) 177{ 178 u32 tmp, reg, and_mask, or_mask; 179 int i; 180 181 if (array_size % 3) 182 return; 183 184 for (i = 0; i < array_size; i +=3) { 185 reg = registers[i + 0]; 186 and_mask = registers[i + 1]; 187 or_mask = registers[i + 2]; 188 189 if (and_mask == 0xffffffff) { 190 tmp = or_mask; 191 } else { 192 tmp = RREG32(reg); 193 tmp &= ~and_mask; 194 tmp |= or_mask; 195 } 196 WREG32(reg, tmp); 197 } 198} 199 200void radeon_pci_config_reset(struct radeon_device *rdev) 201{ 202 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); 203} 204 205/** 206 * radeon_surface_init - Clear GPU surface registers. 207 * 208 * @rdev: radeon_device pointer 209 * 210 * Clear GPU surface registers (r1xx-r5xx). 211 */ 212void radeon_surface_init(struct radeon_device *rdev) 213{ 214 /* FIXME: check this out */ 215 if (rdev->family < CHIP_R600) { 216 int i; 217 218 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 219 if (rdev->surface_regs[i].bo) 220 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 221 else 222 radeon_clear_surface_reg(rdev, i); 223 } 224 /* enable surfaces */ 225 WREG32(RADEON_SURFACE_CNTL, 0); 226 } 227} 228 229/* 230 * GPU scratch registers helpers function. 231 */ 232/** 233 * radeon_scratch_init - Init scratch register driver information. 234 * 235 * @rdev: radeon_device pointer 236 * 237 * Init CP scratch register driver information (r1xx-r5xx) 238 */ 239void radeon_scratch_init(struct radeon_device *rdev) 240{ 241 int i; 242 243 /* FIXME: check this out */ 244 if (rdev->family < CHIP_R300) { 245 rdev->scratch.num_reg = 5; 246 } else { 247 rdev->scratch.num_reg = 7; 248 } 249 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 250 for (i = 0; i < rdev->scratch.num_reg; i++) { 251 rdev->scratch.free[i] = true; 252 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 253 } 254} 255 256/** 257 * radeon_scratch_get - Allocate a scratch register 258 * 259 * @rdev: radeon_device pointer 260 * @reg: scratch register mmio offset 261 * 262 * Allocate a CP scratch register for use by the driver (all asics). 263 * Returns 0 on success or -EINVAL on failure. 264 */ 265int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 266{ 267 int i; 268 269 for (i = 0; i < rdev->scratch.num_reg; i++) { 270 if (rdev->scratch.free[i]) { 271 rdev->scratch.free[i] = false; 272 *reg = rdev->scratch.reg[i]; 273 return 0; 274 } 275 } 276 return -EINVAL; 277} 278 279/** 280 * radeon_scratch_free - Free a scratch register 281 * 282 * @rdev: radeon_device pointer 283 * @reg: scratch register mmio offset 284 * 285 * Free a CP scratch register allocated for use by the driver (all asics) 286 */ 287void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 288{ 289 int i; 290 291 for (i = 0; i < rdev->scratch.num_reg; i++) { 292 if (rdev->scratch.reg[i] == reg) { 293 rdev->scratch.free[i] = true; 294 return; 295 } 296 } 297} 298 299/* 300 * GPU doorbell aperture helpers function. 301 */ 302/** 303 * radeon_doorbell_init - Init doorbell driver information. 304 * 305 * @rdev: radeon_device pointer 306 * 307 * Init doorbell driver information (CIK) 308 * Returns 0 on success, error on failure. 309 */ 310static int radeon_doorbell_init(struct radeon_device *rdev) 311{ 312 /* doorbell bar mapping */ 313 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); 314 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); 315 316 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); 317 if (rdev->doorbell.num_doorbells == 0) 318 return -EINVAL; 319 320 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); 321 if (rdev->doorbell.ptr == NULL) { 322 return -ENOMEM; 323 } 324 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); 325 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); 326 327 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); 328 329 return 0; 330} 331 332/** 333 * radeon_doorbell_fini - Tear down doorbell driver information. 334 * 335 * @rdev: radeon_device pointer 336 * 337 * Tear down doorbell driver information (CIK) 338 */ 339static void radeon_doorbell_fini(struct radeon_device *rdev) 340{ 341 iounmap(rdev->doorbell.ptr); 342 rdev->doorbell.ptr = NULL; 343} 344 345/** 346 * radeon_doorbell_get - Allocate a doorbell entry 347 * 348 * @rdev: radeon_device pointer 349 * @doorbell: doorbell index 350 * 351 * Allocate a doorbell for use by the driver (all asics). 352 * Returns 0 on success or -EINVAL on failure. 353 */ 354int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) 355{ 356 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); 357 if (offset < rdev->doorbell.num_doorbells) { 358 __set_bit(offset, rdev->doorbell.used); 359 *doorbell = offset; 360 return 0; 361 } else { 362 return -EINVAL; 363 } 364} 365 366/** 367 * radeon_doorbell_free - Free a doorbell entry 368 * 369 * @rdev: radeon_device pointer 370 * @doorbell: doorbell index 371 * 372 * Free a doorbell allocated for use by the driver (all asics) 373 */ 374void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) 375{ 376 if (doorbell < rdev->doorbell.num_doorbells) 377 __clear_bit(doorbell, rdev->doorbell.used); 378} 379 380/** 381 * radeon_doorbell_get_kfd_info - Report doorbell configuration required to 382 * setup KFD 383 * 384 * @rdev: radeon_device pointer 385 * @aperture_base: output returning doorbell aperture base physical address 386 * @aperture_size: output returning doorbell aperture size in bytes 387 * @start_offset: output returning # of doorbell bytes reserved for radeon. 388 * 389 * Radeon and the KFD share the doorbell aperture. Radeon sets it up, 390 * takes doorbells required for its own rings and reports the setup to KFD. 391 * Radeon reserved doorbells are at the start of the doorbell aperture. 392 */ 393void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, 394 phys_addr_t *aperture_base, 395 size_t *aperture_size, 396 size_t *start_offset) 397{ 398 /* The first num_doorbells are used by radeon. 399 * KFD takes whatever's left in the aperture. */ 400 if (rdev->doorbell.size > rdev->doorbell.num_doorbells * sizeof(u32)) { 401 *aperture_base = rdev->doorbell.base; 402 *aperture_size = rdev->doorbell.size; 403 *start_offset = rdev->doorbell.num_doorbells * sizeof(u32); 404 } else { 405 *aperture_base = 0; 406 *aperture_size = 0; 407 *start_offset = 0; 408 } 409} 410 411/* 412 * radeon_wb_*() 413 * Writeback is the the method by which the the GPU updates special pages 414 * in memory with the status of certain GPU events (fences, ring pointers, 415 * etc.). 416 */ 417 418/** 419 * radeon_wb_disable - Disable Writeback 420 * 421 * @rdev: radeon_device pointer 422 * 423 * Disables Writeback (all asics). Used for suspend. 424 */ 425void radeon_wb_disable(struct radeon_device *rdev) 426{ 427 rdev->wb.enabled = false; 428} 429 430/** 431 * radeon_wb_fini - Disable Writeback and free memory 432 * 433 * @rdev: radeon_device pointer 434 * 435 * Disables Writeback and frees the Writeback memory (all asics). 436 * Used at driver shutdown. 437 */ 438void radeon_wb_fini(struct radeon_device *rdev) 439{ 440 radeon_wb_disable(rdev); 441 if (rdev->wb.wb_obj) { 442 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { 443 radeon_bo_kunmap(rdev->wb.wb_obj); 444 radeon_bo_unpin(rdev->wb.wb_obj); 445 radeon_bo_unreserve(rdev->wb.wb_obj); 446 } 447 radeon_bo_unref(&rdev->wb.wb_obj); 448 rdev->wb.wb = NULL; 449 rdev->wb.wb_obj = NULL; 450 } 451} 452 453/** 454 * radeon_wb_init- Init Writeback driver info and allocate memory 455 * 456 * @rdev: radeon_device pointer 457 * 458 * Disables Writeback and frees the Writeback memory (all asics). 459 * Used at driver startup. 460 * Returns 0 on success or an -error on failure. 461 */ 462int radeon_wb_init(struct radeon_device *rdev) 463{ 464 int r; 465 466 if (rdev->wb.wb_obj == NULL) { 467 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 468 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL, 469 &rdev->wb.wb_obj); 470 if (r) { 471 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 472 return r; 473 } 474 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 475 if (unlikely(r != 0)) { 476 radeon_wb_fini(rdev); 477 return r; 478 } 479 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 480 &rdev->wb.gpu_addr); 481 if (r) { 482 radeon_bo_unreserve(rdev->wb.wb_obj); 483 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 484 radeon_wb_fini(rdev); 485 return r; 486 } 487 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); 488 radeon_bo_unreserve(rdev->wb.wb_obj); 489 if (r) { 490 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 491 radeon_wb_fini(rdev); 492 return r; 493 } 494 } 495 496 /* clear wb memory */ 497 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); 498 /* disable event_write fences */ 499 rdev->wb.use_event = false; 500 /* disabled via module param */ 501 if (radeon_no_wb == 1) { 502 rdev->wb.enabled = false; 503 } else { 504 if (rdev->flags & RADEON_IS_AGP) { 505 /* often unreliable on AGP */ 506 rdev->wb.enabled = false; 507 } else if (rdev->family < CHIP_R300) { 508 /* often unreliable on pre-r300 */ 509 rdev->wb.enabled = false; 510 } else { 511 rdev->wb.enabled = true; 512 /* event_write fences are only available on r600+ */ 513 if (rdev->family >= CHIP_R600) { 514 rdev->wb.use_event = true; 515 } 516 } 517 } 518 /* always use writeback/events on NI, APUs */ 519 if (rdev->family >= CHIP_PALM) { 520 rdev->wb.enabled = true; 521 rdev->wb.use_event = true; 522 } 523 524 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 525 526 return 0; 527} 528 529/** 530 * radeon_vram_location - try to find VRAM location 531 * @rdev: radeon device structure holding all necessary informations 532 * @mc: memory controller structure holding memory informations 533 * @base: base address at which to put VRAM 534 * 535 * Function will place try to place VRAM at base address provided 536 * as parameter (which is so far either PCI aperture address or 537 * for IGP TOM base address). 538 * 539 * If there is not enough space to fit the unvisible VRAM in the 32bits 540 * address space then we limit the VRAM size to the aperture. 541 * 542 * If we are using AGP and if the AGP aperture doesn't allow us to have 543 * room for all the VRAM than we restrict the VRAM to the PCI aperture 544 * size and print a warning. 545 * 546 * This function will never fails, worst case are limiting VRAM. 547 * 548 * Note: GTT start, end, size should be initialized before calling this 549 * function on AGP platform. 550 * 551 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, 552 * this shouldn't be a problem as we are using the PCI aperture as a reference. 553 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 554 * not IGP. 555 * 556 * Note: we use mc_vram_size as on some board we need to program the mc to 557 * cover the whole aperture even if VRAM size is inferior to aperture size 558 * Novell bug 204882 + along with lots of ubuntu ones 559 * 560 * Note: when limiting vram it's safe to overwritte real_vram_size because 561 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 562 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 563 * ones) 564 * 565 * Note: IGP TOM addr should be the same as the aperture addr, we don't 566 * explicitly check for that thought. 567 * 568 * FIXME: when reducing VRAM size align new size on power of 2. 569 */ 570void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 571{ 572 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 573 574 mc->vram_start = base; 575 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { 576 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 577 mc->real_vram_size = mc->aper_size; 578 mc->mc_vram_size = mc->aper_size; 579 } 580 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 581 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 582 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 583 mc->real_vram_size = mc->aper_size; 584 mc->mc_vram_size = mc->aper_size; 585 } 586 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 587 if (limit && limit < mc->real_vram_size) 588 mc->real_vram_size = limit; 589 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 590 mc->mc_vram_size >> 20, mc->vram_start, 591 mc->vram_end, mc->real_vram_size >> 20); 592} 593 594/** 595 * radeon_gtt_location - try to find GTT location 596 * @rdev: radeon device structure holding all necessary informations 597 * @mc: memory controller structure holding memory informations 598 * 599 * Function will place try to place GTT before or after VRAM. 600 * 601 * If GTT size is bigger than space left then we ajust GTT size. 602 * Thus function will never fails. 603 * 604 * FIXME: when reducing GTT size align new size on power of 2. 605 */ 606void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 607{ 608 u64 size_af, size_bf; 609 610 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 611 size_bf = mc->vram_start & ~mc->gtt_base_align; 612 if (size_bf > size_af) { 613 if (mc->gtt_size > size_bf) { 614 dev_warn(rdev->dev, "limiting GTT\n"); 615 mc->gtt_size = size_bf; 616 } 617 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 618 } else { 619 if (mc->gtt_size > size_af) { 620 dev_warn(rdev->dev, "limiting GTT\n"); 621 mc->gtt_size = size_af; 622 } 623 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 624 } 625 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 626 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 627 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 628} 629 630/* 631 * GPU helpers function. 632 */ 633/** 634 * radeon_card_posted - check if the hw has already been initialized 635 * 636 * @rdev: radeon_device pointer 637 * 638 * Check if the asic has been initialized (all asics). 639 * Used at driver startup. 640 * Returns true if initialized or false if not. 641 */ 642bool radeon_card_posted(struct radeon_device *rdev) 643{ 644 uint32_t reg; 645 646 /* required for EFI mode on macbook2,1 which uses an r5xx asic */ 647 if (efi_enabled(EFI_BOOT) && 648 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 649 (rdev->family < CHIP_R600)) 650 return false; 651 652 if (ASIC_IS_NODCE(rdev)) 653 goto check_memsize; 654 655 /* first check CRTCs */ 656 if (ASIC_IS_DCE4(rdev)) { 657 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 658 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 659 if (rdev->num_crtc >= 4) { 660 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 661 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 662 } 663 if (rdev->num_crtc >= 6) { 664 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 665 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 666 } 667 if (reg & EVERGREEN_CRTC_MASTER_EN) 668 return true; 669 } else if (ASIC_IS_AVIVO(rdev)) { 670 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 671 RREG32(AVIVO_D2CRTC_CONTROL); 672 if (reg & AVIVO_CRTC_EN) { 673 return true; 674 } 675 } else { 676 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 677 RREG32(RADEON_CRTC2_GEN_CNTL); 678 if (reg & RADEON_CRTC_EN) { 679 return true; 680 } 681 } 682 683check_memsize: 684 /* then check MEM_SIZE, in case the crtcs are off */ 685 if (rdev->family >= CHIP_R600) 686 reg = RREG32(R600_CONFIG_MEMSIZE); 687 else 688 reg = RREG32(RADEON_CONFIG_MEMSIZE); 689 690 if (reg) 691 return true; 692 693 return false; 694 695} 696 697/** 698 * radeon_update_bandwidth_info - update display bandwidth params 699 * 700 * @rdev: radeon_device pointer 701 * 702 * Used when sclk/mclk are switched or display modes are set. 703 * params are used to calculate display watermarks (all asics) 704 */ 705void radeon_update_bandwidth_info(struct radeon_device *rdev) 706{ 707 fixed20_12 a; 708 u32 sclk = rdev->pm.current_sclk; 709 u32 mclk = rdev->pm.current_mclk; 710 711 /* sclk/mclk in Mhz */ 712 a.full = dfixed_const(100); 713 rdev->pm.sclk.full = dfixed_const(sclk); 714 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 715 rdev->pm.mclk.full = dfixed_const(mclk); 716 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 717 718 if (rdev->flags & RADEON_IS_IGP) { 719 a.full = dfixed_const(16); 720 /* core_bandwidth = sclk(Mhz) * 16 */ 721 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 722 } 723} 724 725/** 726 * radeon_boot_test_post_card - check and possibly initialize the hw 727 * 728 * @rdev: radeon_device pointer 729 * 730 * Check if the asic is initialized and if not, attempt to initialize 731 * it (all asics). 732 * Returns true if initialized or false if not. 733 */ 734bool radeon_boot_test_post_card(struct radeon_device *rdev) 735{ 736 if (radeon_card_posted(rdev)) 737 return true; 738 739 if (rdev->bios) { 740 DRM_INFO("GPU not posted. posting now...\n"); 741 if (rdev->is_atom_bios) 742 atom_asic_init(rdev->mode_info.atom_context); 743 else 744 radeon_combios_asic_init(rdev->ddev); 745 return true; 746 } else { 747 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 748 return false; 749 } 750} 751 752/** 753 * radeon_dummy_page_init - init dummy page used by the driver 754 * 755 * @rdev: radeon_device pointer 756 * 757 * Allocate the dummy page used by the driver (all asics). 758 * This dummy page is used by the driver as a filler for gart entries 759 * when pages are taken out of the GART 760 * Returns 0 on sucess, -ENOMEM on failure. 761 */ 762int radeon_dummy_page_init(struct radeon_device *rdev) 763{ 764 if (rdev->dummy_page.page) 765 return 0; 766 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); 767 if (rdev->dummy_page.page == NULL) 768 return -ENOMEM; 769 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, 770 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 771 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) { 772 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 773 __free_page(rdev->dummy_page.page); 774 rdev->dummy_page.page = NULL; 775 return -ENOMEM; 776 } 777 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, 778 RADEON_GART_PAGE_DUMMY); 779 return 0; 780} 781 782/** 783 * radeon_dummy_page_fini - free dummy page used by the driver 784 * 785 * @rdev: radeon_device pointer 786 * 787 * Frees the dummy page used by the driver (all asics). 788 */ 789void radeon_dummy_page_fini(struct radeon_device *rdev) 790{ 791 if (rdev->dummy_page.page == NULL) 792 return; 793 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, 794 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 795 __free_page(rdev->dummy_page.page); 796 rdev->dummy_page.page = NULL; 797} 798 799 800/* ATOM accessor methods */ 801/* 802 * ATOM is an interpreted byte code stored in tables in the vbios. The 803 * driver registers callbacks to access registers and the interpreter 804 * in the driver parses the tables and executes then to program specific 805 * actions (set display modes, asic init, etc.). See radeon_atombios.c, 806 * atombios.h, and atom.c 807 */ 808 809/** 810 * cail_pll_read - read PLL register 811 * 812 * @info: atom card_info pointer 813 * @reg: PLL register offset 814 * 815 * Provides a PLL register accessor for the atom interpreter (r4xx+). 816 * Returns the value of the PLL register. 817 */ 818static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 819{ 820 struct radeon_device *rdev = info->dev->dev_private; 821 uint32_t r; 822 823 r = rdev->pll_rreg(rdev, reg); 824 return r; 825} 826 827/** 828 * cail_pll_write - write PLL register 829 * 830 * @info: atom card_info pointer 831 * @reg: PLL register offset 832 * @val: value to write to the pll register 833 * 834 * Provides a PLL register accessor for the atom interpreter (r4xx+). 835 */ 836static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 837{ 838 struct radeon_device *rdev = info->dev->dev_private; 839 840 rdev->pll_wreg(rdev, reg, val); 841} 842 843/** 844 * cail_mc_read - read MC (Memory Controller) register 845 * 846 * @info: atom card_info pointer 847 * @reg: MC register offset 848 * 849 * Provides an MC register accessor for the atom interpreter (r4xx+). 850 * Returns the value of the MC register. 851 */ 852static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 853{ 854 struct radeon_device *rdev = info->dev->dev_private; 855 uint32_t r; 856 857 r = rdev->mc_rreg(rdev, reg); 858 return r; 859} 860 861/** 862 * cail_mc_write - write MC (Memory Controller) register 863 * 864 * @info: atom card_info pointer 865 * @reg: MC register offset 866 * @val: value to write to the pll register 867 * 868 * Provides a MC register accessor for the atom interpreter (r4xx+). 869 */ 870static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 871{ 872 struct radeon_device *rdev = info->dev->dev_private; 873 874 rdev->mc_wreg(rdev, reg, val); 875} 876 877/** 878 * cail_reg_write - write MMIO register 879 * 880 * @info: atom card_info pointer 881 * @reg: MMIO register offset 882 * @val: value to write to the pll register 883 * 884 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 885 */ 886static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 887{ 888 struct radeon_device *rdev = info->dev->dev_private; 889 890 WREG32(reg*4, val); 891} 892 893/** 894 * cail_reg_read - read MMIO register 895 * 896 * @info: atom card_info pointer 897 * @reg: MMIO register offset 898 * 899 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 900 * Returns the value of the MMIO register. 901 */ 902static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 903{ 904 struct radeon_device *rdev = info->dev->dev_private; 905 uint32_t r; 906 907 r = RREG32(reg*4); 908 return r; 909} 910 911/** 912 * cail_ioreg_write - write IO register 913 * 914 * @info: atom card_info pointer 915 * @reg: IO register offset 916 * @val: value to write to the pll register 917 * 918 * Provides a IO register accessor for the atom interpreter (r4xx+). 919 */ 920static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 921{ 922 struct radeon_device *rdev = info->dev->dev_private; 923 924 WREG32_IO(reg*4, val); 925} 926 927/** 928 * cail_ioreg_read - read IO register 929 * 930 * @info: atom card_info pointer 931 * @reg: IO register offset 932 * 933 * Provides an IO register accessor for the atom interpreter (r4xx+). 934 * Returns the value of the IO register. 935 */ 936static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 937{ 938 struct radeon_device *rdev = info->dev->dev_private; 939 uint32_t r; 940 941 r = RREG32_IO(reg*4); 942 return r; 943} 944 945/** 946 * radeon_atombios_init - init the driver info and callbacks for atombios 947 * 948 * @rdev: radeon_device pointer 949 * 950 * Initializes the driver info and register access callbacks for the 951 * ATOM interpreter (r4xx+). 952 * Returns 0 on sucess, -ENOMEM on failure. 953 * Called at driver startup. 954 */ 955int radeon_atombios_init(struct radeon_device *rdev) 956{ 957 struct card_info *atom_card_info = 958 kzalloc(sizeof(struct card_info), GFP_KERNEL); 959 960 if (!atom_card_info) 961 return -ENOMEM; 962 963 rdev->mode_info.atom_card_info = atom_card_info; 964 atom_card_info->dev = rdev->ddev; 965 atom_card_info->reg_read = cail_reg_read; 966 atom_card_info->reg_write = cail_reg_write; 967 /* needed for iio ops */ 968 if (rdev->rio_mem) { 969 atom_card_info->ioreg_read = cail_ioreg_read; 970 atom_card_info->ioreg_write = cail_ioreg_write; 971 } else { 972 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 973 atom_card_info->ioreg_read = cail_reg_read; 974 atom_card_info->ioreg_write = cail_reg_write; 975 } 976 atom_card_info->mc_read = cail_mc_read; 977 atom_card_info->mc_write = cail_mc_write; 978 atom_card_info->pll_read = cail_pll_read; 979 atom_card_info->pll_write = cail_pll_write; 980 981 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 982 if (!rdev->mode_info.atom_context) { 983 radeon_atombios_fini(rdev); 984 return -ENOMEM; 985 } 986 987 mutex_init(&rdev->mode_info.atom_context->mutex); 988 mutex_init(&rdev->mode_info.atom_context->scratch_mutex); 989 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 990 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 991 return 0; 992} 993 994/** 995 * radeon_atombios_fini - free the driver info and callbacks for atombios 996 * 997 * @rdev: radeon_device pointer 998 * 999 * Frees the driver info and register access callbacks for the ATOM 1000 * interpreter (r4xx+). 1001 * Called at driver shutdown. 1002 */ 1003void radeon_atombios_fini(struct radeon_device *rdev) 1004{ 1005 if (rdev->mode_info.atom_context) { 1006 kfree(rdev->mode_info.atom_context->scratch); 1007 } 1008 kfree(rdev->mode_info.atom_context); 1009 rdev->mode_info.atom_context = NULL; 1010 kfree(rdev->mode_info.atom_card_info); 1011 rdev->mode_info.atom_card_info = NULL; 1012} 1013 1014/* COMBIOS */ 1015/* 1016 * COMBIOS is the bios format prior to ATOM. It provides 1017 * command tables similar to ATOM, but doesn't have a unified 1018 * parser. See radeon_combios.c 1019 */ 1020 1021/** 1022 * radeon_combios_init - init the driver info for combios 1023 * 1024 * @rdev: radeon_device pointer 1025 * 1026 * Initializes the driver info for combios (r1xx-r3xx). 1027 * Returns 0 on sucess. 1028 * Called at driver startup. 1029 */ 1030int radeon_combios_init(struct radeon_device *rdev) 1031{ 1032 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 1033 return 0; 1034} 1035 1036/** 1037 * radeon_combios_fini - free the driver info for combios 1038 * 1039 * @rdev: radeon_device pointer 1040 * 1041 * Frees the driver info for combios (r1xx-r3xx). 1042 * Called at driver shutdown. 1043 */ 1044void radeon_combios_fini(struct radeon_device *rdev) 1045{ 1046} 1047 1048/* if we get transitioned to only one device, take VGA back */ 1049/** 1050 * radeon_vga_set_decode - enable/disable vga decode 1051 * 1052 * @cookie: radeon_device pointer 1053 * @state: enable/disable vga decode 1054 * 1055 * Enable/disable vga decode (all asics). 1056 * Returns VGA resource flags. 1057 */ 1058static unsigned int radeon_vga_set_decode(void *cookie, bool state) 1059{ 1060 struct radeon_device *rdev = cookie; 1061 radeon_vga_set_state(rdev, state); 1062 if (state) 1063 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 1064 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1065 else 1066 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1067} 1068 1069/** 1070 * radeon_check_pot_argument - check that argument is a power of two 1071 * 1072 * @arg: value to check 1073 * 1074 * Validates that a certain argument is a power of two (all asics). 1075 * Returns true if argument is valid. 1076 */ 1077static bool radeon_check_pot_argument(int arg) 1078{ 1079 return (arg & (arg - 1)) == 0; 1080} 1081 1082/** 1083 * radeon_check_arguments - validate module params 1084 * 1085 * @rdev: radeon_device pointer 1086 * 1087 * Validates certain module parameters and updates 1088 * the associated values used by the driver (all asics). 1089 */ 1090static void radeon_check_arguments(struct radeon_device *rdev) 1091{ 1092 /* vramlimit must be a power of two */ 1093 if (!radeon_check_pot_argument(radeon_vram_limit)) { 1094 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 1095 radeon_vram_limit); 1096 radeon_vram_limit = 0; 1097 } 1098 1099 if (radeon_gart_size == -1) { 1100 /* default to a larger gart size on newer asics */ 1101 if (rdev->family >= CHIP_RV770) 1102 radeon_gart_size = 1024; 1103 else 1104 radeon_gart_size = 512; 1105 } 1106 /* gtt size must be power of two and greater or equal to 32M */ 1107 if (radeon_gart_size < 32) { 1108 dev_warn(rdev->dev, "gart size (%d) too small\n", 1109 radeon_gart_size); 1110 if (rdev->family >= CHIP_RV770) 1111 radeon_gart_size = 1024; 1112 else 1113 radeon_gart_size = 512; 1114 } else if (!radeon_check_pot_argument(radeon_gart_size)) { 1115 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 1116 radeon_gart_size); 1117 if (rdev->family >= CHIP_RV770) 1118 radeon_gart_size = 1024; 1119 else 1120 radeon_gart_size = 512; 1121 } 1122 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 1123 1124 /* AGP mode can only be -1, 1, 2, 4, 8 */ 1125 switch (radeon_agpmode) { 1126 case -1: 1127 case 0: 1128 case 1: 1129 case 2: 1130 case 4: 1131 case 8: 1132 break; 1133 default: 1134 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 1135 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 1136 radeon_agpmode = 0; 1137 break; 1138 } 1139 1140 if (!radeon_check_pot_argument(radeon_vm_size)) { 1141 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", 1142 radeon_vm_size); 1143 radeon_vm_size = 4; 1144 } 1145 1146 if (radeon_vm_size < 1) { 1147 dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n", 1148 radeon_vm_size); 1149 radeon_vm_size = 4; 1150 } 1151 1152 /* 1153 * Max GPUVM size for Cayman, SI and CI are 40 bits. 1154 */ 1155 if (radeon_vm_size > 1024) { 1156 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", 1157 radeon_vm_size); 1158 radeon_vm_size = 4; 1159 } 1160 1161 /* defines number of bits in page table versus page directory, 1162 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the 1163 * page table and the remaining bits are in the page directory */ 1164 if (radeon_vm_block_size == -1) { 1165 1166 /* Total bits covered by PD + PTs */ 1167 unsigned bits = ilog2(radeon_vm_size) + 18; 1168 1169 /* Make sure the PD is 4K in size up to 8GB address space. 1170 Above that split equal between PD and PTs */ 1171 if (radeon_vm_size <= 8) 1172 radeon_vm_block_size = bits - 9; 1173 else 1174 radeon_vm_block_size = (bits + 3) / 2; 1175 1176 } else if (radeon_vm_block_size < 9) { 1177 dev_warn(rdev->dev, "VM page table size (%d) too small\n", 1178 radeon_vm_block_size); 1179 radeon_vm_block_size = 9; 1180 } 1181 1182 if (radeon_vm_block_size > 24 || 1183 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { 1184 dev_warn(rdev->dev, "VM page table size (%d) too large\n", 1185 radeon_vm_block_size); 1186 radeon_vm_block_size = 9; 1187 } 1188} 1189 1190/** 1191 * radeon_switcheroo_set_state - set switcheroo state 1192 * 1193 * @pdev: pci dev pointer 1194 * @state: vga switcheroo state 1195 * 1196 * Callback for the switcheroo driver. Suspends or resumes the 1197 * the asics before or after it is powered up using ACPI methods. 1198 */ 1199static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 1200{ 1201 struct drm_device *dev = pci_get_drvdata(pdev); 1202 struct radeon_device *rdev = dev->dev_private; 1203 1204 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF) 1205 return; 1206 1207 if (state == VGA_SWITCHEROO_ON) { 1208 unsigned d3_delay = dev->pdev->d3_delay; 1209 1210 printk(KERN_INFO "radeon: switched on\n"); 1211 /* don't suspend or resume card normally */ 1212 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1213 1214 if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP)) 1215 dev->pdev->d3_delay = 20; 1216 1217 radeon_resume_kms(dev, true, true); 1218 1219 dev->pdev->d3_delay = d3_delay; 1220 1221 dev->switch_power_state = DRM_SWITCH_POWER_ON; 1222 drm_kms_helper_poll_enable(dev); 1223 } else { 1224 printk(KERN_INFO "radeon: switched off\n"); 1225 drm_kms_helper_poll_disable(dev); 1226 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1227 radeon_suspend_kms(dev, true, true); 1228 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 1229 } 1230} 1231 1232/** 1233 * radeon_switcheroo_can_switch - see if switcheroo state can change 1234 * 1235 * @pdev: pci dev pointer 1236 * 1237 * Callback for the switcheroo driver. Check of the switcheroo 1238 * state can be changed. 1239 * Returns true if the state can be changed, false if not. 1240 */ 1241static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 1242{ 1243 struct drm_device *dev = pci_get_drvdata(pdev); 1244 1245 /* 1246 * FIXME: open_count is protected by drm_global_mutex but that would lead to 1247 * locking inversion with the driver load path. And the access here is 1248 * completely racy anyway. So don't bother with locking for now. 1249 */ 1250 return dev->open_count == 0; 1251} 1252 1253static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { 1254 .set_gpu_state = radeon_switcheroo_set_state, 1255 .reprobe = NULL, 1256 .can_switch = radeon_switcheroo_can_switch, 1257}; 1258 1259/** 1260 * radeon_device_init - initialize the driver 1261 * 1262 * @rdev: radeon_device pointer 1263 * @pdev: drm dev pointer 1264 * @pdev: pci dev pointer 1265 * @flags: driver flags 1266 * 1267 * Initializes the driver info and hw (all asics). 1268 * Returns 0 for success or an error on failure. 1269 * Called at driver startup. 1270 */ 1271int radeon_device_init(struct radeon_device *rdev, 1272 struct drm_device *ddev, 1273 struct pci_dev *pdev, 1274 uint32_t flags) 1275{ 1276 int r, i; 1277 int dma_bits; 1278 bool runtime = false; 1279 1280 rdev->shutdown = false; 1281 rdev->dev = &pdev->dev; 1282 rdev->ddev = ddev; 1283 rdev->pdev = pdev; 1284 rdev->flags = flags; 1285 rdev->family = flags & RADEON_FAMILY_MASK; 1286 rdev->is_atom_bios = false; 1287 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 1288 rdev->mc.gtt_size = 512 * 1024 * 1024; 1289 rdev->accel_working = false; 1290 /* set up ring ids */ 1291 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1292 rdev->ring[i].idx = i; 1293 } 1294 rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS); 1295 1296 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", 1297 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1298 pdev->subsystem_vendor, pdev->subsystem_device); 1299 1300 /* mutex initialization are all done here so we 1301 * can recall function without having locking issues */ 1302 mutex_init(&rdev->ring_lock); 1303 mutex_init(&rdev->dc_hw_i2c_mutex); 1304 atomic_set(&rdev->ih.lock, 0); 1305 mutex_init(&rdev->gem.mutex); 1306 mutex_init(&rdev->pm.mutex); 1307 mutex_init(&rdev->gpu_clock_mutex); 1308 mutex_init(&rdev->srbm_mutex); 1309 mutex_init(&rdev->grbm_idx_mutex); 1310 init_rwsem(&rdev->pm.mclk_lock); 1311 init_rwsem(&rdev->exclusive_lock); 1312 init_waitqueue_head(&rdev->irq.vblank_queue); 1313 mutex_init(&rdev->mn_lock); 1314 hash_init(rdev->mn_hash); 1315 r = radeon_gem_init(rdev); 1316 if (r) 1317 return r; 1318 1319 radeon_check_arguments(rdev); 1320 /* Adjust VM size here. 1321 * Max GPUVM size for cayman+ is 40 bits. 1322 */ 1323 rdev->vm_manager.max_pfn = radeon_vm_size << 18; 1324 1325 /* Set asic functions */ 1326 r = radeon_asic_init(rdev); 1327 if (r) 1328 return r; 1329 1330 /* all of the newer IGP chips have an internal gart 1331 * However some rs4xx report as AGP, so remove that here. 1332 */ 1333 if ((rdev->family >= CHIP_RS400) && 1334 (rdev->flags & RADEON_IS_IGP)) { 1335 rdev->flags &= ~RADEON_IS_AGP; 1336 } 1337 1338 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 1339 radeon_agp_disable(rdev); 1340 } 1341 1342 /* Set the internal MC address mask 1343 * This is the max address of the GPU's 1344 * internal address space. 1345 */ 1346 if (rdev->family >= CHIP_CAYMAN) 1347 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1348 else if (rdev->family >= CHIP_CEDAR) 1349 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ 1350 else 1351 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ 1352 1353 /* set DMA mask + need_dma32 flags. 1354 * PCIE - can handle 40-bits. 1355 * IGP - can handle 40-bits 1356 * AGP - generally dma32 is safest 1357 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1358 */ 1359 rdev->need_dma32 = false; 1360 if (rdev->flags & RADEON_IS_AGP) 1361 rdev->need_dma32 = true; 1362 if ((rdev->flags & RADEON_IS_PCI) && 1363 (rdev->family <= CHIP_RS740)) 1364 rdev->need_dma32 = true; 1365 1366 dma_bits = rdev->need_dma32 ? 32 : 40; 1367 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1368 if (r) { 1369 rdev->need_dma32 = true; 1370 dma_bits = 32; 1371 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 1372 } 1373 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1374 if (r) { 1375 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 1376 printk(KERN_WARNING "radeon: No coherent DMA available.\n"); 1377 } 1378 1379 /* Registers mapping */ 1380 /* TODO: block userspace mapping of io register */ 1381 spin_lock_init(&rdev->mmio_idx_lock); 1382 spin_lock_init(&rdev->smc_idx_lock); 1383 spin_lock_init(&rdev->pll_idx_lock); 1384 spin_lock_init(&rdev->mc_idx_lock); 1385 spin_lock_init(&rdev->pcie_idx_lock); 1386 spin_lock_init(&rdev->pciep_idx_lock); 1387 spin_lock_init(&rdev->pif_idx_lock); 1388 spin_lock_init(&rdev->cg_idx_lock); 1389 spin_lock_init(&rdev->uvd_idx_lock); 1390 spin_lock_init(&rdev->rcu_idx_lock); 1391 spin_lock_init(&rdev->didt_idx_lock); 1392 spin_lock_init(&rdev->end_idx_lock); 1393 if (rdev->family >= CHIP_BONAIRE) { 1394 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5); 1395 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5); 1396 } else { 1397 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); 1398 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); 1399 } 1400 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 1401 if (rdev->rmmio == NULL) { 1402 return -ENOMEM; 1403 } 1404 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 1405 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 1406 1407 /* doorbell bar mapping */ 1408 if (rdev->family >= CHIP_BONAIRE) 1409 radeon_doorbell_init(rdev); 1410 1411 /* io port mapping */ 1412 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1413 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { 1414 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); 1415 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); 1416 break; 1417 } 1418 } 1419 if (rdev->rio_mem == NULL) 1420 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1421 1422 if (rdev->flags & RADEON_IS_PX) 1423 radeon_device_handle_px_quirks(rdev); 1424 1425 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1426 /* this will fail for cards that aren't VGA class devices, just 1427 * ignore it */ 1428 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1429 1430 if (rdev->flags & RADEON_IS_PX) 1431 runtime = true; 1432 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime); 1433 if (runtime) 1434 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain); 1435 1436 r = radeon_init(rdev); 1437 if (r) 1438 goto failed; 1439 1440 r = radeon_gem_debugfs_init(rdev); 1441 if (r) { 1442 DRM_ERROR("registering gem debugfs failed (%d).\n", r); 1443 } 1444 1445 r = radeon_mst_debugfs_init(rdev); 1446 if (r) { 1447 DRM_ERROR("registering mst debugfs failed (%d).\n", r); 1448 } 1449 1450 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1451 /* Acceleration not working on AGP card try again 1452 * with fallback to PCI or PCIE GART 1453 */ 1454 radeon_asic_reset(rdev); 1455 radeon_fini(rdev); 1456 radeon_agp_disable(rdev); 1457 r = radeon_init(rdev); 1458 if (r) 1459 goto failed; 1460 } 1461 1462 r = radeon_ib_ring_tests(rdev); 1463 if (r) 1464 DRM_ERROR("ib ring test failed (%d).\n", r); 1465 1466 /* 1467 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted 1468 * after the CP ring have chew one packet at least. Hence here we stop 1469 * and restart DPM after the radeon_ib_ring_tests(). 1470 */ 1471 if (rdev->pm.dpm_enabled && 1472 (rdev->pm.pm_method == PM_METHOD_DPM) && 1473 (rdev->family == CHIP_TURKS) && 1474 (rdev->flags & RADEON_IS_MOBILITY)) { 1475 mutex_lock(&rdev->pm.mutex); 1476 radeon_dpm_disable(rdev); 1477 radeon_dpm_enable(rdev); 1478 mutex_unlock(&rdev->pm.mutex); 1479 } 1480 1481 if ((radeon_testing & 1)) { 1482 if (rdev->accel_working) 1483 radeon_test_moves(rdev); 1484 else 1485 DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); 1486 } 1487 if ((radeon_testing & 2)) { 1488 if (rdev->accel_working) 1489 radeon_test_syncing(rdev); 1490 else 1491 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); 1492 } 1493 if (radeon_benchmarking) { 1494 if (rdev->accel_working) 1495 radeon_benchmark(rdev, radeon_benchmarking); 1496 else 1497 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); 1498 } 1499 return 0; 1500 1501failed: 1502 if (runtime) 1503 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1504 return r; 1505} 1506 1507static void radeon_debugfs_remove_files(struct radeon_device *rdev); 1508 1509/** 1510 * radeon_device_fini - tear down the driver 1511 * 1512 * @rdev: radeon_device pointer 1513 * 1514 * Tear down the driver info (all asics). 1515 * Called at driver shutdown. 1516 */ 1517void radeon_device_fini(struct radeon_device *rdev) 1518{ 1519 DRM_INFO("radeon: finishing device.\n"); 1520 rdev->shutdown = true; 1521 /* evict vram memory */ 1522 radeon_bo_evict_vram(rdev); 1523 radeon_fini(rdev); 1524 vga_switcheroo_unregister_client(rdev->pdev); 1525 if (rdev->flags & RADEON_IS_PX) 1526 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1527 vga_client_register(rdev->pdev, NULL, NULL, NULL); 1528 if (rdev->rio_mem) 1529 pci_iounmap(rdev->pdev, rdev->rio_mem); 1530 rdev->rio_mem = NULL; 1531 iounmap(rdev->rmmio); 1532 rdev->rmmio = NULL; 1533 if (rdev->family >= CHIP_BONAIRE) 1534 radeon_doorbell_fini(rdev); 1535 radeon_debugfs_remove_files(rdev); 1536} 1537 1538 1539/* 1540 * Suspend & resume. 1541 */ 1542/** 1543 * radeon_suspend_kms - initiate device suspend 1544 * 1545 * @pdev: drm dev pointer 1546 * @state: suspend state 1547 * 1548 * Puts the hw in the suspend state (all asics). 1549 * Returns 0 for success or an error on failure. 1550 * Called at driver suspend. 1551 */ 1552int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon) 1553{ 1554 struct radeon_device *rdev; 1555 struct drm_crtc *crtc; 1556 struct drm_connector *connector; 1557 int i, r; 1558 1559 if (dev == NULL || dev->dev_private == NULL) { 1560 return -ENODEV; 1561 } 1562 1563 rdev = dev->dev_private; 1564 1565 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1566 return 0; 1567 1568 drm_kms_helper_poll_disable(dev); 1569 1570 /* turn off display hw */ 1571 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1572 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1573 } 1574 1575 /* unpin the front buffers and cursors */ 1576 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1577 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1578 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb); 1579 struct radeon_bo *robj; 1580 1581 if (radeon_crtc->cursor_bo) { 1582 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1583 r = radeon_bo_reserve(robj, false); 1584 if (r == 0) { 1585 radeon_bo_unpin(robj); 1586 radeon_bo_unreserve(robj); 1587 } 1588 } 1589 1590 if (rfb == NULL || rfb->obj == NULL) { 1591 continue; 1592 } 1593 robj = gem_to_radeon_bo(rfb->obj); 1594 /* don't unpin kernel fb objects */ 1595 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 1596 r = radeon_bo_reserve(robj, false); 1597 if (r == 0) { 1598 radeon_bo_unpin(robj); 1599 radeon_bo_unreserve(robj); 1600 } 1601 } 1602 } 1603 /* evict vram memory */ 1604 radeon_bo_evict_vram(rdev); 1605 1606 /* wait for gpu to finish processing current batch */ 1607 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1608 r = radeon_fence_wait_empty(rdev, i); 1609 if (r) { 1610 /* delay GPU reset to resume */ 1611 radeon_fence_driver_force_completion(rdev, i); 1612 } 1613 } 1614 1615 radeon_save_bios_scratch_regs(rdev); 1616 1617 radeon_suspend(rdev); 1618 radeon_hpd_fini(rdev); 1619 /* evict remaining vram memory */ 1620 radeon_bo_evict_vram(rdev); 1621 1622 radeon_agp_suspend(rdev); 1623 1624 pci_save_state(dev->pdev); 1625 if (suspend) { 1626 /* Shut down the device */ 1627 pci_disable_device(dev->pdev); 1628 pci_set_power_state(dev->pdev, PCI_D3hot); 1629 } 1630 1631 if (fbcon) { 1632 console_lock(); 1633 radeon_fbdev_set_suspend(rdev, 1); 1634 console_unlock(); 1635 } 1636 return 0; 1637} 1638 1639/** 1640 * radeon_resume_kms - initiate device resume 1641 * 1642 * @pdev: drm dev pointer 1643 * 1644 * Bring the hw back to operating state (all asics). 1645 * Returns 0 for success or an error on failure. 1646 * Called at driver resume. 1647 */ 1648int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) 1649{ 1650 struct drm_connector *connector; 1651 struct radeon_device *rdev = dev->dev_private; 1652 struct drm_crtc *crtc; 1653 int r; 1654 1655 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1656 return 0; 1657 1658 if (fbcon) { 1659 console_lock(); 1660 } 1661 if (resume) { 1662 pci_set_power_state(dev->pdev, PCI_D0); 1663 pci_restore_state(dev->pdev); 1664 if (pci_enable_device(dev->pdev)) { 1665 if (fbcon) 1666 console_unlock(); 1667 return -1; 1668 } 1669 } 1670 /* resume AGP if in use */ 1671 radeon_agp_resume(rdev); 1672 radeon_resume(rdev); 1673 1674 r = radeon_ib_ring_tests(rdev); 1675 if (r) 1676 DRM_ERROR("ib ring test failed (%d).\n", r); 1677 1678 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1679 /* do dpm late init */ 1680 r = radeon_pm_late_init(rdev); 1681 if (r) { 1682 rdev->pm.dpm_enabled = false; 1683 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1684 } 1685 } else { 1686 /* resume old pm late */ 1687 radeon_pm_resume(rdev); 1688 } 1689 1690 radeon_restore_bios_scratch_regs(rdev); 1691 1692 /* pin cursors */ 1693 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1694 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1695 1696 if (radeon_crtc->cursor_bo) { 1697 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1698 r = radeon_bo_reserve(robj, false); 1699 if (r == 0) { 1700 /* Only 27 bit offset for legacy cursor */ 1701 r = radeon_bo_pin_restricted(robj, 1702 RADEON_GEM_DOMAIN_VRAM, 1703 ASIC_IS_AVIVO(rdev) ? 1704 0 : 1 << 27, 1705 &radeon_crtc->cursor_addr); 1706 if (r != 0) 1707 DRM_ERROR("Failed to pin cursor BO (%d)\n", r); 1708 radeon_bo_unreserve(robj); 1709 } 1710 } 1711 } 1712 1713 /* init dig PHYs, disp eng pll */ 1714 if (rdev->is_atom_bios) { 1715 radeon_atom_encoder_init(rdev); 1716 radeon_atom_disp_eng_pll_init(rdev); 1717 /* turn on the BL */ 1718 if (rdev->mode_info.bl_encoder) { 1719 u8 bl_level = radeon_get_backlight_level(rdev, 1720 rdev->mode_info.bl_encoder); 1721 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1722 bl_level); 1723 } 1724 } 1725 /* reset hpd state */ 1726 radeon_hpd_init(rdev); 1727 /* blat the mode back in */ 1728 if (fbcon) { 1729 drm_helper_resume_force_mode(dev); 1730 /* turn on display hw */ 1731 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1732 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1733 } 1734 } 1735 1736 drm_kms_helper_poll_enable(dev); 1737 1738 /* set the power state here in case we are a PX system or headless */ 1739 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1740 radeon_pm_compute_clocks(rdev); 1741 1742 if (fbcon) { 1743 radeon_fbdev_set_suspend(rdev, 0); 1744 console_unlock(); 1745 } 1746 1747 return 0; 1748} 1749 1750/** 1751 * radeon_gpu_reset - reset the asic 1752 * 1753 * @rdev: radeon device pointer 1754 * 1755 * Attempt the reset the GPU if it has hung (all asics). 1756 * Returns 0 for success or an error on failure. 1757 */ 1758int radeon_gpu_reset(struct radeon_device *rdev) 1759{ 1760 unsigned ring_sizes[RADEON_NUM_RINGS]; 1761 uint32_t *ring_data[RADEON_NUM_RINGS]; 1762 1763 bool saved = false; 1764 1765 int i, r; 1766 int resched; 1767 1768 down_write(&rdev->exclusive_lock); 1769 1770 if (!rdev->needs_reset) { 1771 up_write(&rdev->exclusive_lock); 1772 return 0; 1773 } 1774 1775 radeon_save_bios_scratch_regs(rdev); 1776 /* block TTM */ 1777 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1778 radeon_suspend(rdev); 1779 radeon_hpd_fini(rdev); 1780 1781 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1782 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], 1783 &ring_data[i]); 1784 if (ring_sizes[i]) { 1785 saved = true; 1786 dev_info(rdev->dev, "Saved %d dwords of commands " 1787 "on ring %d.\n", ring_sizes[i], i); 1788 } 1789 } 1790 1791 r = radeon_asic_reset(rdev); 1792 if (!r) { 1793 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); 1794 radeon_resume(rdev); 1795 } 1796 1797 radeon_restore_bios_scratch_regs(rdev); 1798 1799 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1800 if (!r && ring_data[i]) { 1801 radeon_ring_restore(rdev, &rdev->ring[i], 1802 ring_sizes[i], ring_data[i]); 1803 } else { 1804 radeon_fence_driver_force_completion(rdev, i); 1805 kfree(ring_data[i]); 1806 } 1807 } 1808 1809 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1810 /* do dpm late init */ 1811 r = radeon_pm_late_init(rdev); 1812 if (r) { 1813 rdev->pm.dpm_enabled = false; 1814 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1815 } 1816 } else { 1817 /* resume old pm late */ 1818 radeon_pm_resume(rdev); 1819 } 1820 1821 /* init dig PHYs, disp eng pll */ 1822 if (rdev->is_atom_bios) { 1823 radeon_atom_encoder_init(rdev); 1824 radeon_atom_disp_eng_pll_init(rdev); 1825 /* turn on the BL */ 1826 if (rdev->mode_info.bl_encoder) { 1827 u8 bl_level = radeon_get_backlight_level(rdev, 1828 rdev->mode_info.bl_encoder); 1829 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1830 bl_level); 1831 } 1832 } 1833 /* reset hpd state */ 1834 radeon_hpd_init(rdev); 1835 1836 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1837 1838 rdev->in_reset = true; 1839 rdev->needs_reset = false; 1840 1841 downgrade_write(&rdev->exclusive_lock); 1842 1843 drm_helper_resume_force_mode(rdev->ddev); 1844 1845 /* set the power state here in case we are a PX system or headless */ 1846 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1847 radeon_pm_compute_clocks(rdev); 1848 1849 if (!r) { 1850 r = radeon_ib_ring_tests(rdev); 1851 if (r && saved) 1852 r = -EAGAIN; 1853 } else { 1854 /* bad news, how to tell it to userspace ? */ 1855 dev_info(rdev->dev, "GPU reset failed\n"); 1856 } 1857 1858 rdev->needs_reset = r == -EAGAIN; 1859 rdev->in_reset = false; 1860 1861 up_read(&rdev->exclusive_lock); 1862 return r; 1863} 1864 1865 1866/* 1867 * Debugfs 1868 */ 1869int radeon_debugfs_add_files(struct radeon_device *rdev, 1870 struct drm_info_list *files, 1871 unsigned nfiles) 1872{ 1873 unsigned i; 1874 1875 for (i = 0; i < rdev->debugfs_count; i++) { 1876 if (rdev->debugfs[i].files == files) { 1877 /* Already registered */ 1878 return 0; 1879 } 1880 } 1881 1882 i = rdev->debugfs_count + 1; 1883 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { 1884 DRM_ERROR("Reached maximum number of debugfs components.\n"); 1885 DRM_ERROR("Report so we increase " 1886 "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); 1887 return -EINVAL; 1888 } 1889 rdev->debugfs[rdev->debugfs_count].files = files; 1890 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; 1891 rdev->debugfs_count = i; 1892#if defined(CONFIG_DEBUG_FS) 1893 drm_debugfs_create_files(files, nfiles, 1894 rdev->ddev->control->debugfs_root, 1895 rdev->ddev->control); 1896 drm_debugfs_create_files(files, nfiles, 1897 rdev->ddev->primary->debugfs_root, 1898 rdev->ddev->primary); 1899#endif 1900 return 0; 1901} 1902 1903static void radeon_debugfs_remove_files(struct radeon_device *rdev) 1904{ 1905#if defined(CONFIG_DEBUG_FS) 1906 unsigned i; 1907 1908 for (i = 0; i < rdev->debugfs_count; i++) { 1909 drm_debugfs_remove_files(rdev->debugfs[i].files, 1910 rdev->debugfs[i].num_files, 1911 rdev->ddev->control); 1912 drm_debugfs_remove_files(rdev->debugfs[i].files, 1913 rdev->debugfs[i].num_files, 1914 rdev->ddev->primary); 1915 } 1916#endif 1917} 1918 1919#if defined(CONFIG_DEBUG_FS) 1920int radeon_debugfs_init(struct drm_minor *minor) 1921{ 1922 return 0; 1923} 1924 1925void radeon_debugfs_cleanup(struct drm_minor *minor) 1926{ 1927} 1928#endif 1929