1/*
2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13 * for more details.
14 */
15#ifndef __IPU_PRV_H__
16#define __IPU_PRV_H__
17
18struct ipu_soc;
19
20#include <linux/types.h>
21#include <linux/device.h>
22#include <linux/clk.h>
23#include <linux/platform_device.h>
24
25#include <video/imx-ipu-v3.h>
26
27#define IPU_MCU_T_DEFAULT	8
28#define IPU_CM_IDMAC_REG_OFS	0x00008000
29#define IPU_CM_IC_REG_OFS	0x00020000
30#define IPU_CM_IRT_REG_OFS	0x00028000
31#define IPU_CM_CSI0_REG_OFS	0x00030000
32#define IPU_CM_CSI1_REG_OFS	0x00038000
33#define IPU_CM_SMFC_REG_OFS	0x00050000
34#define IPU_CM_DC_REG_OFS	0x00058000
35#define IPU_CM_DMFC_REG_OFS	0x00060000
36
37/* Register addresses */
38/* IPU Common registers */
39#define IPU_CM_REG(offset)	(offset)
40
41#define IPU_CONF			IPU_CM_REG(0)
42
43#define IPU_SRM_PRI1			IPU_CM_REG(0x00a0)
44#define IPU_SRM_PRI2			IPU_CM_REG(0x00a4)
45#define IPU_FS_PROC_FLOW1		IPU_CM_REG(0x00a8)
46#define IPU_FS_PROC_FLOW2		IPU_CM_REG(0x00ac)
47#define IPU_FS_PROC_FLOW3		IPU_CM_REG(0x00b0)
48#define IPU_FS_DISP_FLOW1		IPU_CM_REG(0x00b4)
49#define IPU_FS_DISP_FLOW2		IPU_CM_REG(0x00b8)
50#define IPU_SKIP			IPU_CM_REG(0x00bc)
51#define IPU_DISP_ALT_CONF		IPU_CM_REG(0x00c0)
52#define IPU_DISP_GEN			IPU_CM_REG(0x00c4)
53#define IPU_DISP_ALT1			IPU_CM_REG(0x00c8)
54#define IPU_DISP_ALT2			IPU_CM_REG(0x00cc)
55#define IPU_DISP_ALT3			IPU_CM_REG(0x00d0)
56#define IPU_DISP_ALT4			IPU_CM_REG(0x00d4)
57#define IPU_SNOOP			IPU_CM_REG(0x00d8)
58#define IPU_MEM_RST			IPU_CM_REG(0x00dc)
59#define IPU_PM				IPU_CM_REG(0x00e0)
60#define IPU_GPR				IPU_CM_REG(0x00e4)
61#define IPU_CHA_DB_MODE_SEL(ch)		IPU_CM_REG(0x0150 + 4 * ((ch) / 32))
62#define IPU_ALT_CHA_DB_MODE_SEL(ch)	IPU_CM_REG(0x0168 + 4 * ((ch) / 32))
63#define IPU_CHA_CUR_BUF(ch)		IPU_CM_REG(0x023C + 4 * ((ch) / 32))
64#define IPU_ALT_CUR_BUF0		IPU_CM_REG(0x0244)
65#define IPU_ALT_CUR_BUF1		IPU_CM_REG(0x0248)
66#define IPU_SRM_STAT			IPU_CM_REG(0x024C)
67#define IPU_PROC_TASK_STAT		IPU_CM_REG(0x0250)
68#define IPU_DISP_TASK_STAT		IPU_CM_REG(0x0254)
69#define IPU_CHA_BUF0_RDY(ch)		IPU_CM_REG(0x0268 + 4 * ((ch) / 32))
70#define IPU_CHA_BUF1_RDY(ch)		IPU_CM_REG(0x0270 + 4 * ((ch) / 32))
71#define IPU_CHA_BUF2_RDY(ch)		IPU_CM_REG(0x0288 + 4 * ((ch) / 32))
72#define IPU_ALT_CHA_BUF0_RDY(ch)	IPU_CM_REG(0x0278 + 4 * ((ch) / 32))
73#define IPU_ALT_CHA_BUF1_RDY(ch)	IPU_CM_REG(0x0280 + 4 * ((ch) / 32))
74
75#define IPU_INT_CTRL(n)		IPU_CM_REG(0x003C + 4 * (n))
76#define IPU_INT_STAT(n)		IPU_CM_REG(0x0200 + 4 * (n))
77
78#define IPU_DI0_COUNTER_RELEASE			(1 << 24)
79#define IPU_DI1_COUNTER_RELEASE			(1 << 25)
80
81#define IPU_IDMAC_REG(offset)	(offset)
82
83#define IDMAC_CONF			IPU_IDMAC_REG(0x0000)
84#define IDMAC_CHA_EN(ch)		IPU_IDMAC_REG(0x0004 + 4 * ((ch) / 32))
85#define IDMAC_SEP_ALPHA			IPU_IDMAC_REG(0x000c)
86#define IDMAC_ALT_SEP_ALPHA		IPU_IDMAC_REG(0x0010)
87#define IDMAC_CHA_PRI(ch)		IPU_IDMAC_REG(0x0014 + 4 * ((ch) / 32))
88#define IDMAC_WM_EN(ch)			IPU_IDMAC_REG(0x001c + 4 * ((ch) / 32))
89#define IDMAC_CH_LOCK_EN_1		IPU_IDMAC_REG(0x0024)
90#define IDMAC_CH_LOCK_EN_2		IPU_IDMAC_REG(0x0028)
91#define IDMAC_SUB_ADDR_0		IPU_IDMAC_REG(0x002c)
92#define IDMAC_SUB_ADDR_1		IPU_IDMAC_REG(0x0030)
93#define IDMAC_SUB_ADDR_2		IPU_IDMAC_REG(0x0034)
94#define IDMAC_BAND_EN(ch)		IPU_IDMAC_REG(0x0040 + 4 * ((ch) / 32))
95#define IDMAC_CHA_BUSY(ch)		IPU_IDMAC_REG(0x0100 + 4 * ((ch) / 32))
96
97#define IPU_NUM_IRQS	(32 * 15)
98
99enum ipu_modules {
100	IPU_CONF_CSI0_EN		= (1 << 0),
101	IPU_CONF_CSI1_EN		= (1 << 1),
102	IPU_CONF_IC_EN			= (1 << 2),
103	IPU_CONF_ROT_EN			= (1 << 3),
104	IPU_CONF_ISP_EN			= (1 << 4),
105	IPU_CONF_DP_EN			= (1 << 5),
106	IPU_CONF_DI0_EN			= (1 << 6),
107	IPU_CONF_DI1_EN			= (1 << 7),
108	IPU_CONF_SMFC_EN		= (1 << 8),
109	IPU_CONF_DC_EN			= (1 << 9),
110	IPU_CONF_DMFC_EN		= (1 << 10),
111
112	IPU_CONF_VDI_EN			= (1 << 12),
113
114	IPU_CONF_IDMAC_DIS		= (1 << 22),
115
116	IPU_CONF_IC_DMFC_SEL		= (1 << 25),
117	IPU_CONF_IC_DMFC_SYNC		= (1 << 26),
118	IPU_CONF_VDI_DMFC_SYNC		= (1 << 27),
119
120	IPU_CONF_CSI0_DATA_SOURCE	= (1 << 28),
121	IPU_CONF_CSI1_DATA_SOURCE	= (1 << 29),
122	IPU_CONF_IC_INPUT		= (1 << 30),
123	IPU_CONF_CSI_SEL		= (1 << 31),
124};
125
126struct ipuv3_channel {
127	unsigned int num;
128
129	bool enabled;
130	bool busy;
131
132	struct ipu_soc *ipu;
133};
134
135struct ipu_cpmem;
136struct ipu_csi;
137struct ipu_dc_priv;
138struct ipu_dmfc_priv;
139struct ipu_di;
140struct ipu_ic_priv;
141struct ipu_smfc_priv;
142
143struct ipu_devtype;
144
145struct ipu_soc {
146	struct device		*dev;
147	const struct ipu_devtype	*devtype;
148	enum ipuv3_type		ipu_type;
149	spinlock_t		lock;
150	struct mutex		channel_lock;
151
152	void __iomem		*cm_reg;
153	void __iomem		*idmac_reg;
154
155	int			usecount;
156
157	struct clk		*clk;
158
159	struct ipuv3_channel	channel[64];
160
161	int			irq_sync;
162	int			irq_err;
163	struct irq_domain	*domain;
164
165	struct ipu_cpmem	*cpmem_priv;
166	struct ipu_dc_priv	*dc_priv;
167	struct ipu_dp_priv	*dp_priv;
168	struct ipu_dmfc_priv	*dmfc_priv;
169	struct ipu_di		*di_priv[2];
170	struct ipu_csi		*csi_priv[2];
171	struct ipu_ic_priv	*ic_priv;
172	struct ipu_smfc_priv	*smfc_priv;
173};
174
175static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
176{
177	return readl(ipu->idmac_reg + offset);
178}
179
180static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
181				   unsigned offset)
182{
183	writel(value, ipu->idmac_reg + offset);
184}
185
186void ipu_srm_dp_sync_update(struct ipu_soc *ipu);
187
188int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
189int ipu_module_disable(struct ipu_soc *ipu, u32 mask);
190
191bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno);
192int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms);
193
194int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
195		 unsigned long base, u32 module, struct clk *clk_ipu);
196void ipu_csi_exit(struct ipu_soc *ipu, int id);
197
198int ipu_ic_init(struct ipu_soc *ipu, struct device *dev,
199		unsigned long base, unsigned long tpmem_base);
200void ipu_ic_exit(struct ipu_soc *ipu);
201
202int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
203		unsigned long base, u32 module, struct clk *ipu_clk);
204void ipu_di_exit(struct ipu_soc *ipu, int id);
205
206int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
207		struct clk *ipu_clk);
208void ipu_dmfc_exit(struct ipu_soc *ipu);
209
210int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
211void ipu_dp_exit(struct ipu_soc *ipu);
212
213int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
214		unsigned long template_base);
215void ipu_dc_exit(struct ipu_soc *ipu);
216
217int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
218void ipu_cpmem_exit(struct ipu_soc *ipu);
219
220int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
221void ipu_smfc_exit(struct ipu_soc *ipu);
222
223#endif				/* __IPU_PRV_H__ */
224