1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef _CORESIGHT_CORESIGHT_ETM_H
14#define _CORESIGHT_CORESIGHT_ETM_H
15
16#include <linux/spinlock.h>
17#include "coresight-priv.h"
18
19/*
20 * Device registers:
21 * 0x000 - 0x2FC: Trace         registers
22 * 0x300 - 0x314: Management    registers
23 * 0x318 - 0xEFC: Trace         registers
24 *
25 * Coresight registers
26 * 0xF00 - 0xF9C: Management    registers
27 * 0xFA0 - 0xFA4: Management    registers in PFTv1.0
28 *                Trace         registers in PFTv1.1
29 * 0xFA8 - 0xFFC: Management    registers
30 */
31
32/* Trace registers (0x000-0x2FC) */
33#define ETMCR			0x000
34#define ETMCCR			0x004
35#define ETMTRIGGER		0x008
36#define ETMSR			0x010
37#define ETMSCR			0x014
38#define ETMTSSCR		0x018
39#define ETMTECR2		0x01c
40#define ETMTEEVR		0x020
41#define ETMTECR1		0x024
42#define ETMFFLR			0x02c
43#define ETMACVRn(n)		(0x040 + (n * 4))
44#define ETMACTRn(n)		(0x080 + (n * 4))
45#define ETMCNTRLDVRn(n)		(0x140 + (n * 4))
46#define ETMCNTENRn(n)		(0x150 + (n * 4))
47#define ETMCNTRLDEVRn(n)	(0x160 + (n * 4))
48#define ETMCNTVRn(n)		(0x170 + (n * 4))
49#define ETMSQ12EVR		0x180
50#define ETMSQ21EVR		0x184
51#define ETMSQ23EVR		0x188
52#define ETMSQ31EVR		0x18c
53#define ETMSQ32EVR		0x190
54#define ETMSQ13EVR		0x194
55#define ETMSQR			0x19c
56#define ETMEXTOUTEVRn(n)	(0x1a0 + (n * 4))
57#define ETMCIDCVRn(n)		(0x1b0 + (n * 4))
58#define ETMCIDCMR		0x1bc
59#define ETMIMPSPEC0		0x1c0
60#define ETMIMPSPEC1		0x1c4
61#define ETMIMPSPEC2		0x1c8
62#define ETMIMPSPEC3		0x1cc
63#define ETMIMPSPEC4		0x1d0
64#define ETMIMPSPEC5		0x1d4
65#define ETMIMPSPEC6		0x1d8
66#define ETMIMPSPEC7		0x1dc
67#define ETMSYNCFR		0x1e0
68#define ETMIDR			0x1e4
69#define ETMCCER			0x1e8
70#define ETMEXTINSELR		0x1ec
71#define ETMTESSEICR		0x1f0
72#define ETMEIBCR		0x1f4
73#define ETMTSEVR		0x1f8
74#define ETMAUXCR		0x1fc
75#define ETMTRACEIDR		0x200
76#define ETMVMIDCVR		0x240
77/* Management registers (0x300-0x314) */
78#define ETMOSLAR		0x300
79#define ETMOSLSR		0x304
80#define ETMOSSRR		0x308
81#define ETMPDCR			0x310
82#define ETMPDSR			0x314
83#define ETM_MAX_ADDR_CMP	16
84#define ETM_MAX_CNTR		4
85#define ETM_MAX_CTXID_CMP	3
86
87/* Register definition */
88/* ETMCR - 0x00 */
89#define ETMCR_PWD_DWN		BIT(0)
90#define ETMCR_STALL_MODE	BIT(7)
91#define ETMCR_ETM_PRG		BIT(10)
92#define ETMCR_ETM_EN		BIT(11)
93#define ETMCR_CYC_ACC		BIT(12)
94#define ETMCR_CTXID_SIZE	(BIT(14)|BIT(15))
95#define ETMCR_TIMESTAMP_EN	BIT(28)
96/* ETMCCR - 0x04 */
97#define ETMCCR_FIFOFULL		BIT(23)
98/* ETMPDCR - 0x310 */
99#define ETMPDCR_PWD_UP		BIT(3)
100/* ETMTECR1 - 0x024 */
101#define ETMTECR1_ADDR_COMP_1	BIT(0)
102#define ETMTECR1_INC_EXC	BIT(24)
103#define ETMTECR1_START_STOP	BIT(25)
104/* ETMCCER - 0x1E8 */
105#define ETMCCER_TIMESTAMP	BIT(22)
106
107#define ETM_MODE_EXCLUDE	BIT(0)
108#define ETM_MODE_CYCACC		BIT(1)
109#define ETM_MODE_STALL		BIT(2)
110#define ETM_MODE_TIMESTAMP	BIT(3)
111#define ETM_MODE_CTXID		BIT(4)
112#define ETM_MODE_ALL		0x1f
113
114#define ETM_SQR_MASK		0x3
115#define ETM_TRACEID_MASK	0x3f
116#define ETM_EVENT_MASK		0x1ffff
117#define ETM_SYNC_MASK		0xfff
118#define ETM_ALL_MASK		0xffffffff
119
120#define ETMSR_PROG_BIT		1
121#define ETM_SEQ_STATE_MAX_VAL	(0x2)
122#define PORT_SIZE_MASK		(GENMASK(21, 21) | GENMASK(6, 4))
123
124#define ETM_HARD_WIRE_RES_A	/* Hard wired, always true */	\
125				((0x0f << 0)	|		\
126				/* Resource index A */		\
127				(0x06 << 4))
128
129#define ETM_ADD_COMP_0		/* Single addr comparator 1 */	\
130				((0x00 << 7)	|		\
131				/* Resource index B */		\
132				(0x00 << 11))
133
134#define ETM_EVENT_NOT_A		BIT(14) /* NOT(A) */
135
136#define ETM_DEFAULT_EVENT_VAL	(ETM_HARD_WIRE_RES_A	|	\
137				 ETM_ADD_COMP_0		|	\
138				 ETM_EVENT_NOT_A)
139/**
140 * struct etm_drvdata - specifics associated to an ETM component
141 * @base:	memory mapped base address for this component.
142 * @dev:	the device entity associated to this component.
143 * @csdev:	component vitals needed by the framework.
144 * @clk:	the clock this component is associated to.
145 * @spinlock:	only one at a time pls.
146 * @cpu:	the cpu this component is affined to.
147 * @port_size:	port size as reported by ETMCR bit 4-6 and 21.
148 * @arch:	ETM/PTM version number.
149 * @use_cpu14:	true if management registers need to be accessed via CP14.
150 * @enable:	is this ETM/PTM currently tracing.
151 * @sticky_enable: true if ETM base configuration has been done.
152 * @boot_enable:true if we should start tracing at boot time.
153 * @os_unlock:	true if access to management registers is allowed.
154 * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR.
155 * @nr_cntr:	Number of counters as found in ETMCCR bit 13-15.
156 * @nr_ext_inp:	Number of external input as found in ETMCCR bit 17-19.
157 * @nr_ext_out:	Number of external output as found in ETMCCR bit 20-22.
158 * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25.
159 * @etmccr:	value of register ETMCCR.
160 * @etmccer:	value of register ETMCCER.
161 * @traceid:	value of the current ID for this component.
162 * @mode:	controls various modes supported by this ETM/PTM.
163 * @ctrl:	used in conjunction with @mode.
164 * @trigger_event: setting for register ETMTRIGGER.
165 * @startstop_ctrl: setting for register ETMTSSCR.
166 * @enable_event: setting for register ETMTEEVR.
167 * @enable_ctrl1: setting for register ETMTECR1.
168 * @fifofull_level: setting for register ETMFFLR.
169 * @addr_idx:	index for the address comparator selection.
170 * @addr_val:	value for address comparator register.
171 * @addr_acctype: access type for address comparator register.
172 * @addr_type:	current status of the comparator register.
173 * @cntr_idx:	index for the counter register selection.
174 * @cntr_rld_val: reload value of a counter register.
175 * @cntr_event:	control for counter enable register.
176 * @cntr_rld_event: value for counter reload event register.
177 * @cntr_val:	counter value register.
178 * @seq_12_event: event causing the transition from 1 to 2.
179 * @seq_21_event: event causing the transition from 2 to 1.
180 * @seq_23_event: event causing the transition from 2 to 3.
181 * @seq_31_event: event causing the transition from 3 to 1.
182 * @seq_32_event: event causing the transition from 3 to 2.
183 * @seq_13_event: event causing the transition from 1 to 3.
184 * @seq_curr_state: current value of the sequencer register.
185 * @ctxid_idx: index for the context ID registers.
186 * @ctxid_val: value for the context ID to trigger on.
187 * @ctxid_mask: mask applicable to all the context IDs.
188 * @sync_freq:	Synchronisation frequency.
189 * @timestamp_event: Defines an event that requests the insertion
190		     of a timestamp into the trace stream.
191 */
192struct etm_drvdata {
193	void __iomem			*base;
194	struct device			*dev;
195	struct coresight_device		*csdev;
196	struct clk			*clk;
197	spinlock_t			spinlock;
198	int				cpu;
199	int				port_size;
200	u8				arch;
201	bool				use_cp14;
202	bool				enable;
203	bool				sticky_enable;
204	bool				boot_enable;
205	bool				os_unlock;
206	u8				nr_addr_cmp;
207	u8				nr_cntr;
208	u8				nr_ext_inp;
209	u8				nr_ext_out;
210	u8				nr_ctxid_cmp;
211	u32				etmccr;
212	u32				etmccer;
213	u32				traceid;
214	u32				mode;
215	u32				ctrl;
216	u32				trigger_event;
217	u32				startstop_ctrl;
218	u32				enable_event;
219	u32				enable_ctrl1;
220	u32				fifofull_level;
221	u8				addr_idx;
222	u32				addr_val[ETM_MAX_ADDR_CMP];
223	u32				addr_acctype[ETM_MAX_ADDR_CMP];
224	u32				addr_type[ETM_MAX_ADDR_CMP];
225	u8				cntr_idx;
226	u32				cntr_rld_val[ETM_MAX_CNTR];
227	u32				cntr_event[ETM_MAX_CNTR];
228	u32				cntr_rld_event[ETM_MAX_CNTR];
229	u32				cntr_val[ETM_MAX_CNTR];
230	u32				seq_12_event;
231	u32				seq_21_event;
232	u32				seq_23_event;
233	u32				seq_31_event;
234	u32				seq_32_event;
235	u32				seq_13_event;
236	u32				seq_curr_state;
237	u8				ctxid_idx;
238	u32				ctxid_val[ETM_MAX_CTXID_CMP];
239	u32				ctxid_mask;
240	u32				sync_freq;
241	u32				timestamp_event;
242};
243
244enum etm_addr_type {
245	ETM_ADDR_TYPE_NONE,
246	ETM_ADDR_TYPE_SINGLE,
247	ETM_ADDR_TYPE_RANGE,
248	ETM_ADDR_TYPE_START,
249	ETM_ADDR_TYPE_STOP,
250};
251#endif
252