1/*
2 * Xilinx XADC driver
3 *
4 * Copyright 2013 Analog Devices Inc.
5 *  Author: Lars-Peter Clauen <lars@metafoo.de>
6 *
7 * Licensed under the GPL-2.
8 */
9
10#ifndef __IIO_XILINX_XADC__
11#define __IIO_XILINX_XADC__
12
13#include <linux/interrupt.h>
14#include <linux/mutex.h>
15#include <linux/spinlock.h>
16
17struct iio_dev;
18struct clk;
19struct xadc_ops;
20struct platform_device;
21
22void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events);
23
24int xadc_read_event_config(struct iio_dev *indio_dev,
25	const struct iio_chan_spec *chan, enum iio_event_type type,
26	enum iio_event_direction dir);
27int xadc_write_event_config(struct iio_dev *indio_dev,
28	const struct iio_chan_spec *chan, enum iio_event_type type,
29	enum iio_event_direction dir, int state);
30int xadc_read_event_value(struct iio_dev *indio_dev,
31	const struct iio_chan_spec *chan, enum iio_event_type type,
32	enum iio_event_direction dir, enum iio_event_info info,
33	int *val, int *val2);
34int xadc_write_event_value(struct iio_dev *indio_dev,
35	const struct iio_chan_spec *chan, enum iio_event_type type,
36	enum iio_event_direction dir, enum iio_event_info info,
37	int val, int val2);
38
39enum xadc_external_mux_mode {
40	XADC_EXTERNAL_MUX_NONE,
41	XADC_EXTERNAL_MUX_SINGLE,
42	XADC_EXTERNAL_MUX_DUAL,
43};
44
45struct xadc {
46	void __iomem *base;
47	struct clk *clk;
48
49	const struct xadc_ops *ops;
50
51	uint16_t threshold[16];
52	uint16_t temp_hysteresis;
53	unsigned int alarm_mask;
54
55	uint16_t *data;
56
57	struct iio_trigger *trigger;
58	struct iio_trigger *convst_trigger;
59	struct iio_trigger *samplerate_trigger;
60
61	enum xadc_external_mux_mode external_mux_mode;
62
63	unsigned int zynq_alarm;
64	unsigned int zynq_masked_alarm;
65	unsigned int zynq_intmask;
66	struct delayed_work zynq_unmask_work;
67
68	struct mutex mutex;
69	spinlock_t lock;
70
71	struct completion completion;
72};
73
74struct xadc_ops {
75	int (*read)(struct xadc *, unsigned int, uint16_t *);
76	int (*write)(struct xadc *, unsigned int, uint16_t);
77	int (*setup)(struct platform_device *pdev, struct iio_dev *indio_dev,
78			int irq);
79	void (*update_alarm)(struct xadc *, unsigned int);
80	unsigned long (*get_dclk_rate)(struct xadc *);
81	irqreturn_t (*interrupt_handler)(int, void *);
82	irqreturn_t (*threaded_interrupt_handler)(int, void *);
83
84	unsigned int flags;
85};
86
87static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
88	uint16_t *val)
89{
90	lockdep_assert_held(&xadc->mutex);
91	return xadc->ops->read(xadc, reg, val);
92}
93
94static inline int _xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
95	uint16_t val)
96{
97	lockdep_assert_held(&xadc->mutex);
98	return xadc->ops->write(xadc, reg, val);
99}
100
101static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
102	uint16_t *val)
103{
104	int ret;
105
106	mutex_lock(&xadc->mutex);
107	ret = _xadc_read_adc_reg(xadc, reg, val);
108	mutex_unlock(&xadc->mutex);
109	return ret;
110}
111
112static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
113	uint16_t val)
114{
115	int ret;
116
117	mutex_lock(&xadc->mutex);
118	ret = _xadc_write_adc_reg(xadc, reg, val);
119	mutex_unlock(&xadc->mutex);
120	return ret;
121}
122
123/* XADC hardmacro register definitions */
124#define XADC_REG_TEMP		0x00
125#define XADC_REG_VCCINT		0x01
126#define XADC_REG_VCCAUX		0x02
127#define XADC_REG_VPVN		0x03
128#define XADC_REG_VREFP		0x04
129#define XADC_REG_VREFN		0x05
130#define XADC_REG_VCCBRAM	0x06
131
132#define XADC_REG_VCCPINT	0x0d
133#define XADC_REG_VCCPAUX	0x0e
134#define XADC_REG_VCCO_DDR	0x0f
135#define XADC_REG_VAUX(x)	(0x10 + (x))
136
137#define XADC_REG_MAX_TEMP	0x20
138#define XADC_REG_MAX_VCCINT	0x21
139#define XADC_REG_MAX_VCCAUX	0x22
140#define XADC_REG_MAX_VCCBRAM	0x23
141#define XADC_REG_MIN_TEMP	0x24
142#define XADC_REG_MIN_VCCINT	0x25
143#define XADC_REG_MIN_VCCAUX	0x26
144#define XADC_REG_MIN_VCCBRAM	0x27
145#define XADC_REG_MAX_VCCPINT	0x28
146#define XADC_REG_MAX_VCCPAUX	0x29
147#define XADC_REG_MAX_VCCO_DDR	0x2a
148#define XADC_REG_MIN_VCCPINT	0x2c
149#define XADC_REG_MIN_VCCPAUX	0x2d
150#define XADC_REG_MIN_VCCO_DDR	0x2e
151
152#define XADC_REG_CONF0		0x40
153#define XADC_REG_CONF1		0x41
154#define XADC_REG_CONF2		0x42
155#define XADC_REG_SEQ(x)		(0x48 + (x))
156#define XADC_REG_INPUT_MODE(x)	(0x4c + (x))
157#define XADC_REG_THRESHOLD(x)	(0x50 + (x))
158
159#define XADC_REG_FLAG		0x3f
160
161#define XADC_CONF0_EC			BIT(9)
162#define XADC_CONF0_ACQ			BIT(8)
163#define XADC_CONF0_MUX			BIT(11)
164#define XADC_CONF0_CHAN(x)		(x)
165
166#define XADC_CONF1_SEQ_MASK		(0xf << 12)
167#define XADC_CONF1_SEQ_DEFAULT		(0 << 12)
168#define XADC_CONF1_SEQ_SINGLE_PASS	(1 << 12)
169#define XADC_CONF1_SEQ_CONTINUOUS	(2 << 12)
170#define XADC_CONF1_SEQ_SINGLE_CHANNEL	(3 << 12)
171#define XADC_CONF1_SEQ_SIMULTANEOUS	(4 << 12)
172#define XADC_CONF1_SEQ_INDEPENDENT	(8 << 12)
173#define XADC_CONF1_ALARM_MASK		0x0f0f
174
175#define XADC_CONF2_DIV_MASK	0xff00
176#define XADC_CONF2_DIV_OFFSET	8
177
178#define XADC_CONF2_PD_MASK	(0x3 << 4)
179#define XADC_CONF2_PD_NONE	(0x0 << 4)
180#define XADC_CONF2_PD_ADC_B	(0x2 << 4)
181#define XADC_CONF2_PD_BOTH	(0x3 << 4)
182
183#define XADC_ALARM_TEMP_MASK		BIT(0)
184#define XADC_ALARM_VCCINT_MASK		BIT(1)
185#define XADC_ALARM_VCCAUX_MASK		BIT(2)
186#define XADC_ALARM_OT_MASK		BIT(3)
187#define XADC_ALARM_VCCBRAM_MASK		BIT(4)
188#define XADC_ALARM_VCCPINT_MASK		BIT(5)
189#define XADC_ALARM_VCCPAUX_MASK		BIT(6)
190#define XADC_ALARM_VCCODDR_MASK		BIT(7)
191
192#define XADC_THRESHOLD_TEMP_MAX		0x0
193#define XADC_THRESHOLD_VCCINT_MAX	0x1
194#define XADC_THRESHOLD_VCCAUX_MAX	0x2
195#define XADC_THRESHOLD_OT_MAX		0x3
196#define XADC_THRESHOLD_TEMP_MIN		0x4
197#define XADC_THRESHOLD_VCCINT_MIN	0x5
198#define XADC_THRESHOLD_VCCAUX_MIN	0x6
199#define XADC_THRESHOLD_OT_MIN		0x7
200#define XADC_THRESHOLD_VCCBRAM_MAX	0x8
201#define XADC_THRESHOLD_VCCPINT_MAX	0x9
202#define XADC_THRESHOLD_VCCPAUX_MAX	0xa
203#define XADC_THRESHOLD_VCCODDR_MAX	0xb
204#define XADC_THRESHOLD_VCCBRAM_MIN	0xc
205#define XADC_THRESHOLD_VCCPINT_MIN	0xd
206#define XADC_THRESHOLD_VCCPAUX_MIN	0xe
207#define XADC_THRESHOLD_VCCODDR_MIN	0xf
208
209#endif
210