1/*
2 * omap iommu: main structures
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef _OMAP_IOMMU_H
14#define _OMAP_IOMMU_H
15
16struct iotlb_entry {
17	u32 da;
18	u32 pa;
19	u32 pgsz, prsvd, valid;
20	union {
21		u16 ap;
22		struct {
23			u32 endian, elsz, mixed;
24		};
25	};
26};
27
28struct omap_iommu {
29	const char	*name;
30	void __iomem	*regbase;
31	struct device	*dev;
32	struct iommu_domain *domain;
33	struct dentry	*debug_dir;
34
35	spinlock_t	iommu_lock;	/* global for this whole object */
36
37	/*
38	 * We don't change iopgd for a situation like pgd for a task,
39	 * but share it globally for each iommu.
40	 */
41	u32		*iopgd;
42	spinlock_t	page_table_lock; /* protect iopgd */
43
44	int		nr_tlb_entries;
45
46	void *ctx; /* iommu context: registres saved area */
47
48	int has_bus_err_back;
49};
50
51struct cr_regs {
52	union {
53		struct {
54			u16 cam_l;
55			u16 cam_h;
56		};
57		u32 cam;
58	};
59	union {
60		struct {
61			u16 ram_l;
62			u16 ram_h;
63		};
64		u32 ram;
65	};
66};
67
68/**
69 * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
70 * @dev: iommu client device
71 */
72static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
73{
74	struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
75
76	return arch_data->iommu_dev;
77}
78
79/*
80 * MMU Register offsets
81 */
82#define MMU_REVISION		0x00
83#define MMU_IRQSTATUS		0x18
84#define MMU_IRQENABLE		0x1c
85#define MMU_WALKING_ST		0x40
86#define MMU_CNTL		0x44
87#define MMU_FAULT_AD		0x48
88#define MMU_TTB			0x4c
89#define MMU_LOCK		0x50
90#define MMU_LD_TLB		0x54
91#define MMU_CAM			0x58
92#define MMU_RAM			0x5c
93#define MMU_GFLUSH		0x60
94#define MMU_FLUSH_ENTRY		0x64
95#define MMU_READ_CAM		0x68
96#define MMU_READ_RAM		0x6c
97#define MMU_EMU_FAULT_AD	0x70
98#define MMU_GP_REG		0x88
99
100#define MMU_REG_SIZE		256
101
102/*
103 * MMU Register bit definitions
104 */
105/* IRQSTATUS & IRQENABLE */
106#define MMU_IRQ_MULTIHITFAULT	(1 << 4)
107#define MMU_IRQ_TABLEWALKFAULT	(1 << 3)
108#define MMU_IRQ_EMUMISS		(1 << 2)
109#define MMU_IRQ_TRANSLATIONFAULT	(1 << 1)
110#define MMU_IRQ_TLBMISS		(1 << 0)
111
112#define __MMU_IRQ_FAULT		\
113	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
114#define MMU_IRQ_MASK		\
115	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
116#define MMU_IRQ_TWL_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
117#define MMU_IRQ_TLB_MISS_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
118
119/* MMU_CNTL */
120#define MMU_CNTL_SHIFT		1
121#define MMU_CNTL_MASK		(7 << MMU_CNTL_SHIFT)
122#define MMU_CNTL_EML_TLB	(1 << 3)
123#define MMU_CNTL_TWL_EN		(1 << 2)
124#define MMU_CNTL_MMU_EN		(1 << 1)
125
126/* CAM */
127#define MMU_CAM_VATAG_SHIFT	12
128#define MMU_CAM_VATAG_MASK \
129	((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
130#define MMU_CAM_P		(1 << 3)
131#define MMU_CAM_V		(1 << 2)
132#define MMU_CAM_PGSZ_MASK	3
133#define MMU_CAM_PGSZ_1M		(0 << 0)
134#define MMU_CAM_PGSZ_64K	(1 << 0)
135#define MMU_CAM_PGSZ_4K		(2 << 0)
136#define MMU_CAM_PGSZ_16M	(3 << 0)
137
138/* RAM */
139#define MMU_RAM_PADDR_SHIFT	12
140#define MMU_RAM_PADDR_MASK \
141	((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
142
143#define MMU_RAM_ENDIAN_SHIFT	9
144#define MMU_RAM_ENDIAN_MASK	(1 << MMU_RAM_ENDIAN_SHIFT)
145#define MMU_RAM_ENDIAN_LITTLE	(0 << MMU_RAM_ENDIAN_SHIFT)
146#define MMU_RAM_ENDIAN_BIG	(1 << MMU_RAM_ENDIAN_SHIFT)
147
148#define MMU_RAM_ELSZ_SHIFT	7
149#define MMU_RAM_ELSZ_MASK	(3 << MMU_RAM_ELSZ_SHIFT)
150#define MMU_RAM_ELSZ_8		(0 << MMU_RAM_ELSZ_SHIFT)
151#define MMU_RAM_ELSZ_16		(1 << MMU_RAM_ELSZ_SHIFT)
152#define MMU_RAM_ELSZ_32		(2 << MMU_RAM_ELSZ_SHIFT)
153#define MMU_RAM_ELSZ_NONE	(3 << MMU_RAM_ELSZ_SHIFT)
154#define MMU_RAM_MIXED_SHIFT	6
155#define MMU_RAM_MIXED_MASK	(1 << MMU_RAM_MIXED_SHIFT)
156#define MMU_RAM_MIXED		MMU_RAM_MIXED_MASK
157
158#define MMU_GP_REG_BUS_ERR_BACK_EN	0x1
159
160#define get_cam_va_mask(pgsz)				\
161	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :	\
162	 ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :	\
163	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
164	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
165
166/*
167 * utilities for super page(16MB, 1MB, 64KB and 4KB)
168 */
169
170#define iopgsz_max(bytes)			\
171	(((bytes) >= SZ_16M) ? SZ_16M :		\
172	 ((bytes) >= SZ_1M)  ? SZ_1M  :		\
173	 ((bytes) >= SZ_64K) ? SZ_64K :		\
174	 ((bytes) >= SZ_4K)  ? SZ_4K  :	0)
175
176#define bytes_to_iopgsz(bytes)				\
177	(((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M :	\
178	 ((bytes) == SZ_1M)  ? MMU_CAM_PGSZ_1M  :	\
179	 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K :	\
180	 ((bytes) == SZ_4K)  ? MMU_CAM_PGSZ_4K  : -1)
181
182#define iopgsz_to_bytes(iopgsz)				\
183	(((iopgsz) == MMU_CAM_PGSZ_16M)	? SZ_16M :	\
184	 ((iopgsz) == MMU_CAM_PGSZ_1M)	? SZ_1M  :	\
185	 ((iopgsz) == MMU_CAM_PGSZ_64K)	? SZ_64K :	\
186	 ((iopgsz) == MMU_CAM_PGSZ_4K)	? SZ_4K  : 0)
187
188#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
189
190/*
191 * global functions
192 */
193#ifdef CONFIG_OMAP_IOMMU_DEBUG
194extern ssize_t
195omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
196extern size_t
197omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
198
199void omap_iommu_debugfs_init(void);
200void omap_iommu_debugfs_exit(void);
201
202void omap_iommu_debugfs_add(struct omap_iommu *obj);
203void omap_iommu_debugfs_remove(struct omap_iommu *obj);
204#else
205static inline void omap_iommu_debugfs_init(void) { }
206static inline void omap_iommu_debugfs_exit(void) { }
207
208static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
209static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
210#endif
211
212/*
213 * register accessors
214 */
215static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
216{
217	return __raw_readl(obj->regbase + offs);
218}
219
220static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
221{
222	__raw_writel(val, obj->regbase + offs);
223}
224
225#endif /* _OMAP_IOMMU_H */
226