1/* 2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18#include <linux/cpu.h> 19#include <linux/cpu_pm.h> 20#include <linux/delay.h> 21#include <linux/interrupt.h> 22#include <linux/of.h> 23#include <linux/of_address.h> 24#include <linux/of_irq.h> 25#include <linux/percpu.h> 26#include <linux/slab.h> 27 28#include <linux/irqchip/arm-gic-v3.h> 29 30#include <asm/cputype.h> 31#include <asm/exception.h> 32#include <asm/smp_plat.h> 33 34#include "irq-gic-common.h" 35#include "irqchip.h" 36 37struct redist_region { 38 void __iomem *redist_base; 39 phys_addr_t phys_base; 40}; 41 42struct gic_chip_data { 43 void __iomem *dist_base; 44 struct redist_region *redist_regions; 45 struct rdists rdists; 46 struct irq_domain *domain; 47 u64 redist_stride; 48 u32 nr_redist_regions; 49 unsigned int irq_nr; 50}; 51 52static struct gic_chip_data gic_data __read_mostly; 53 54#define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 55#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 56#define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 57 58/* Our default, arbitrary priority value. Linux only uses one anyway. */ 59#define DEFAULT_PMR_VALUE 0xf0 60 61static inline unsigned int gic_irq(struct irq_data *d) 62{ 63 return d->hwirq; 64} 65 66static inline int gic_irq_in_rdist(struct irq_data *d) 67{ 68 return gic_irq(d) < 32; 69} 70 71static inline void __iomem *gic_dist_base(struct irq_data *d) 72{ 73 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 74 return gic_data_rdist_sgi_base(); 75 76 if (d->hwirq <= 1023) /* SPI -> dist_base */ 77 return gic_data.dist_base; 78 79 return NULL; 80} 81 82static void gic_do_wait_for_rwp(void __iomem *base) 83{ 84 u32 count = 1000000; /* 1s! */ 85 86 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 87 count--; 88 if (!count) { 89 pr_err_ratelimited("RWP timeout, gone fishing\n"); 90 return; 91 } 92 cpu_relax(); 93 udelay(1); 94 }; 95} 96 97/* Wait for completion of a distributor change */ 98static void gic_dist_wait_for_rwp(void) 99{ 100 gic_do_wait_for_rwp(gic_data.dist_base); 101} 102 103/* Wait for completion of a redistributor change */ 104static void gic_redist_wait_for_rwp(void) 105{ 106 gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 107} 108 109/* Low level accessors */ 110static u64 __maybe_unused gic_read_iar(void) 111{ 112 u64 irqstat; 113 114 asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); 115 return irqstat; 116} 117 118static void __maybe_unused gic_write_pmr(u64 val) 119{ 120 asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val)); 121} 122 123static void __maybe_unused gic_write_ctlr(u64 val) 124{ 125 asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val)); 126 isb(); 127} 128 129static void __maybe_unused gic_write_grpen1(u64 val) 130{ 131 asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val)); 132 isb(); 133} 134 135static void __maybe_unused gic_write_sgi1r(u64 val) 136{ 137 asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); 138} 139 140static void gic_enable_sre(void) 141{ 142 u64 val; 143 144 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); 145 val |= ICC_SRE_EL1_SRE; 146 asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); 147 isb(); 148 149 /* 150 * Need to check that the SRE bit has actually been set. If 151 * not, it means that SRE is disabled at EL2. We're going to 152 * die painfully, and there is nothing we can do about it. 153 * 154 * Kindly inform the luser. 155 */ 156 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); 157 if (!(val & ICC_SRE_EL1_SRE)) 158 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 159} 160 161static void gic_enable_redist(bool enable) 162{ 163 void __iomem *rbase; 164 u32 count = 1000000; /* 1s! */ 165 u32 val; 166 167 rbase = gic_data_rdist_rd_base(); 168 169 val = readl_relaxed(rbase + GICR_WAKER); 170 if (enable) 171 /* Wake up this CPU redistributor */ 172 val &= ~GICR_WAKER_ProcessorSleep; 173 else 174 val |= GICR_WAKER_ProcessorSleep; 175 writel_relaxed(val, rbase + GICR_WAKER); 176 177 if (!enable) { /* Check that GICR_WAKER is writeable */ 178 val = readl_relaxed(rbase + GICR_WAKER); 179 if (!(val & GICR_WAKER_ProcessorSleep)) 180 return; /* No PM support in this redistributor */ 181 } 182 183 while (count--) { 184 val = readl_relaxed(rbase + GICR_WAKER); 185 if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) 186 break; 187 cpu_relax(); 188 udelay(1); 189 }; 190 if (!count) 191 pr_err_ratelimited("redistributor failed to %s...\n", 192 enable ? "wakeup" : "sleep"); 193} 194 195/* 196 * Routines to disable, enable, EOI and route interrupts 197 */ 198static int gic_peek_irq(struct irq_data *d, u32 offset) 199{ 200 u32 mask = 1 << (gic_irq(d) % 32); 201 void __iomem *base; 202 203 if (gic_irq_in_rdist(d)) 204 base = gic_data_rdist_sgi_base(); 205 else 206 base = gic_data.dist_base; 207 208 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 209} 210 211static void gic_poke_irq(struct irq_data *d, u32 offset) 212{ 213 u32 mask = 1 << (gic_irq(d) % 32); 214 void (*rwp_wait)(void); 215 void __iomem *base; 216 217 if (gic_irq_in_rdist(d)) { 218 base = gic_data_rdist_sgi_base(); 219 rwp_wait = gic_redist_wait_for_rwp; 220 } else { 221 base = gic_data.dist_base; 222 rwp_wait = gic_dist_wait_for_rwp; 223 } 224 225 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 226 rwp_wait(); 227} 228 229static void gic_mask_irq(struct irq_data *d) 230{ 231 gic_poke_irq(d, GICD_ICENABLER); 232} 233 234static void gic_unmask_irq(struct irq_data *d) 235{ 236 gic_poke_irq(d, GICD_ISENABLER); 237} 238 239static int gic_irq_set_irqchip_state(struct irq_data *d, 240 enum irqchip_irq_state which, bool val) 241{ 242 u32 reg; 243 244 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 245 return -EINVAL; 246 247 switch (which) { 248 case IRQCHIP_STATE_PENDING: 249 reg = val ? GICD_ISPENDR : GICD_ICPENDR; 250 break; 251 252 case IRQCHIP_STATE_ACTIVE: 253 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 254 break; 255 256 case IRQCHIP_STATE_MASKED: 257 reg = val ? GICD_ICENABLER : GICD_ISENABLER; 258 break; 259 260 default: 261 return -EINVAL; 262 } 263 264 gic_poke_irq(d, reg); 265 return 0; 266} 267 268static int gic_irq_get_irqchip_state(struct irq_data *d, 269 enum irqchip_irq_state which, bool *val) 270{ 271 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 272 return -EINVAL; 273 274 switch (which) { 275 case IRQCHIP_STATE_PENDING: 276 *val = gic_peek_irq(d, GICD_ISPENDR); 277 break; 278 279 case IRQCHIP_STATE_ACTIVE: 280 *val = gic_peek_irq(d, GICD_ISACTIVER); 281 break; 282 283 case IRQCHIP_STATE_MASKED: 284 *val = !gic_peek_irq(d, GICD_ISENABLER); 285 break; 286 287 default: 288 return -EINVAL; 289 } 290 291 return 0; 292} 293 294static void gic_eoi_irq(struct irq_data *d) 295{ 296 gic_write_eoir(gic_irq(d)); 297} 298 299static int gic_set_type(struct irq_data *d, unsigned int type) 300{ 301 unsigned int irq = gic_irq(d); 302 void (*rwp_wait)(void); 303 void __iomem *base; 304 305 /* Interrupt configuration for SGIs can't be changed */ 306 if (irq < 16) 307 return -EINVAL; 308 309 /* SPIs have restrictions on the supported types */ 310 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 311 type != IRQ_TYPE_EDGE_RISING) 312 return -EINVAL; 313 314 if (gic_irq_in_rdist(d)) { 315 base = gic_data_rdist_sgi_base(); 316 rwp_wait = gic_redist_wait_for_rwp; 317 } else { 318 base = gic_data.dist_base; 319 rwp_wait = gic_dist_wait_for_rwp; 320 } 321 322 return gic_configure_irq(irq, type, base, rwp_wait); 323} 324 325static u64 gic_mpidr_to_affinity(u64 mpidr) 326{ 327 u64 aff; 328 329 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 330 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 331 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 332 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 333 334 return aff; 335} 336 337static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 338{ 339 u64 irqnr; 340 341 do { 342 irqnr = gic_read_iar(); 343 344 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 345 int err; 346 err = handle_domain_irq(gic_data.domain, irqnr, regs); 347 if (err) { 348 WARN_ONCE(true, "Unexpected interrupt received!\n"); 349 gic_write_eoir(irqnr); 350 } 351 continue; 352 } 353 if (irqnr < 16) { 354 gic_write_eoir(irqnr); 355#ifdef CONFIG_SMP 356 /* 357 * Unlike GICv2, we don't need an smp_rmb() here. 358 * The control dependency from gic_read_iar to 359 * the ISB in gic_write_eoir is enough to ensure 360 * that any shared data read by handle_IPI will 361 * be read after the ACK. 362 */ 363 handle_IPI(irqnr, regs); 364#else 365 WARN_ONCE(true, "Unexpected SGI received!\n"); 366#endif 367 continue; 368 } 369 } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 370} 371 372static void __init gic_dist_init(void) 373{ 374 unsigned int i; 375 u64 affinity; 376 void __iomem *base = gic_data.dist_base; 377 378 /* Disable the distributor */ 379 writel_relaxed(0, base + GICD_CTLR); 380 gic_dist_wait_for_rwp(); 381 382 /* 383 * Configure SPIs as non-secure Group-1. This will only matter 384 * if the GIC only has a single security state. This will not 385 * do the right thing if the kernel is running in secure mode, 386 * but that's not the intended use case anyway. 387 */ 388 for (i = 32; i < gic_data.irq_nr; i += 32) 389 writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 390 391 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 392 393 /* Enable distributor with ARE, Group1 */ 394 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 395 base + GICD_CTLR); 396 397 /* 398 * Set all global interrupts to the boot CPU only. ARE must be 399 * enabled. 400 */ 401 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 402 for (i = 32; i < gic_data.irq_nr; i++) 403 writeq_relaxed(affinity, base + GICD_IROUTER + i * 8); 404} 405 406static int gic_populate_rdist(void) 407{ 408 u64 mpidr = cpu_logical_map(smp_processor_id()); 409 u64 typer; 410 u32 aff; 411 int i; 412 413 /* 414 * Convert affinity to a 32bit value that can be matched to 415 * GICR_TYPER bits [63:32]. 416 */ 417 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 418 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 419 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 420 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 421 422 for (i = 0; i < gic_data.nr_redist_regions; i++) { 423 void __iomem *ptr = gic_data.redist_regions[i].redist_base; 424 u32 reg; 425 426 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 427 if (reg != GIC_PIDR2_ARCH_GICv3 && 428 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 429 pr_warn("No redistributor present @%p\n", ptr); 430 break; 431 } 432 433 do { 434 typer = readq_relaxed(ptr + GICR_TYPER); 435 if ((typer >> 32) == aff) { 436 u64 offset = ptr - gic_data.redist_regions[i].redist_base; 437 gic_data_rdist_rd_base() = ptr; 438 gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; 439 pr_info("CPU%d: found redistributor %llx region %d:%pa\n", 440 smp_processor_id(), 441 (unsigned long long)mpidr, 442 i, &gic_data_rdist()->phys_base); 443 return 0; 444 } 445 446 if (gic_data.redist_stride) { 447 ptr += gic_data.redist_stride; 448 } else { 449 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 450 if (typer & GICR_TYPER_VLPIS) 451 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 452 } 453 } while (!(typer & GICR_TYPER_LAST)); 454 } 455 456 /* We couldn't even deal with ourselves... */ 457 WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n", 458 smp_processor_id(), (unsigned long long)mpidr); 459 return -ENODEV; 460} 461 462static void gic_cpu_sys_reg_init(void) 463{ 464 /* Enable system registers */ 465 gic_enable_sre(); 466 467 /* Set priority mask register */ 468 gic_write_pmr(DEFAULT_PMR_VALUE); 469 470 /* EOI deactivates interrupt too (mode 0) */ 471 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 472 473 /* ... and let's hit the road... */ 474 gic_write_grpen1(1); 475} 476 477static int gic_dist_supports_lpis(void) 478{ 479 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 480} 481 482static void gic_cpu_init(void) 483{ 484 void __iomem *rbase; 485 486 /* Register ourselves with the rest of the world */ 487 if (gic_populate_rdist()) 488 return; 489 490 gic_enable_redist(true); 491 492 rbase = gic_data_rdist_sgi_base(); 493 494 /* Configure SGIs/PPIs as non-secure Group-1 */ 495 writel_relaxed(~0, rbase + GICR_IGROUPR0); 496 497 gic_cpu_config(rbase, gic_redist_wait_for_rwp); 498 499 /* Give LPIs a spin */ 500 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 501 its_cpu_init(); 502 503 /* initialise system registers */ 504 gic_cpu_sys_reg_init(); 505} 506 507#ifdef CONFIG_SMP 508static int gic_secondary_init(struct notifier_block *nfb, 509 unsigned long action, void *hcpu) 510{ 511 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 512 gic_cpu_init(); 513 return NOTIFY_OK; 514} 515 516/* 517 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 518 * priority because the GIC needs to be up before the ARM generic timers. 519 */ 520static struct notifier_block gic_cpu_notifier = { 521 .notifier_call = gic_secondary_init, 522 .priority = 100, 523}; 524 525static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 526 u64 cluster_id) 527{ 528 int cpu = *base_cpu; 529 u64 mpidr = cpu_logical_map(cpu); 530 u16 tlist = 0; 531 532 while (cpu < nr_cpu_ids) { 533 /* 534 * If we ever get a cluster of more than 16 CPUs, just 535 * scream and skip that CPU. 536 */ 537 if (WARN_ON((mpidr & 0xff) >= 16)) 538 goto out; 539 540 tlist |= 1 << (mpidr & 0xf); 541 542 cpu = cpumask_next(cpu, mask); 543 if (cpu >= nr_cpu_ids) 544 goto out; 545 546 mpidr = cpu_logical_map(cpu); 547 548 if (cluster_id != (mpidr & ~0xffUL)) { 549 cpu--; 550 goto out; 551 } 552 } 553out: 554 *base_cpu = cpu; 555 return tlist; 556} 557 558#define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 559 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 560 << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 561 562static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 563{ 564 u64 val; 565 566 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 567 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 568 irq << ICC_SGI1R_SGI_ID_SHIFT | 569 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 570 tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 571 572 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 573 gic_write_sgi1r(val); 574} 575 576static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 577{ 578 int cpu; 579 580 if (WARN_ON(irq >= 16)) 581 return; 582 583 /* 584 * Ensure that stores to Normal memory are visible to the 585 * other CPUs before issuing the IPI. 586 */ 587 smp_wmb(); 588 589 for_each_cpu(cpu, mask) { 590 u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL; 591 u16 tlist; 592 593 tlist = gic_compute_target_list(&cpu, mask, cluster_id); 594 gic_send_sgi(cluster_id, tlist, irq); 595 } 596 597 /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 598 isb(); 599} 600 601static void gic_smp_init(void) 602{ 603 set_smp_cross_call(gic_raise_softirq); 604 register_cpu_notifier(&gic_cpu_notifier); 605} 606 607static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 608 bool force) 609{ 610 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 611 void __iomem *reg; 612 int enabled; 613 u64 val; 614 615 if (gic_irq_in_rdist(d)) 616 return -EINVAL; 617 618 /* If interrupt was enabled, disable it first */ 619 enabled = gic_peek_irq(d, GICD_ISENABLER); 620 if (enabled) 621 gic_mask_irq(d); 622 623 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 624 val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 625 626 writeq_relaxed(val, reg); 627 628 /* 629 * If the interrupt was enabled, enabled it again. Otherwise, 630 * just wait for the distributor to have digested our changes. 631 */ 632 if (enabled) 633 gic_unmask_irq(d); 634 else 635 gic_dist_wait_for_rwp(); 636 637 return IRQ_SET_MASK_OK; 638} 639#else 640#define gic_set_affinity NULL 641#define gic_smp_init() do { } while(0) 642#endif 643 644#ifdef CONFIG_CPU_PM 645static int gic_cpu_pm_notifier(struct notifier_block *self, 646 unsigned long cmd, void *v) 647{ 648 if (cmd == CPU_PM_EXIT) { 649 gic_enable_redist(true); 650 gic_cpu_sys_reg_init(); 651 } else if (cmd == CPU_PM_ENTER) { 652 gic_write_grpen1(0); 653 gic_enable_redist(false); 654 } 655 return NOTIFY_OK; 656} 657 658static struct notifier_block gic_cpu_pm_notifier_block = { 659 .notifier_call = gic_cpu_pm_notifier, 660}; 661 662static void gic_cpu_pm_init(void) 663{ 664 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 665} 666 667#else 668static inline void gic_cpu_pm_init(void) { } 669#endif /* CONFIG_CPU_PM */ 670 671static struct irq_chip gic_chip = { 672 .name = "GICv3", 673 .irq_mask = gic_mask_irq, 674 .irq_unmask = gic_unmask_irq, 675 .irq_eoi = gic_eoi_irq, 676 .irq_set_type = gic_set_type, 677 .irq_set_affinity = gic_set_affinity, 678 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 679 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 680}; 681 682#define GIC_ID_NR (1U << gic_data.rdists.id_bits) 683 684static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 685 irq_hw_number_t hw) 686{ 687 /* SGIs are private to the core kernel */ 688 if (hw < 16) 689 return -EPERM; 690 /* Nothing here */ 691 if (hw >= gic_data.irq_nr && hw < 8192) 692 return -EPERM; 693 /* Off limits */ 694 if (hw >= GIC_ID_NR) 695 return -EPERM; 696 697 /* PPIs */ 698 if (hw < 32) { 699 irq_set_percpu_devid(irq); 700 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 701 handle_percpu_devid_irq, NULL, NULL); 702 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); 703 } 704 /* SPIs */ 705 if (hw >= 32 && hw < gic_data.irq_nr) { 706 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 707 handle_fasteoi_irq, NULL, NULL); 708 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 709 } 710 /* LPIs */ 711 if (hw >= 8192 && hw < GIC_ID_NR) { 712 if (!gic_dist_supports_lpis()) 713 return -EPERM; 714 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 715 handle_fasteoi_irq, NULL, NULL); 716 set_irq_flags(irq, IRQF_VALID); 717 } 718 719 return 0; 720} 721 722static int gic_irq_domain_xlate(struct irq_domain *d, 723 struct device_node *controller, 724 const u32 *intspec, unsigned int intsize, 725 unsigned long *out_hwirq, unsigned int *out_type) 726{ 727 if (d->of_node != controller) 728 return -EINVAL; 729 if (intsize < 3) 730 return -EINVAL; 731 732 switch(intspec[0]) { 733 case 0: /* SPI */ 734 *out_hwirq = intspec[1] + 32; 735 break; 736 case 1: /* PPI */ 737 *out_hwirq = intspec[1] + 16; 738 break; 739 case GIC_IRQ_TYPE_LPI: /* LPI */ 740 *out_hwirq = intspec[1]; 741 break; 742 default: 743 return -EINVAL; 744 } 745 746 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 747 return 0; 748} 749 750static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 751 unsigned int nr_irqs, void *arg) 752{ 753 int i, ret; 754 irq_hw_number_t hwirq; 755 unsigned int type = IRQ_TYPE_NONE; 756 struct of_phandle_args *irq_data = arg; 757 758 ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, 759 irq_data->args_count, &hwirq, &type); 760 if (ret) 761 return ret; 762 763 for (i = 0; i < nr_irqs; i++) 764 gic_irq_domain_map(domain, virq + i, hwirq + i); 765 766 return 0; 767} 768 769static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 770 unsigned int nr_irqs) 771{ 772 int i; 773 774 for (i = 0; i < nr_irqs; i++) { 775 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 776 irq_set_handler(virq + i, NULL); 777 irq_domain_reset_irq_data(d); 778 } 779} 780 781static const struct irq_domain_ops gic_irq_domain_ops = { 782 .xlate = gic_irq_domain_xlate, 783 .alloc = gic_irq_domain_alloc, 784 .free = gic_irq_domain_free, 785}; 786 787static int __init gic_of_init(struct device_node *node, struct device_node *parent) 788{ 789 void __iomem *dist_base; 790 struct redist_region *rdist_regs; 791 u64 redist_stride; 792 u32 nr_redist_regions; 793 u32 typer; 794 u32 reg; 795 int gic_irqs; 796 int err; 797 int i; 798 799 dist_base = of_iomap(node, 0); 800 if (!dist_base) { 801 pr_err("%s: unable to map gic dist registers\n", 802 node->full_name); 803 return -ENXIO; 804 } 805 806 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 807 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) { 808 pr_err("%s: no distributor detected, giving up\n", 809 node->full_name); 810 err = -ENODEV; 811 goto out_unmap_dist; 812 } 813 814 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 815 nr_redist_regions = 1; 816 817 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 818 if (!rdist_regs) { 819 err = -ENOMEM; 820 goto out_unmap_dist; 821 } 822 823 for (i = 0; i < nr_redist_regions; i++) { 824 struct resource res; 825 int ret; 826 827 ret = of_address_to_resource(node, 1 + i, &res); 828 rdist_regs[i].redist_base = of_iomap(node, 1 + i); 829 if (ret || !rdist_regs[i].redist_base) { 830 pr_err("%s: couldn't map region %d\n", 831 node->full_name, i); 832 err = -ENODEV; 833 goto out_unmap_rdist; 834 } 835 rdist_regs[i].phys_base = res.start; 836 } 837 838 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 839 redist_stride = 0; 840 841 gic_data.dist_base = dist_base; 842 gic_data.redist_regions = rdist_regs; 843 gic_data.nr_redist_regions = nr_redist_regions; 844 gic_data.redist_stride = redist_stride; 845 846 /* 847 * Find out how many interrupts are supported. 848 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 849 */ 850 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 851 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 852 gic_irqs = GICD_TYPER_IRQS(typer); 853 if (gic_irqs > 1020) 854 gic_irqs = 1020; 855 gic_data.irq_nr = gic_irqs; 856 857 gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, 858 &gic_data); 859 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 860 861 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 862 err = -ENOMEM; 863 goto out_free; 864 } 865 866 set_handle_irq(gic_handle_irq); 867 868 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 869 its_init(node, &gic_data.rdists, gic_data.domain); 870 871 gic_smp_init(); 872 gic_dist_init(); 873 gic_cpu_init(); 874 gic_cpu_pm_init(); 875 876 return 0; 877 878out_free: 879 if (gic_data.domain) 880 irq_domain_remove(gic_data.domain); 881 free_percpu(gic_data.rdists.rdist); 882out_unmap_rdist: 883 for (i = 0; i < nr_redist_regions; i++) 884 if (rdist_regs[i].redist_base) 885 iounmap(rdist_regs[i].redist_base); 886 kfree(rdist_regs); 887out_unmap_dist: 888 iounmap(dist_base); 889 return err; 890} 891 892IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 893