1/* 2 * V4L2 Driver for PXA camera host 3 * 4 * Copyright (C) 2006, Sascha Hauer, Pengutronix 5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/init.h> 14#include <linux/module.h> 15#include <linux/io.h> 16#include <linux/delay.h> 17#include <linux/dma-mapping.h> 18#include <linux/err.h> 19#include <linux/errno.h> 20#include <linux/fs.h> 21#include <linux/interrupt.h> 22#include <linux/kernel.h> 23#include <linux/mm.h> 24#include <linux/moduleparam.h> 25#include <linux/time.h> 26#include <linux/device.h> 27#include <linux/platform_device.h> 28#include <linux/clk.h> 29#include <linux/sched.h> 30#include <linux/slab.h> 31 32#include <media/v4l2-common.h> 33#include <media/v4l2-dev.h> 34#include <media/videobuf-dma-sg.h> 35#include <media/soc_camera.h> 36#include <media/soc_mediabus.h> 37#include <media/v4l2-of.h> 38 39#include <linux/videodev2.h> 40 41#include <mach/dma.h> 42#include <linux/platform_data/camera-pxa.h> 43 44#define PXA_CAM_VERSION "0.0.6" 45#define PXA_CAM_DRV_NAME "pxa27x-camera" 46 47/* Camera Interface */ 48#define CICR0 0x0000 49#define CICR1 0x0004 50#define CICR2 0x0008 51#define CICR3 0x000C 52#define CICR4 0x0010 53#define CISR 0x0014 54#define CIFR 0x0018 55#define CITOR 0x001C 56#define CIBR0 0x0028 57#define CIBR1 0x0030 58#define CIBR2 0x0038 59 60#define CICR0_DMAEN (1 << 31) /* DMA request enable */ 61#define CICR0_PAR_EN (1 << 30) /* Parity enable */ 62#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ 63#define CICR0_ENB (1 << 28) /* Camera interface enable */ 64#define CICR0_DIS (1 << 27) /* Camera interface disable */ 65#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ 66#define CICR0_TOM (1 << 9) /* Time-out mask */ 67#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ 68#define CICR0_FEM (1 << 7) /* FIFO-empty mask */ 69#define CICR0_EOLM (1 << 6) /* End-of-line mask */ 70#define CICR0_PERRM (1 << 5) /* Parity-error mask */ 71#define CICR0_QDM (1 << 4) /* Quick-disable mask */ 72#define CICR0_CDM (1 << 3) /* Disable-done mask */ 73#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ 74#define CICR0_EOFM (1 << 1) /* End-of-frame mask */ 75#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ 76 77#define CICR1_TBIT (1 << 31) /* Transparency bit */ 78#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ 79#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ 80#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ 81#define CICR1_RGB_F (1 << 11) /* RGB format */ 82#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ 83#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ 84#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ 85#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ 86#define CICR1_DW (0x7 << 0) /* Data width mask */ 87 88#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock 89 wait count mask */ 90#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock 91 wait count mask */ 92#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ 93#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock 94 wait count mask */ 95#define CICR2_FSW (0x7 << 0) /* Frame stabilization 96 wait count mask */ 97 98#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock 99 wait count mask */ 100#define CICR3_EFW (0xff << 16) /* End-of-frame line clock 101 wait count mask */ 102#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ 103#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock 104 wait count mask */ 105#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ 106 107#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ 108#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ 109#define CICR4_PCP (1 << 22) /* Pixel clock polarity */ 110#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ 111#define CICR4_VSP (1 << 20) /* Vertical sync polarity */ 112#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ 113#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ 114#define CICR4_DIV (0xff << 0) /* Clock divisor mask */ 115 116#define CISR_FTO (1 << 15) /* FIFO time-out */ 117#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ 118#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ 119#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ 120#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ 121#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ 122#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ 123#define CISR_EOL (1 << 8) /* End of line */ 124#define CISR_PAR_ERR (1 << 7) /* Parity error */ 125#define CISR_CQD (1 << 6) /* Camera interface quick disable */ 126#define CISR_CDD (1 << 5) /* Camera interface disable done */ 127#define CISR_SOF (1 << 4) /* Start of frame */ 128#define CISR_EOF (1 << 3) /* End of frame */ 129#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ 130#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ 131#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ 132 133#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ 134#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ 135#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ 136#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ 137#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ 138#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ 139#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ 140#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ 141 142#define CICR0_SIM_MP (0 << 24) 143#define CICR0_SIM_SP (1 << 24) 144#define CICR0_SIM_MS (2 << 24) 145#define CICR0_SIM_EP (3 << 24) 146#define CICR0_SIM_ES (4 << 24) 147 148#define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ 149#define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ 150#define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ 151#define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ 152#define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ 153 154#define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ 155#define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ 156#define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ 157#define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ 158#define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ 159 160#define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ 161#define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ 162#define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ 163#define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ 164 165#define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ 166 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ 167 CICR0_EOFM | CICR0_FOM) 168 169/* 170 * Structures 171 */ 172enum pxa_camera_active_dma { 173 DMA_Y = 0x1, 174 DMA_U = 0x2, 175 DMA_V = 0x4, 176}; 177 178/* descriptor needed for the PXA DMA engine */ 179struct pxa_cam_dma { 180 dma_addr_t sg_dma; 181 struct pxa_dma_desc *sg_cpu; 182 size_t sg_size; 183 int sglen; 184}; 185 186/* buffer for one video frame */ 187struct pxa_buffer { 188 /* common v4l buffer stuff -- must be first */ 189 struct videobuf_buffer vb; 190 u32 code; 191 /* our descriptor lists for Y, U and V channels */ 192 struct pxa_cam_dma dmas[3]; 193 int inwork; 194 enum pxa_camera_active_dma active_dma; 195}; 196 197struct pxa_camera_dev { 198 struct soc_camera_host soc_host; 199 /* 200 * PXA27x is only supposed to handle one camera on its Quick Capture 201 * interface. If anyone ever builds hardware to enable more than 202 * one camera, they will have to modify this driver too 203 */ 204 struct clk *clk; 205 206 unsigned int irq; 207 void __iomem *base; 208 209 int channels; 210 unsigned int dma_chans[3]; 211 212 struct pxacamera_platform_data *pdata; 213 struct resource *res; 214 unsigned long platform_flags; 215 unsigned long ciclk; 216 unsigned long mclk; 217 u32 mclk_divisor; 218 u16 width_flags; /* max 10 bits */ 219 220 struct list_head capture; 221 222 spinlock_t lock; 223 224 struct pxa_buffer *active; 225 struct pxa_dma_desc *sg_tail[3]; 226 227 u32 save_cicr[5]; 228}; 229 230struct pxa_cam { 231 unsigned long flags; 232}; 233 234static const char *pxa_cam_driver_description = "PXA_Camera"; 235 236static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ 237 238/* 239 * Videobuf operations 240 */ 241static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, 242 unsigned int *size) 243{ 244 struct soc_camera_device *icd = vq->priv_data; 245 246 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, *size); 247 248 *size = icd->sizeimage; 249 250 if (0 == *count) 251 *count = 32; 252 if (*size * *count > vid_limit * 1024 * 1024) 253 *count = (vid_limit * 1024 * 1024) / *size; 254 255 return 0; 256} 257 258static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) 259{ 260 struct soc_camera_device *icd = vq->priv_data; 261 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 262 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); 263 int i; 264 265 BUG_ON(in_interrupt()); 266 267 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 268 &buf->vb, buf->vb.baddr, buf->vb.bsize); 269 270 /* 271 * This waits until this buffer is out of danger, i.e., until it is no 272 * longer in STATE_QUEUED or STATE_ACTIVE 273 */ 274 videobuf_waiton(vq, &buf->vb, 0, 0); 275 videobuf_dma_unmap(vq->dev, dma); 276 videobuf_dma_free(dma); 277 278 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) { 279 if (buf->dmas[i].sg_cpu) 280 dma_free_coherent(ici->v4l2_dev.dev, 281 buf->dmas[i].sg_size, 282 buf->dmas[i].sg_cpu, 283 buf->dmas[i].sg_dma); 284 buf->dmas[i].sg_cpu = NULL; 285 } 286 287 buf->vb.state = VIDEOBUF_NEEDS_INIT; 288} 289 290static int calculate_dma_sglen(struct scatterlist *sglist, int sglen, 291 int sg_first_ofs, int size) 292{ 293 int i, offset, dma_len, xfer_len; 294 struct scatterlist *sg; 295 296 offset = sg_first_ofs; 297 for_each_sg(sglist, sg, sglen, i) { 298 dma_len = sg_dma_len(sg); 299 300 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ 301 xfer_len = roundup(min(dma_len - offset, size), 8); 302 303 size = max(0, size - xfer_len); 304 offset = 0; 305 if (size == 0) 306 break; 307 } 308 309 BUG_ON(size != 0); 310 return i + 1; 311} 312 313/** 314 * pxa_init_dma_channel - init dma descriptors 315 * @pcdev: pxa camera device 316 * @buf: pxa buffer to find pxa dma channel 317 * @dma: dma video buffer 318 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V') 319 * @cibr: camera Receive Buffer Register 320 * @size: bytes to transfer 321 * @sg_first: first element of sg_list 322 * @sg_first_ofs: offset in first element of sg_list 323 * 324 * Prepares the pxa dma descriptors to transfer one camera channel. 325 * Beware sg_first and sg_first_ofs are both input and output parameters. 326 * 327 * Returns 0 or -ENOMEM if no coherent memory is available 328 */ 329static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, 330 struct pxa_buffer *buf, 331 struct videobuf_dmabuf *dma, int channel, 332 int cibr, int size, 333 struct scatterlist **sg_first, int *sg_first_ofs) 334{ 335 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel]; 336 struct device *dev = pcdev->soc_host.v4l2_dev.dev; 337 struct scatterlist *sg; 338 int i, offset, sglen; 339 int dma_len = 0, xfer_len = 0; 340 341 if (pxa_dma->sg_cpu) 342 dma_free_coherent(dev, pxa_dma->sg_size, 343 pxa_dma->sg_cpu, pxa_dma->sg_dma); 344 345 sglen = calculate_dma_sglen(*sg_first, dma->sglen, 346 *sg_first_ofs, size); 347 348 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc); 349 pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size, 350 &pxa_dma->sg_dma, GFP_KERNEL); 351 if (!pxa_dma->sg_cpu) 352 return -ENOMEM; 353 354 pxa_dma->sglen = sglen; 355 offset = *sg_first_ofs; 356 357 dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n", 358 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma); 359 360 361 for_each_sg(*sg_first, sg, sglen, i) { 362 dma_len = sg_dma_len(sg); 363 364 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ 365 xfer_len = roundup(min(dma_len - offset, size), 8); 366 367 size = max(0, size - xfer_len); 368 369 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr; 370 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset; 371 pxa_dma->sg_cpu[i].dcmd = 372 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len; 373#ifdef DEBUG 374 if (!i) 375 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN; 376#endif 377 pxa_dma->sg_cpu[i].ddadr = 378 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc); 379 380 dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n", 381 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc), 382 sg_dma_address(sg) + offset, xfer_len); 383 offset = 0; 384 385 if (size == 0) 386 break; 387 } 388 389 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP; 390 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN; 391 392 /* 393 * Handle 1 special case : 394 * - in 3 planes (YUV422P format), we might finish with xfer_len equal 395 * to dma_len (end on PAGE boundary). In this case, the sg element 396 * for next plane should be the next after the last used to store the 397 * last scatter gather RAM page 398 */ 399 if (xfer_len >= dma_len) { 400 *sg_first_ofs = xfer_len - dma_len; 401 *sg_first = sg_next(sg); 402 } else { 403 *sg_first_ofs = xfer_len; 404 *sg_first = sg; 405 } 406 407 return 0; 408} 409 410static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev, 411 struct pxa_buffer *buf) 412{ 413 buf->active_dma = DMA_Y; 414 if (pcdev->channels == 3) 415 buf->active_dma |= DMA_U | DMA_V; 416} 417 418/* 419 * Please check the DMA prepared buffer structure in : 420 * Documentation/video4linux/pxa_camera.txt 421 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain 422 * modification while DMA chain is running will work anyway. 423 */ 424static int pxa_videobuf_prepare(struct videobuf_queue *vq, 425 struct videobuf_buffer *vb, enum v4l2_field field) 426{ 427 struct soc_camera_device *icd = vq->priv_data; 428 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 429 struct pxa_camera_dev *pcdev = ici->priv; 430 struct device *dev = pcdev->soc_host.v4l2_dev.dev; 431 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); 432 int ret; 433 int size_y, size_u = 0, size_v = 0; 434 435 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 436 vb, vb->baddr, vb->bsize); 437 438 /* Added list head initialization on alloc */ 439 WARN_ON(!list_empty(&vb->queue)); 440 441#ifdef DEBUG 442 /* 443 * This can be useful if you want to see if we actually fill 444 * the buffer with something 445 */ 446 memset((void *)vb->baddr, 0xaa, vb->bsize); 447#endif 448 449 BUG_ON(NULL == icd->current_fmt); 450 451 /* 452 * I think, in buf_prepare you only have to protect global data, 453 * the actual buffer is yours 454 */ 455 buf->inwork = 1; 456 457 if (buf->code != icd->current_fmt->code || 458 vb->width != icd->user_width || 459 vb->height != icd->user_height || 460 vb->field != field) { 461 buf->code = icd->current_fmt->code; 462 vb->width = icd->user_width; 463 vb->height = icd->user_height; 464 vb->field = field; 465 vb->state = VIDEOBUF_NEEDS_INIT; 466 } 467 468 vb->size = icd->sizeimage; 469 if (0 != vb->baddr && vb->bsize < vb->size) { 470 ret = -EINVAL; 471 goto out; 472 } 473 474 if (vb->state == VIDEOBUF_NEEDS_INIT) { 475 int size = vb->size; 476 int next_ofs = 0; 477 struct videobuf_dmabuf *dma = videobuf_to_dma(vb); 478 struct scatterlist *sg; 479 480 ret = videobuf_iolock(vq, vb, NULL); 481 if (ret) 482 goto fail; 483 484 if (pcdev->channels == 3) { 485 size_y = size / 2; 486 size_u = size_v = size / 4; 487 } else { 488 size_y = size; 489 } 490 491 sg = dma->sglist; 492 493 /* init DMA for Y channel */ 494 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y, 495 &sg, &next_ofs); 496 if (ret) { 497 dev_err(dev, "DMA initialization for Y/RGB failed\n"); 498 goto fail; 499 } 500 501 /* init DMA for U channel */ 502 if (size_u) 503 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1, 504 size_u, &sg, &next_ofs); 505 if (ret) { 506 dev_err(dev, "DMA initialization for U failed\n"); 507 goto fail_u; 508 } 509 510 /* init DMA for V channel */ 511 if (size_v) 512 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2, 513 size_v, &sg, &next_ofs); 514 if (ret) { 515 dev_err(dev, "DMA initialization for V failed\n"); 516 goto fail_v; 517 } 518 519 vb->state = VIDEOBUF_PREPARED; 520 } 521 522 buf->inwork = 0; 523 pxa_videobuf_set_actdma(pcdev, buf); 524 525 return 0; 526 527fail_v: 528 dma_free_coherent(dev, buf->dmas[1].sg_size, 529 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma); 530fail_u: 531 dma_free_coherent(dev, buf->dmas[0].sg_size, 532 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma); 533fail: 534 free_buffer(vq, buf); 535out: 536 buf->inwork = 0; 537 return ret; 538} 539 540/** 541 * pxa_dma_start_channels - start DMA channel for active buffer 542 * @pcdev: pxa camera device 543 * 544 * Initialize DMA channels to the beginning of the active video buffer, and 545 * start these channels. 546 */ 547static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev) 548{ 549 int i; 550 struct pxa_buffer *active; 551 552 active = pcdev->active; 553 554 for (i = 0; i < pcdev->channels; i++) { 555 dev_dbg(pcdev->soc_host.v4l2_dev.dev, 556 "%s (channel=%d) ddadr=%08x\n", __func__, 557 i, active->dmas[i].sg_dma); 558 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma; 559 DCSR(pcdev->dma_chans[i]) = DCSR_RUN; 560 } 561} 562 563static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev) 564{ 565 int i; 566 567 for (i = 0; i < pcdev->channels; i++) { 568 dev_dbg(pcdev->soc_host.v4l2_dev.dev, 569 "%s (channel=%d)\n", __func__, i); 570 DCSR(pcdev->dma_chans[i]) = 0; 571 } 572} 573 574static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev, 575 struct pxa_buffer *buf) 576{ 577 int i; 578 struct pxa_dma_desc *buf_last_desc; 579 580 for (i = 0; i < pcdev->channels; i++) { 581 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen; 582 buf_last_desc->ddadr = DDADR_STOP; 583 584 if (pcdev->sg_tail[i]) 585 /* Link the new buffer to the old tail */ 586 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma; 587 588 /* Update the channel tail */ 589 pcdev->sg_tail[i] = buf_last_desc; 590 } 591} 592 593/** 594 * pxa_camera_start_capture - start video capturing 595 * @pcdev: camera device 596 * 597 * Launch capturing. DMA channels should not be active yet. They should get 598 * activated at the end of frame interrupt, to capture only whole frames, and 599 * never begin the capture of a partial frame. 600 */ 601static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev) 602{ 603 unsigned long cicr0; 604 605 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); 606 /* Enable End-Of-Frame Interrupt */ 607 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; 608 cicr0 &= ~CICR0_EOFM; 609 __raw_writel(cicr0, pcdev->base + CICR0); 610} 611 612static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev) 613{ 614 unsigned long cicr0; 615 616 pxa_dma_stop_channels(pcdev); 617 618 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; 619 __raw_writel(cicr0, pcdev->base + CICR0); 620 621 pcdev->active = NULL; 622 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); 623} 624 625/* Called under spinlock_irqsave(&pcdev->lock, ...) */ 626static void pxa_videobuf_queue(struct videobuf_queue *vq, 627 struct videobuf_buffer *vb) 628{ 629 struct soc_camera_device *icd = vq->priv_data; 630 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 631 struct pxa_camera_dev *pcdev = ici->priv; 632 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); 633 634 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n", 635 __func__, vb, vb->baddr, vb->bsize, pcdev->active); 636 637 list_add_tail(&vb->queue, &pcdev->capture); 638 639 vb->state = VIDEOBUF_ACTIVE; 640 pxa_dma_add_tail_buf(pcdev, buf); 641 642 if (!pcdev->active) 643 pxa_camera_start_capture(pcdev); 644} 645 646static void pxa_videobuf_release(struct videobuf_queue *vq, 647 struct videobuf_buffer *vb) 648{ 649 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); 650#ifdef DEBUG 651 struct soc_camera_device *icd = vq->priv_data; 652 struct device *dev = icd->parent; 653 654 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 655 vb, vb->baddr, vb->bsize); 656 657 switch (vb->state) { 658 case VIDEOBUF_ACTIVE: 659 dev_dbg(dev, "%s (active)\n", __func__); 660 break; 661 case VIDEOBUF_QUEUED: 662 dev_dbg(dev, "%s (queued)\n", __func__); 663 break; 664 case VIDEOBUF_PREPARED: 665 dev_dbg(dev, "%s (prepared)\n", __func__); 666 break; 667 default: 668 dev_dbg(dev, "%s (unknown)\n", __func__); 669 break; 670 } 671#endif 672 673 free_buffer(vq, buf); 674} 675 676static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, 677 struct videobuf_buffer *vb, 678 struct pxa_buffer *buf) 679{ 680 int i; 681 682 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ 683 list_del_init(&vb->queue); 684 vb->state = VIDEOBUF_DONE; 685 v4l2_get_timestamp(&vb->ts); 686 vb->field_count++; 687 wake_up(&vb->done); 688 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n", 689 __func__, vb); 690 691 if (list_empty(&pcdev->capture)) { 692 pxa_camera_stop_capture(pcdev); 693 for (i = 0; i < pcdev->channels; i++) 694 pcdev->sg_tail[i] = NULL; 695 return; 696 } 697 698 pcdev->active = list_entry(pcdev->capture.next, 699 struct pxa_buffer, vb.queue); 700} 701 702/** 703 * pxa_camera_check_link_miss - check missed DMA linking 704 * @pcdev: camera device 705 * 706 * The DMA chaining is done with DMA running. This means a tiny temporal window 707 * remains, where a buffer is queued on the chain, while the chain is already 708 * stopped. This means the tailed buffer would never be transferred by DMA. 709 * This function restarts the capture for this corner case, where : 710 * - DADR() == DADDR_STOP 711 * - a videobuffer is queued on the pcdev->capture list 712 * 713 * Please check the "DMA hot chaining timeslice issue" in 714 * Documentation/video4linux/pxa_camera.txt 715 * 716 * Context: should only be called within the dma irq handler 717 */ 718static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev) 719{ 720 int i, is_dma_stopped = 1; 721 722 for (i = 0; i < pcdev->channels; i++) 723 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP) 724 is_dma_stopped = 0; 725 dev_dbg(pcdev->soc_host.v4l2_dev.dev, 726 "%s : top queued buffer=%p, dma_stopped=%d\n", 727 __func__, pcdev->active, is_dma_stopped); 728 if (pcdev->active && is_dma_stopped) 729 pxa_camera_start_capture(pcdev); 730} 731 732static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev, 733 enum pxa_camera_active_dma act_dma) 734{ 735 struct device *dev = pcdev->soc_host.v4l2_dev.dev; 736 struct pxa_buffer *buf; 737 unsigned long flags; 738 u32 status, camera_status, overrun; 739 struct videobuf_buffer *vb; 740 741 spin_lock_irqsave(&pcdev->lock, flags); 742 743 status = DCSR(channel); 744 DCSR(channel) = status; 745 746 camera_status = __raw_readl(pcdev->base + CISR); 747 overrun = CISR_IFO_0; 748 if (pcdev->channels == 3) 749 overrun |= CISR_IFO_1 | CISR_IFO_2; 750 751 if (status & DCSR_BUSERR) { 752 dev_err(dev, "DMA Bus Error IRQ!\n"); 753 goto out; 754 } 755 756 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) { 757 dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n", 758 status); 759 goto out; 760 } 761 762 /* 763 * pcdev->active should not be NULL in DMA irq handler. 764 * 765 * But there is one corner case : if capture was stopped due to an 766 * overrun of channel 1, and at that same channel 2 was completed. 767 * 768 * When handling the overrun in DMA irq for channel 1, we'll stop the 769 * capture and restart it (and thus set pcdev->active to NULL). But the 770 * DMA irq handler will already be pending for channel 2. So on entering 771 * the DMA irq handler for channel 2 there will be no active buffer, yet 772 * that is normal. 773 */ 774 if (!pcdev->active) 775 goto out; 776 777 vb = &pcdev->active->vb; 778 buf = container_of(vb, struct pxa_buffer, vb); 779 WARN_ON(buf->inwork || list_empty(&vb->queue)); 780 781 dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n", 782 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "", 783 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel)); 784 785 if (status & DCSR_ENDINTR) { 786 /* 787 * It's normal if the last frame creates an overrun, as there 788 * are no more DMA descriptors to fetch from QCI fifos 789 */ 790 if (camera_status & overrun && 791 !list_is_last(pcdev->capture.next, &pcdev->capture)) { 792 dev_dbg(dev, "FIFO overrun! CISR: %x\n", 793 camera_status); 794 pxa_camera_stop_capture(pcdev); 795 pxa_camera_start_capture(pcdev); 796 goto out; 797 } 798 buf->active_dma &= ~act_dma; 799 if (!buf->active_dma) { 800 pxa_camera_wakeup(pcdev, vb, buf); 801 pxa_camera_check_link_miss(pcdev); 802 } 803 } 804 805out: 806 spin_unlock_irqrestore(&pcdev->lock, flags); 807} 808 809static void pxa_camera_dma_irq_y(int channel, void *data) 810{ 811 struct pxa_camera_dev *pcdev = data; 812 pxa_camera_dma_irq(channel, pcdev, DMA_Y); 813} 814 815static void pxa_camera_dma_irq_u(int channel, void *data) 816{ 817 struct pxa_camera_dev *pcdev = data; 818 pxa_camera_dma_irq(channel, pcdev, DMA_U); 819} 820 821static void pxa_camera_dma_irq_v(int channel, void *data) 822{ 823 struct pxa_camera_dev *pcdev = data; 824 pxa_camera_dma_irq(channel, pcdev, DMA_V); 825} 826 827static struct videobuf_queue_ops pxa_videobuf_ops = { 828 .buf_setup = pxa_videobuf_setup, 829 .buf_prepare = pxa_videobuf_prepare, 830 .buf_queue = pxa_videobuf_queue, 831 .buf_release = pxa_videobuf_release, 832}; 833 834static void pxa_camera_init_videobuf(struct videobuf_queue *q, 835 struct soc_camera_device *icd) 836{ 837 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 838 struct pxa_camera_dev *pcdev = ici->priv; 839 840 /* 841 * We must pass NULL as dev pointer, then all pci_* dma operations 842 * transform to normal dma_* ones. 843 */ 844 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock, 845 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE, 846 sizeof(struct pxa_buffer), icd, &ici->host_lock); 847} 848 849static u32 mclk_get_divisor(struct platform_device *pdev, 850 struct pxa_camera_dev *pcdev) 851{ 852 unsigned long mclk = pcdev->mclk; 853 struct device *dev = &pdev->dev; 854 u32 div; 855 unsigned long lcdclk; 856 857 lcdclk = clk_get_rate(pcdev->clk); 858 pcdev->ciclk = lcdclk; 859 860 /* mclk <= ciclk / 4 (27.4.2) */ 861 if (mclk > lcdclk / 4) { 862 mclk = lcdclk / 4; 863 dev_warn(dev, "Limiting master clock to %lu\n", mclk); 864 } 865 866 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ 867 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; 868 869 /* If we're not supplying MCLK, leave it at 0 */ 870 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) 871 pcdev->mclk = lcdclk / (2 * (div + 1)); 872 873 dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n", 874 lcdclk, mclk, div); 875 876 return div; 877} 878 879static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, 880 unsigned long pclk) 881{ 882 /* We want a timeout > 1 pixel time, not ">=" */ 883 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; 884 885 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); 886} 887 888static void pxa_camera_activate(struct pxa_camera_dev *pcdev) 889{ 890 u32 cicr4 = 0; 891 892 /* disable all interrupts */ 893 __raw_writel(0x3ff, pcdev->base + CICR0); 894 895 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) 896 cicr4 |= CICR4_PCLK_EN; 897 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) 898 cicr4 |= CICR4_MCLK_EN; 899 if (pcdev->platform_flags & PXA_CAMERA_PCP) 900 cicr4 |= CICR4_PCP; 901 if (pcdev->platform_flags & PXA_CAMERA_HSP) 902 cicr4 |= CICR4_HSP; 903 if (pcdev->platform_flags & PXA_CAMERA_VSP) 904 cicr4 |= CICR4_VSP; 905 906 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); 907 908 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) 909 /* Initialise the timeout under the assumption pclk = mclk */ 910 recalculate_fifo_timeout(pcdev, pcdev->mclk); 911 else 912 /* "Safe default" - 13MHz */ 913 recalculate_fifo_timeout(pcdev, 13000000); 914 915 clk_prepare_enable(pcdev->clk); 916} 917 918static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) 919{ 920 clk_disable_unprepare(pcdev->clk); 921} 922 923static irqreturn_t pxa_camera_irq(int irq, void *data) 924{ 925 struct pxa_camera_dev *pcdev = data; 926 unsigned long status, cifr, cicr0; 927 struct pxa_buffer *buf; 928 struct videobuf_buffer *vb; 929 930 status = __raw_readl(pcdev->base + CISR); 931 dev_dbg(pcdev->soc_host.v4l2_dev.dev, 932 "Camera interrupt status 0x%lx\n", status); 933 934 if (!status) 935 return IRQ_NONE; 936 937 __raw_writel(status, pcdev->base + CISR); 938 939 if (status & CISR_EOF) { 940 /* Reset the FIFOs */ 941 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; 942 __raw_writel(cifr, pcdev->base + CIFR); 943 944 pcdev->active = list_first_entry(&pcdev->capture, 945 struct pxa_buffer, vb.queue); 946 vb = &pcdev->active->vb; 947 buf = container_of(vb, struct pxa_buffer, vb); 948 pxa_videobuf_set_actdma(pcdev, buf); 949 950 pxa_dma_start_channels(pcdev); 951 952 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; 953 __raw_writel(cicr0, pcdev->base + CICR0); 954 } 955 956 return IRQ_HANDLED; 957} 958 959static int pxa_camera_add_device(struct soc_camera_device *icd) 960{ 961 dev_info(icd->parent, "PXA Camera driver attached to camera %d\n", 962 icd->devnum); 963 964 return 0; 965} 966 967static void pxa_camera_remove_device(struct soc_camera_device *icd) 968{ 969 dev_info(icd->parent, "PXA Camera driver detached from camera %d\n", 970 icd->devnum); 971} 972 973/* 974 * The following two functions absolutely depend on the fact, that 975 * there can be only one camera on PXA quick capture interface 976 * Called with .host_lock held 977 */ 978static int pxa_camera_clock_start(struct soc_camera_host *ici) 979{ 980 struct pxa_camera_dev *pcdev = ici->priv; 981 982 pxa_camera_activate(pcdev); 983 984 return 0; 985} 986 987/* Called with .host_lock held */ 988static void pxa_camera_clock_stop(struct soc_camera_host *ici) 989{ 990 struct pxa_camera_dev *pcdev = ici->priv; 991 992 /* disable capture, disable interrupts */ 993 __raw_writel(0x3ff, pcdev->base + CICR0); 994 995 /* Stop DMA engine */ 996 DCSR(pcdev->dma_chans[0]) = 0; 997 DCSR(pcdev->dma_chans[1]) = 0; 998 DCSR(pcdev->dma_chans[2]) = 0; 999 1000 pxa_camera_deactivate(pcdev); 1001} 1002 1003static int test_platform_param(struct pxa_camera_dev *pcdev, 1004 unsigned char buswidth, unsigned long *flags) 1005{ 1006 /* 1007 * Platform specified synchronization and pixel clock polarities are 1008 * only a recommendation and are only used during probing. The PXA270 1009 * quick capture interface supports both. 1010 */ 1011 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? 1012 V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) | 1013 V4L2_MBUS_HSYNC_ACTIVE_HIGH | 1014 V4L2_MBUS_HSYNC_ACTIVE_LOW | 1015 V4L2_MBUS_VSYNC_ACTIVE_HIGH | 1016 V4L2_MBUS_VSYNC_ACTIVE_LOW | 1017 V4L2_MBUS_DATA_ACTIVE_HIGH | 1018 V4L2_MBUS_PCLK_SAMPLE_RISING | 1019 V4L2_MBUS_PCLK_SAMPLE_FALLING; 1020 1021 /* If requested data width is supported by the platform, use it */ 1022 if ((1 << (buswidth - 1)) & pcdev->width_flags) 1023 return 0; 1024 1025 return -EINVAL; 1026} 1027 1028static void pxa_camera_setup_cicr(struct soc_camera_device *icd, 1029 unsigned long flags, __u32 pixfmt) 1030{ 1031 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 1032 struct pxa_camera_dev *pcdev = ici->priv; 1033 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1034 unsigned long dw, bpp; 1035 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top; 1036 int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top); 1037 1038 if (ret < 0) 1039 y_skip_top = 0; 1040 1041 /* 1042 * Datawidth is now guaranteed to be equal to one of the three values. 1043 * We fix bit-per-pixel equal to data-width... 1044 */ 1045 switch (icd->current_fmt->host_fmt->bits_per_sample) { 1046 case 10: 1047 dw = 4; 1048 bpp = 0x40; 1049 break; 1050 case 9: 1051 dw = 3; 1052 bpp = 0x20; 1053 break; 1054 default: 1055 /* 1056 * Actually it can only be 8 now, 1057 * default is just to silence compiler warnings 1058 */ 1059 case 8: 1060 dw = 2; 1061 bpp = 0; 1062 } 1063 1064 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) 1065 cicr4 |= CICR4_PCLK_EN; 1066 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) 1067 cicr4 |= CICR4_MCLK_EN; 1068 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) 1069 cicr4 |= CICR4_PCP; 1070 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) 1071 cicr4 |= CICR4_HSP; 1072 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) 1073 cicr4 |= CICR4_VSP; 1074 1075 cicr0 = __raw_readl(pcdev->base + CICR0); 1076 if (cicr0 & CICR0_ENB) 1077 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); 1078 1079 cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw; 1080 1081 switch (pixfmt) { 1082 case V4L2_PIX_FMT_YUV422P: 1083 pcdev->channels = 3; 1084 cicr1 |= CICR1_YCBCR_F; 1085 /* 1086 * Normally, pxa bus wants as input UYVY format. We allow all 1087 * reorderings of the YUV422 format, as no processing is done, 1088 * and the YUV stream is just passed through without any 1089 * transformation. Note that UYVY is the only format that 1090 * should be used if pxa framebuffer Overlay2 is used. 1091 */ 1092 case V4L2_PIX_FMT_UYVY: 1093 case V4L2_PIX_FMT_VYUY: 1094 case V4L2_PIX_FMT_YUYV: 1095 case V4L2_PIX_FMT_YVYU: 1096 cicr1 |= CICR1_COLOR_SP_VAL(2); 1097 break; 1098 case V4L2_PIX_FMT_RGB555: 1099 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | 1100 CICR1_TBIT | CICR1_COLOR_SP_VAL(1); 1101 break; 1102 case V4L2_PIX_FMT_RGB565: 1103 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); 1104 break; 1105 } 1106 1107 cicr2 = 0; 1108 cicr3 = CICR3_LPF_VAL(icd->user_height - 1) | 1109 CICR3_BFW_VAL(min((u32)255, y_skip_top)); 1110 cicr4 |= pcdev->mclk_divisor; 1111 1112 __raw_writel(cicr1, pcdev->base + CICR1); 1113 __raw_writel(cicr2, pcdev->base + CICR2); 1114 __raw_writel(cicr3, pcdev->base + CICR3); 1115 __raw_writel(cicr4, pcdev->base + CICR4); 1116 1117 /* CIF interrupts are not used, only DMA */ 1118 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? 1119 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); 1120 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; 1121 __raw_writel(cicr0, pcdev->base + CICR0); 1122} 1123 1124static int pxa_camera_set_bus_param(struct soc_camera_device *icd) 1125{ 1126 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1127 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 1128 struct pxa_camera_dev *pcdev = ici->priv; 1129 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; 1130 u32 pixfmt = icd->current_fmt->host_fmt->fourcc; 1131 unsigned long bus_flags, common_flags; 1132 int ret; 1133 struct pxa_cam *cam = icd->host_priv; 1134 1135 ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample, 1136 &bus_flags); 1137 if (ret < 0) 1138 return ret; 1139 1140 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); 1141 if (!ret) { 1142 common_flags = soc_mbus_config_compatible(&cfg, 1143 bus_flags); 1144 if (!common_flags) { 1145 dev_warn(icd->parent, 1146 "Flags incompatible: camera 0x%x, host 0x%lx\n", 1147 cfg.flags, bus_flags); 1148 return -EINVAL; 1149 } 1150 } else if (ret != -ENOIOCTLCMD) { 1151 return ret; 1152 } else { 1153 common_flags = bus_flags; 1154 } 1155 1156 pcdev->channels = 1; 1157 1158 /* Make choises, based on platform preferences */ 1159 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && 1160 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { 1161 if (pcdev->platform_flags & PXA_CAMERA_HSP) 1162 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; 1163 else 1164 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; 1165 } 1166 1167 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) && 1168 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) { 1169 if (pcdev->platform_flags & PXA_CAMERA_VSP) 1170 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH; 1171 else 1172 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW; 1173 } 1174 1175 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && 1176 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { 1177 if (pcdev->platform_flags & PXA_CAMERA_PCP) 1178 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; 1179 else 1180 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; 1181 } 1182 1183 cfg.flags = common_flags; 1184 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg); 1185 if (ret < 0 && ret != -ENOIOCTLCMD) { 1186 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n", 1187 common_flags, ret); 1188 return ret; 1189 } 1190 1191 cam->flags = common_flags; 1192 1193 pxa_camera_setup_cicr(icd, common_flags, pixfmt); 1194 1195 return 0; 1196} 1197 1198static int pxa_camera_try_bus_param(struct soc_camera_device *icd, 1199 unsigned char buswidth) 1200{ 1201 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1202 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 1203 struct pxa_camera_dev *pcdev = ici->priv; 1204 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; 1205 unsigned long bus_flags, common_flags; 1206 int ret = test_platform_param(pcdev, buswidth, &bus_flags); 1207 1208 if (ret < 0) 1209 return ret; 1210 1211 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); 1212 if (!ret) { 1213 common_flags = soc_mbus_config_compatible(&cfg, 1214 bus_flags); 1215 if (!common_flags) { 1216 dev_warn(icd->parent, 1217 "Flags incompatible: camera 0x%x, host 0x%lx\n", 1218 cfg.flags, bus_flags); 1219 return -EINVAL; 1220 } 1221 } else if (ret == -ENOIOCTLCMD) { 1222 ret = 0; 1223 } 1224 1225 return ret; 1226} 1227 1228static const struct soc_mbus_pixelfmt pxa_camera_formats[] = { 1229 { 1230 .fourcc = V4L2_PIX_FMT_YUV422P, 1231 .name = "Planar YUV422 16 bit", 1232 .bits_per_sample = 8, 1233 .packing = SOC_MBUS_PACKING_2X8_PADHI, 1234 .order = SOC_MBUS_ORDER_LE, 1235 .layout = SOC_MBUS_LAYOUT_PLANAR_2Y_U_V, 1236 }, 1237}; 1238 1239/* This will be corrected as we get more formats */ 1240static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt) 1241{ 1242 return fmt->packing == SOC_MBUS_PACKING_NONE || 1243 (fmt->bits_per_sample == 8 && 1244 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) || 1245 (fmt->bits_per_sample > 8 && 1246 fmt->packing == SOC_MBUS_PACKING_EXTEND16); 1247} 1248 1249static int pxa_camera_get_formats(struct soc_camera_device *icd, unsigned int idx, 1250 struct soc_camera_format_xlate *xlate) 1251{ 1252 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1253 struct device *dev = icd->parent; 1254 int formats = 0, ret; 1255 struct pxa_cam *cam; 1256 u32 code; 1257 const struct soc_mbus_pixelfmt *fmt; 1258 1259 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code); 1260 if (ret < 0) 1261 /* No more formats */ 1262 return 0; 1263 1264 fmt = soc_mbus_get_fmtdesc(code); 1265 if (!fmt) { 1266 dev_err(dev, "Invalid format code #%u: %d\n", idx, code); 1267 return 0; 1268 } 1269 1270 /* This also checks support for the requested bits-per-sample */ 1271 ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample); 1272 if (ret < 0) 1273 return 0; 1274 1275 if (!icd->host_priv) { 1276 cam = kzalloc(sizeof(*cam), GFP_KERNEL); 1277 if (!cam) 1278 return -ENOMEM; 1279 1280 icd->host_priv = cam; 1281 } else { 1282 cam = icd->host_priv; 1283 } 1284 1285 switch (code) { 1286 case MEDIA_BUS_FMT_UYVY8_2X8: 1287 formats++; 1288 if (xlate) { 1289 xlate->host_fmt = &pxa_camera_formats[0]; 1290 xlate->code = code; 1291 xlate++; 1292 dev_dbg(dev, "Providing format %s using code %d\n", 1293 pxa_camera_formats[0].name, code); 1294 } 1295 case MEDIA_BUS_FMT_VYUY8_2X8: 1296 case MEDIA_BUS_FMT_YUYV8_2X8: 1297 case MEDIA_BUS_FMT_YVYU8_2X8: 1298 case MEDIA_BUS_FMT_RGB565_2X8_LE: 1299 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: 1300 if (xlate) 1301 dev_dbg(dev, "Providing format %s packed\n", 1302 fmt->name); 1303 break; 1304 default: 1305 if (!pxa_camera_packing_supported(fmt)) 1306 return 0; 1307 if (xlate) 1308 dev_dbg(dev, 1309 "Providing format %s in pass-through mode\n", 1310 fmt->name); 1311 } 1312 1313 /* Generic pass-through */ 1314 formats++; 1315 if (xlate) { 1316 xlate->host_fmt = fmt; 1317 xlate->code = code; 1318 xlate++; 1319 } 1320 1321 return formats; 1322} 1323 1324static void pxa_camera_put_formats(struct soc_camera_device *icd) 1325{ 1326 kfree(icd->host_priv); 1327 icd->host_priv = NULL; 1328} 1329 1330static int pxa_camera_check_frame(u32 width, u32 height) 1331{ 1332 /* limit to pxa hardware capabilities */ 1333 return height < 32 || height > 2048 || width < 48 || width > 2048 || 1334 (width & 0x01); 1335} 1336 1337static int pxa_camera_set_crop(struct soc_camera_device *icd, 1338 const struct v4l2_crop *a) 1339{ 1340 const struct v4l2_rect *rect = &a->c; 1341 struct device *dev = icd->parent; 1342 struct soc_camera_host *ici = to_soc_camera_host(dev); 1343 struct pxa_camera_dev *pcdev = ici->priv; 1344 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1345 struct soc_camera_sense sense = { 1346 .master_clock = pcdev->mclk, 1347 .pixel_clock_max = pcdev->ciclk / 4, 1348 }; 1349 struct v4l2_mbus_framefmt mf; 1350 struct pxa_cam *cam = icd->host_priv; 1351 u32 fourcc = icd->current_fmt->host_fmt->fourcc; 1352 int ret; 1353 1354 /* If PCLK is used to latch data from the sensor, check sense */ 1355 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) 1356 icd->sense = &sense; 1357 1358 ret = v4l2_subdev_call(sd, video, s_crop, a); 1359 1360 icd->sense = NULL; 1361 1362 if (ret < 0) { 1363 dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n", 1364 rect->width, rect->height, rect->left, rect->top); 1365 return ret; 1366 } 1367 1368 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); 1369 if (ret < 0) 1370 return ret; 1371 1372 if (pxa_camera_check_frame(mf.width, mf.height)) { 1373 /* 1374 * Camera cropping produced a frame beyond our capabilities. 1375 * FIXME: just extract a subframe, that we can process. 1376 */ 1377 v4l_bound_align_image(&mf.width, 48, 2048, 1, 1378 &mf.height, 32, 2048, 0, 1379 fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0); 1380 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); 1381 if (ret < 0) 1382 return ret; 1383 1384 if (pxa_camera_check_frame(mf.width, mf.height)) { 1385 dev_warn(icd->parent, 1386 "Inconsistent state. Use S_FMT to repair\n"); 1387 return -EINVAL; 1388 } 1389 } 1390 1391 if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { 1392 if (sense.pixel_clock > sense.pixel_clock_max) { 1393 dev_err(dev, 1394 "pixel clock %lu set by the camera too high!", 1395 sense.pixel_clock); 1396 return -EIO; 1397 } 1398 recalculate_fifo_timeout(pcdev, sense.pixel_clock); 1399 } 1400 1401 icd->user_width = mf.width; 1402 icd->user_height = mf.height; 1403 1404 pxa_camera_setup_cicr(icd, cam->flags, fourcc); 1405 1406 return ret; 1407} 1408 1409static int pxa_camera_set_fmt(struct soc_camera_device *icd, 1410 struct v4l2_format *f) 1411{ 1412 struct device *dev = icd->parent; 1413 struct soc_camera_host *ici = to_soc_camera_host(dev); 1414 struct pxa_camera_dev *pcdev = ici->priv; 1415 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1416 const struct soc_camera_format_xlate *xlate = NULL; 1417 struct soc_camera_sense sense = { 1418 .master_clock = pcdev->mclk, 1419 .pixel_clock_max = pcdev->ciclk / 4, 1420 }; 1421 struct v4l2_pix_format *pix = &f->fmt.pix; 1422 struct v4l2_mbus_framefmt mf; 1423 int ret; 1424 1425 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); 1426 if (!xlate) { 1427 dev_warn(dev, "Format %x not found\n", pix->pixelformat); 1428 return -EINVAL; 1429 } 1430 1431 /* If PCLK is used to latch data from the sensor, check sense */ 1432 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) 1433 /* The caller holds a mutex. */ 1434 icd->sense = &sense; 1435 1436 mf.width = pix->width; 1437 mf.height = pix->height; 1438 mf.field = pix->field; 1439 mf.colorspace = pix->colorspace; 1440 mf.code = xlate->code; 1441 1442 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); 1443 1444 if (mf.code != xlate->code) 1445 return -EINVAL; 1446 1447 icd->sense = NULL; 1448 1449 if (ret < 0) { 1450 dev_warn(dev, "Failed to configure for format %x\n", 1451 pix->pixelformat); 1452 } else if (pxa_camera_check_frame(mf.width, mf.height)) { 1453 dev_warn(dev, 1454 "Camera driver produced an unsupported frame %dx%d\n", 1455 mf.width, mf.height); 1456 ret = -EINVAL; 1457 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { 1458 if (sense.pixel_clock > sense.pixel_clock_max) { 1459 dev_err(dev, 1460 "pixel clock %lu set by the camera too high!", 1461 sense.pixel_clock); 1462 return -EIO; 1463 } 1464 recalculate_fifo_timeout(pcdev, sense.pixel_clock); 1465 } 1466 1467 if (ret < 0) 1468 return ret; 1469 1470 pix->width = mf.width; 1471 pix->height = mf.height; 1472 pix->field = mf.field; 1473 pix->colorspace = mf.colorspace; 1474 icd->current_fmt = xlate; 1475 1476 return ret; 1477} 1478 1479static int pxa_camera_try_fmt(struct soc_camera_device *icd, 1480 struct v4l2_format *f) 1481{ 1482 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1483 const struct soc_camera_format_xlate *xlate; 1484 struct v4l2_pix_format *pix = &f->fmt.pix; 1485 struct v4l2_mbus_framefmt mf; 1486 __u32 pixfmt = pix->pixelformat; 1487 int ret; 1488 1489 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); 1490 if (!xlate) { 1491 dev_warn(icd->parent, "Format %x not found\n", pixfmt); 1492 return -EINVAL; 1493 } 1494 1495 /* 1496 * Limit to pxa hardware capabilities. YUV422P planar format requires 1497 * images size to be a multiple of 16 bytes. If not, zeros will be 1498 * inserted between Y and U planes, and U and V planes, which violates 1499 * the YUV422P standard. 1500 */ 1501 v4l_bound_align_image(&pix->width, 48, 2048, 1, 1502 &pix->height, 32, 2048, 0, 1503 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0); 1504 1505 /* limit to sensor capabilities */ 1506 mf.width = pix->width; 1507 mf.height = pix->height; 1508 /* Only progressive video supported so far */ 1509 mf.field = V4L2_FIELD_NONE; 1510 mf.colorspace = pix->colorspace; 1511 mf.code = xlate->code; 1512 1513 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); 1514 if (ret < 0) 1515 return ret; 1516 1517 pix->width = mf.width; 1518 pix->height = mf.height; 1519 pix->colorspace = mf.colorspace; 1520 1521 switch (mf.field) { 1522 case V4L2_FIELD_ANY: 1523 case V4L2_FIELD_NONE: 1524 pix->field = V4L2_FIELD_NONE; 1525 break; 1526 default: 1527 /* TODO: support interlaced at least in pass-through mode */ 1528 dev_err(icd->parent, "Field type %d unsupported.\n", 1529 mf.field); 1530 return -EINVAL; 1531 } 1532 1533 return ret; 1534} 1535 1536static int pxa_camera_reqbufs(struct soc_camera_device *icd, 1537 struct v4l2_requestbuffers *p) 1538{ 1539 int i; 1540 1541 /* 1542 * This is for locking debugging only. I removed spinlocks and now I 1543 * check whether .prepare is ever called on a linked buffer, or whether 1544 * a dma IRQ can occur for an in-work or unlinked buffer. Until now 1545 * it hadn't triggered 1546 */ 1547 for (i = 0; i < p->count; i++) { 1548 struct pxa_buffer *buf = container_of(icd->vb_vidq.bufs[i], 1549 struct pxa_buffer, vb); 1550 buf->inwork = 0; 1551 INIT_LIST_HEAD(&buf->vb.queue); 1552 } 1553 1554 return 0; 1555} 1556 1557static unsigned int pxa_camera_poll(struct file *file, poll_table *pt) 1558{ 1559 struct soc_camera_device *icd = file->private_data; 1560 struct pxa_buffer *buf; 1561 1562 buf = list_entry(icd->vb_vidq.stream.next, struct pxa_buffer, 1563 vb.stream); 1564 1565 poll_wait(file, &buf->vb.done, pt); 1566 1567 if (buf->vb.state == VIDEOBUF_DONE || 1568 buf->vb.state == VIDEOBUF_ERROR) 1569 return POLLIN|POLLRDNORM; 1570 1571 return 0; 1572} 1573 1574static int pxa_camera_querycap(struct soc_camera_host *ici, 1575 struct v4l2_capability *cap) 1576{ 1577 /* cap->name is set by the firendly caller:-> */ 1578 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); 1579 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; 1580 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; 1581 1582 return 0; 1583} 1584 1585static int pxa_camera_suspend(struct device *dev) 1586{ 1587 struct soc_camera_host *ici = to_soc_camera_host(dev); 1588 struct pxa_camera_dev *pcdev = ici->priv; 1589 int i = 0, ret = 0; 1590 1591 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); 1592 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); 1593 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); 1594 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); 1595 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); 1596 1597 if (pcdev->soc_host.icd) { 1598 struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd); 1599 ret = v4l2_subdev_call(sd, core, s_power, 0); 1600 if (ret == -ENOIOCTLCMD) 1601 ret = 0; 1602 } 1603 1604 return ret; 1605} 1606 1607static int pxa_camera_resume(struct device *dev) 1608{ 1609 struct soc_camera_host *ici = to_soc_camera_host(dev); 1610 struct pxa_camera_dev *pcdev = ici->priv; 1611 int i = 0, ret = 0; 1612 1613 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; 1614 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; 1615 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; 1616 1617 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); 1618 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); 1619 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); 1620 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); 1621 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); 1622 1623 if (pcdev->soc_host.icd) { 1624 struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd); 1625 ret = v4l2_subdev_call(sd, core, s_power, 1); 1626 if (ret == -ENOIOCTLCMD) 1627 ret = 0; 1628 } 1629 1630 /* Restart frame capture if active buffer exists */ 1631 if (!ret && pcdev->active) 1632 pxa_camera_start_capture(pcdev); 1633 1634 return ret; 1635} 1636 1637static struct soc_camera_host_ops pxa_soc_camera_host_ops = { 1638 .owner = THIS_MODULE, 1639 .add = pxa_camera_add_device, 1640 .remove = pxa_camera_remove_device, 1641 .clock_start = pxa_camera_clock_start, 1642 .clock_stop = pxa_camera_clock_stop, 1643 .set_crop = pxa_camera_set_crop, 1644 .get_formats = pxa_camera_get_formats, 1645 .put_formats = pxa_camera_put_formats, 1646 .set_fmt = pxa_camera_set_fmt, 1647 .try_fmt = pxa_camera_try_fmt, 1648 .init_videobuf = pxa_camera_init_videobuf, 1649 .reqbufs = pxa_camera_reqbufs, 1650 .poll = pxa_camera_poll, 1651 .querycap = pxa_camera_querycap, 1652 .set_bus_param = pxa_camera_set_bus_param, 1653}; 1654 1655static int pxa_camera_pdata_from_dt(struct device *dev, 1656 struct pxa_camera_dev *pcdev) 1657{ 1658 u32 mclk_rate; 1659 struct device_node *np = dev->of_node; 1660 struct v4l2_of_endpoint ep; 1661 int err = of_property_read_u32(np, "clock-frequency", 1662 &mclk_rate); 1663 if (!err) { 1664 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN; 1665 pcdev->mclk = mclk_rate; 1666 } 1667 1668 np = of_graph_get_next_endpoint(np, NULL); 1669 if (!np) { 1670 dev_err(dev, "could not find endpoint\n"); 1671 return -EINVAL; 1672 } 1673 1674 err = v4l2_of_parse_endpoint(np, &ep); 1675 if (err) { 1676 dev_err(dev, "could not parse endpoint\n"); 1677 goto out; 1678 } 1679 1680 switch (ep.bus.parallel.bus_width) { 1681 case 4: 1682 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4; 1683 break; 1684 case 5: 1685 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5; 1686 break; 1687 case 8: 1688 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8; 1689 break; 1690 case 9: 1691 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9; 1692 break; 1693 case 10: 1694 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; 1695 break; 1696 default: 1697 break; 1698 } 1699 1700 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER) 1701 pcdev->platform_flags |= PXA_CAMERA_MASTER; 1702 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 1703 pcdev->platform_flags |= PXA_CAMERA_HSP; 1704 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 1705 pcdev->platform_flags |= PXA_CAMERA_VSP; 1706 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 1707 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP; 1708 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) 1709 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN; 1710 1711out: 1712 of_node_put(np); 1713 1714 return err; 1715} 1716 1717static int pxa_camera_probe(struct platform_device *pdev) 1718{ 1719 struct pxa_camera_dev *pcdev; 1720 struct resource *res; 1721 void __iomem *base; 1722 int irq; 1723 int err = 0; 1724 1725 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1726 irq = platform_get_irq(pdev, 0); 1727 if (!res || irq < 0) 1728 return -ENODEV; 1729 1730 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL); 1731 if (!pcdev) { 1732 dev_err(&pdev->dev, "Could not allocate pcdev\n"); 1733 return -ENOMEM; 1734 } 1735 1736 pcdev->clk = devm_clk_get(&pdev->dev, NULL); 1737 if (IS_ERR(pcdev->clk)) 1738 return PTR_ERR(pcdev->clk); 1739 1740 pcdev->res = res; 1741 1742 pcdev->pdata = pdev->dev.platform_data; 1743 if (&pdev->dev.of_node && !pcdev->pdata) { 1744 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev); 1745 } else { 1746 pcdev->platform_flags = pcdev->pdata->flags; 1747 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; 1748 } 1749 if (err < 0) 1750 return err; 1751 1752 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | 1753 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { 1754 /* 1755 * Platform hasn't set available data widths. This is bad. 1756 * Warn and use a default. 1757 */ 1758 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " 1759 "data widths, using default 10 bit\n"); 1760 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; 1761 } 1762 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8) 1763 pcdev->width_flags = 1 << 7; 1764 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9) 1765 pcdev->width_flags |= 1 << 8; 1766 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10) 1767 pcdev->width_flags |= 1 << 9; 1768 if (!pcdev->mclk) { 1769 dev_warn(&pdev->dev, 1770 "mclk == 0! Please, fix your platform data. " 1771 "Using default 20MHz\n"); 1772 pcdev->mclk = 20000000; 1773 } 1774 1775 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev); 1776 1777 INIT_LIST_HEAD(&pcdev->capture); 1778 spin_lock_init(&pcdev->lock); 1779 1780 /* 1781 * Request the regions. 1782 */ 1783 base = devm_ioremap_resource(&pdev->dev, res); 1784 if (IS_ERR(base)) 1785 return PTR_ERR(base); 1786 1787 pcdev->irq = irq; 1788 pcdev->base = base; 1789 1790 /* request dma */ 1791 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH, 1792 pxa_camera_dma_irq_y, pcdev); 1793 if (err < 0) { 1794 dev_err(&pdev->dev, "Can't request DMA for Y\n"); 1795 return err; 1796 } 1797 pcdev->dma_chans[0] = err; 1798 dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]); 1799 1800 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH, 1801 pxa_camera_dma_irq_u, pcdev); 1802 if (err < 0) { 1803 dev_err(&pdev->dev, "Can't request DMA for U\n"); 1804 goto exit_free_dma_y; 1805 } 1806 pcdev->dma_chans[1] = err; 1807 dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]); 1808 1809 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH, 1810 pxa_camera_dma_irq_v, pcdev); 1811 if (err < 0) { 1812 dev_err(&pdev->dev, "Can't request DMA for V\n"); 1813 goto exit_free_dma_u; 1814 } 1815 pcdev->dma_chans[2] = err; 1816 dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]); 1817 1818 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; 1819 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; 1820 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; 1821 1822 /* request irq */ 1823 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0, 1824 PXA_CAM_DRV_NAME, pcdev); 1825 if (err) { 1826 dev_err(&pdev->dev, "Camera interrupt register failed\n"); 1827 goto exit_free_dma; 1828 } 1829 1830 pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME; 1831 pcdev->soc_host.ops = &pxa_soc_camera_host_ops; 1832 pcdev->soc_host.priv = pcdev; 1833 pcdev->soc_host.v4l2_dev.dev = &pdev->dev; 1834 pcdev->soc_host.nr = pdev->id; 1835 1836 err = soc_camera_host_register(&pcdev->soc_host); 1837 if (err) 1838 goto exit_free_dma; 1839 1840 return 0; 1841 1842exit_free_dma: 1843 pxa_free_dma(pcdev->dma_chans[2]); 1844exit_free_dma_u: 1845 pxa_free_dma(pcdev->dma_chans[1]); 1846exit_free_dma_y: 1847 pxa_free_dma(pcdev->dma_chans[0]); 1848 return err; 1849} 1850 1851static int pxa_camera_remove(struct platform_device *pdev) 1852{ 1853 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); 1854 struct pxa_camera_dev *pcdev = container_of(soc_host, 1855 struct pxa_camera_dev, soc_host); 1856 1857 pxa_free_dma(pcdev->dma_chans[0]); 1858 pxa_free_dma(pcdev->dma_chans[1]); 1859 pxa_free_dma(pcdev->dma_chans[2]); 1860 1861 soc_camera_host_unregister(soc_host); 1862 1863 dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); 1864 1865 return 0; 1866} 1867 1868static const struct dev_pm_ops pxa_camera_pm = { 1869 .suspend = pxa_camera_suspend, 1870 .resume = pxa_camera_resume, 1871}; 1872 1873static const struct of_device_id pxa_camera_of_match[] = { 1874 { .compatible = "marvell,pxa270-qci", }, 1875 {}, 1876}; 1877MODULE_DEVICE_TABLE(of, pxa_camera_of_match); 1878 1879static struct platform_driver pxa_camera_driver = { 1880 .driver = { 1881 .name = PXA_CAM_DRV_NAME, 1882 .pm = &pxa_camera_pm, 1883 .of_match_table = of_match_ptr(pxa_camera_of_match), 1884 }, 1885 .probe = pxa_camera_probe, 1886 .remove = pxa_camera_remove, 1887}; 1888 1889module_platform_driver(pxa_camera_driver); 1890 1891MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); 1892MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); 1893MODULE_LICENSE("GPL"); 1894MODULE_VERSION(PXA_CAM_VERSION); 1895MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME); 1896