1/* 2 * Rafael Micro R820T driver 3 * 4 * Copyright (C) 2013 Mauro Carvalho Chehab 5 * 6 * This driver was written from scratch, based on an existing driver 7 * that it is part of rtl-sdr git tree, released under GPLv2: 8 * https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug 9 * https://github.com/n1gp/gr-baz 10 * 11 * From what I understood from the threads, the original driver was converted 12 * to userspace from a Realtek tree. I couldn't find the original tree. 13 * However, the original driver look awkward on my eyes. So, I decided to 14 * write a new version from it from the scratch, while trying to reproduce 15 * everything found there. 16 * 17 * TODO: 18 * After locking, the original driver seems to have some routines to 19 * improve reception. This was not implemented here yet. 20 * 21 * RF Gain set/get is not implemented. 22 * 23 * This program is free software; you can redistribute it and/or modify 24 * it under the terms of the GNU General Public License as published by 25 * the Free Software Foundation; either version 2 of the License, or 26 * (at your option) any later version. 27 * 28 * This program is distributed in the hope that it will be useful, 29 * but WITHOUT ANY WARRANTY; without even the implied warranty of 30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 31 * GNU General Public License for more details. 32 * 33 */ 34 35#include <linux/videodev2.h> 36#include <linux/mutex.h> 37#include <linux/slab.h> 38#include <linux/bitrev.h> 39 40#include "tuner-i2c.h" 41#include "r820t.h" 42 43/* 44 * FIXME: I think that there are only 32 registers, but better safe than 45 * sorry. After finishing the driver, we may review it. 46 */ 47#define REG_SHADOW_START 5 48#define NUM_REGS 27 49#define NUM_IMR 5 50#define IMR_TRIAL 9 51 52#define VER_NUM 49 53 54static int debug; 55module_param(debug, int, 0644); 56MODULE_PARM_DESC(debug, "enable verbose debug messages"); 57 58static int no_imr_cal; 59module_param(no_imr_cal, int, 0444); 60MODULE_PARM_DESC(no_imr_cal, "Disable IMR calibration at module init"); 61 62 63/* 64 * enums and structures 65 */ 66 67enum xtal_cap_value { 68 XTAL_LOW_CAP_30P = 0, 69 XTAL_LOW_CAP_20P, 70 XTAL_LOW_CAP_10P, 71 XTAL_LOW_CAP_0P, 72 XTAL_HIGH_CAP_0P 73}; 74 75struct r820t_sect_type { 76 u8 phase_y; 77 u8 gain_x; 78 u16 value; 79}; 80 81struct r820t_priv { 82 struct list_head hybrid_tuner_instance_list; 83 const struct r820t_config *cfg; 84 struct tuner_i2c_props i2c_props; 85 struct mutex lock; 86 87 u8 regs[NUM_REGS]; 88 u8 buf[NUM_REGS + 1]; 89 enum xtal_cap_value xtal_cap_sel; 90 u16 pll; /* kHz */ 91 u32 int_freq; 92 u8 fil_cal_code; 93 bool imr_done; 94 bool has_lock; 95 bool init_done; 96 struct r820t_sect_type imr_data[NUM_IMR]; 97 98 /* Store current mode */ 99 u32 delsys; 100 enum v4l2_tuner_type type; 101 v4l2_std_id std; 102 u32 bw; /* in MHz */ 103}; 104 105struct r820t_freq_range { 106 u32 freq; 107 u8 open_d; 108 u8 rf_mux_ploy; 109 u8 tf_c; 110 u8 xtal_cap20p; 111 u8 xtal_cap10p; 112 u8 xtal_cap0p; 113 u8 imr_mem; /* Not used, currently */ 114}; 115 116#define VCO_POWER_REF 0x02 117#define DIP_FREQ 32000000 118 119/* 120 * Static constants 121 */ 122 123static LIST_HEAD(hybrid_tuner_instance_list); 124static DEFINE_MUTEX(r820t_list_mutex); 125 126/* Those initial values start from REG_SHADOW_START */ 127static const u8 r820t_init_array[NUM_REGS] = { 128 0x83, 0x32, 0x75, /* 05 to 07 */ 129 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */ 130 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */ 131 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */ 132 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */ 133 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */ 134 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */ 135}; 136 137/* Tuner frequency ranges */ 138static const struct r820t_freq_range freq_ranges[] = { 139 { 140 .freq = 0, 141 .open_d = 0x08, /* low */ 142 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 143 .tf_c = 0xdf, /* R27[7:0] band2,band0 */ 144 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 145 .xtal_cap10p = 0x01, 146 .xtal_cap0p = 0x00, 147 .imr_mem = 0, 148 }, { 149 .freq = 50, /* Start freq, in MHz */ 150 .open_d = 0x08, /* low */ 151 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 152 .tf_c = 0xbe, /* R27[7:0] band4,band1 */ 153 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 154 .xtal_cap10p = 0x01, 155 .xtal_cap0p = 0x00, 156 .imr_mem = 0, 157 }, { 158 .freq = 55, /* Start freq, in MHz */ 159 .open_d = 0x08, /* low */ 160 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 161 .tf_c = 0x8b, /* R27[7:0] band7,band4 */ 162 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 163 .xtal_cap10p = 0x01, 164 .xtal_cap0p = 0x00, 165 .imr_mem = 0, 166 }, { 167 .freq = 60, /* Start freq, in MHz */ 168 .open_d = 0x08, /* low */ 169 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 170 .tf_c = 0x7b, /* R27[7:0] band8,band4 */ 171 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 172 .xtal_cap10p = 0x01, 173 .xtal_cap0p = 0x00, 174 .imr_mem = 0, 175 }, { 176 .freq = 65, /* Start freq, in MHz */ 177 .open_d = 0x08, /* low */ 178 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 179 .tf_c = 0x69, /* R27[7:0] band9,band6 */ 180 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 181 .xtal_cap10p = 0x01, 182 .xtal_cap0p = 0x00, 183 .imr_mem = 0, 184 }, { 185 .freq = 70, /* Start freq, in MHz */ 186 .open_d = 0x08, /* low */ 187 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 188 .tf_c = 0x58, /* R27[7:0] band10,band7 */ 189 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 190 .xtal_cap10p = 0x01, 191 .xtal_cap0p = 0x00, 192 .imr_mem = 0, 193 }, { 194 .freq = 75, /* Start freq, in MHz */ 195 .open_d = 0x00, /* high */ 196 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 197 .tf_c = 0x44, /* R27[7:0] band11,band11 */ 198 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 199 .xtal_cap10p = 0x01, 200 .xtal_cap0p = 0x00, 201 .imr_mem = 0, 202 }, { 203 .freq = 80, /* Start freq, in MHz */ 204 .open_d = 0x00, /* high */ 205 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 206 .tf_c = 0x44, /* R27[7:0] band11,band11 */ 207 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 208 .xtal_cap10p = 0x01, 209 .xtal_cap0p = 0x00, 210 .imr_mem = 0, 211 }, { 212 .freq = 90, /* Start freq, in MHz */ 213 .open_d = 0x00, /* high */ 214 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 215 .tf_c = 0x34, /* R27[7:0] band12,band11 */ 216 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 217 .xtal_cap10p = 0x01, 218 .xtal_cap0p = 0x00, 219 .imr_mem = 0, 220 }, { 221 .freq = 100, /* Start freq, in MHz */ 222 .open_d = 0x00, /* high */ 223 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 224 .tf_c = 0x34, /* R27[7:0] band12,band11 */ 225 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 226 .xtal_cap10p = 0x01, 227 .xtal_cap0p = 0x00, 228 .imr_mem = 0, 229 }, { 230 .freq = 110, /* Start freq, in MHz */ 231 .open_d = 0x00, /* high */ 232 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 233 .tf_c = 0x24, /* R27[7:0] band13,band11 */ 234 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 235 .xtal_cap10p = 0x01, 236 .xtal_cap0p = 0x00, 237 .imr_mem = 1, 238 }, { 239 .freq = 120, /* Start freq, in MHz */ 240 .open_d = 0x00, /* high */ 241 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 242 .tf_c = 0x24, /* R27[7:0] band13,band11 */ 243 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 244 .xtal_cap10p = 0x01, 245 .xtal_cap0p = 0x00, 246 .imr_mem = 1, 247 }, { 248 .freq = 140, /* Start freq, in MHz */ 249 .open_d = 0x00, /* high */ 250 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 251 .tf_c = 0x14, /* R27[7:0] band14,band11 */ 252 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 253 .xtal_cap10p = 0x01, 254 .xtal_cap0p = 0x00, 255 .imr_mem = 1, 256 }, { 257 .freq = 180, /* Start freq, in MHz */ 258 .open_d = 0x00, /* high */ 259 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 260 .tf_c = 0x13, /* R27[7:0] band14,band12 */ 261 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 262 .xtal_cap10p = 0x00, 263 .xtal_cap0p = 0x00, 264 .imr_mem = 1, 265 }, { 266 .freq = 220, /* Start freq, in MHz */ 267 .open_d = 0x00, /* high */ 268 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 269 .tf_c = 0x13, /* R27[7:0] band14,band12 */ 270 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 271 .xtal_cap10p = 0x00, 272 .xtal_cap0p = 0x00, 273 .imr_mem = 2, 274 }, { 275 .freq = 250, /* Start freq, in MHz */ 276 .open_d = 0x00, /* high */ 277 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 278 .tf_c = 0x11, /* R27[7:0] highest,highest */ 279 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 280 .xtal_cap10p = 0x00, 281 .xtal_cap0p = 0x00, 282 .imr_mem = 2, 283 }, { 284 .freq = 280, /* Start freq, in MHz */ 285 .open_d = 0x00, /* high */ 286 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 287 .tf_c = 0x00, /* R27[7:0] highest,highest */ 288 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 289 .xtal_cap10p = 0x00, 290 .xtal_cap0p = 0x00, 291 .imr_mem = 2, 292 }, { 293 .freq = 310, /* Start freq, in MHz */ 294 .open_d = 0x00, /* high */ 295 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */ 296 .tf_c = 0x00, /* R27[7:0] highest,highest */ 297 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 298 .xtal_cap10p = 0x00, 299 .xtal_cap0p = 0x00, 300 .imr_mem = 2, 301 }, { 302 .freq = 450, /* Start freq, in MHz */ 303 .open_d = 0x00, /* high */ 304 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */ 305 .tf_c = 0x00, /* R27[7:0] highest,highest */ 306 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 307 .xtal_cap10p = 0x00, 308 .xtal_cap0p = 0x00, 309 .imr_mem = 3, 310 }, { 311 .freq = 588, /* Start freq, in MHz */ 312 .open_d = 0x00, /* high */ 313 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */ 314 .tf_c = 0x00, /* R27[7:0] highest,highest */ 315 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 316 .xtal_cap10p = 0x00, 317 .xtal_cap0p = 0x00, 318 .imr_mem = 3, 319 }, { 320 .freq = 650, /* Start freq, in MHz */ 321 .open_d = 0x00, /* high */ 322 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */ 323 .tf_c = 0x00, /* R27[7:0] highest,highest */ 324 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 325 .xtal_cap10p = 0x00, 326 .xtal_cap0p = 0x00, 327 .imr_mem = 4, 328 } 329}; 330 331static int r820t_xtal_capacitor[][2] = { 332 { 0x0b, XTAL_LOW_CAP_30P }, 333 { 0x02, XTAL_LOW_CAP_20P }, 334 { 0x01, XTAL_LOW_CAP_10P }, 335 { 0x00, XTAL_LOW_CAP_0P }, 336 { 0x10, XTAL_HIGH_CAP_0P }, 337}; 338 339/* 340 * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm 341 * input power, for raw results see: 342 * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/ 343 */ 344 345static const int r820t_lna_gain_steps[] = { 346 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13 347}; 348 349static const int r820t_mixer_gain_steps[] = { 350 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8 351}; 352 353/* 354 * I2C read/write code and shadow registers logic 355 */ 356static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val, 357 int len) 358{ 359 int r = reg - REG_SHADOW_START; 360 361 if (r < 0) { 362 len += r; 363 r = 0; 364 } 365 if (len <= 0) 366 return; 367 if (len > NUM_REGS - r) 368 len = NUM_REGS - r; 369 370 tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n", 371 __func__, r + REG_SHADOW_START, len, len, val); 372 373 memcpy(&priv->regs[r], val, len); 374} 375 376static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val, 377 int len) 378{ 379 int rc, size, pos = 0; 380 381 /* Store the shadow registers */ 382 shadow_store(priv, reg, val, len); 383 384 do { 385 if (len > priv->cfg->max_i2c_msg_len - 1) 386 size = priv->cfg->max_i2c_msg_len - 1; 387 else 388 size = len; 389 390 /* Fill I2C buffer */ 391 priv->buf[0] = reg; 392 memcpy(&priv->buf[1], &val[pos], size); 393 394 rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1); 395 if (rc != size + 1) { 396 tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n", 397 __func__, rc, reg, size, size, &priv->buf[1]); 398 if (rc < 0) 399 return rc; 400 return -EREMOTEIO; 401 } 402 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n", 403 __func__, reg, size, size, &priv->buf[1]); 404 405 reg += size; 406 len -= size; 407 pos += size; 408 } while (len > 0); 409 410 return 0; 411} 412 413static int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val) 414{ 415 return r820t_write(priv, reg, &val, 1); 416} 417 418static int r820t_read_cache_reg(struct r820t_priv *priv, int reg) 419{ 420 reg -= REG_SHADOW_START; 421 422 if (reg >= 0 && reg < NUM_REGS) 423 return priv->regs[reg]; 424 else 425 return -EINVAL; 426} 427 428static int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val, 429 u8 bit_mask) 430{ 431 int rc = r820t_read_cache_reg(priv, reg); 432 433 if (rc < 0) 434 return rc; 435 436 val = (rc & ~bit_mask) | (val & bit_mask); 437 438 return r820t_write(priv, reg, &val, 1); 439} 440 441static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len) 442{ 443 int rc, i; 444 u8 *p = &priv->buf[1]; 445 446 priv->buf[0] = reg; 447 448 rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len); 449 if (rc != len) { 450 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n", 451 __func__, rc, reg, len, len, p); 452 if (rc < 0) 453 return rc; 454 return -EREMOTEIO; 455 } 456 457 /* Copy data to the output buffer */ 458 for (i = 0; i < len; i++) 459 val[i] = bitrev8(p[i]); 460 461 tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n", 462 __func__, reg, len, len, val); 463 464 return 0; 465} 466 467/* 468 * r820t tuning logic 469 */ 470 471static int r820t_set_mux(struct r820t_priv *priv, u32 freq) 472{ 473 const struct r820t_freq_range *range; 474 int i, rc; 475 u8 val, reg08, reg09; 476 477 /* Get the proper frequency range */ 478 freq = freq / 1000000; 479 for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) { 480 if (freq < freq_ranges[i + 1].freq) 481 break; 482 } 483 range = &freq_ranges[i]; 484 485 tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq); 486 487 /* Open Drain */ 488 rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08); 489 if (rc < 0) 490 return rc; 491 492 /* RF_MUX,Polymux */ 493 rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3); 494 if (rc < 0) 495 return rc; 496 497 /* TF BAND */ 498 rc = r820t_write_reg(priv, 0x1b, range->tf_c); 499 if (rc < 0) 500 return rc; 501 502 /* XTAL CAP & Drive */ 503 switch (priv->xtal_cap_sel) { 504 case XTAL_LOW_CAP_30P: 505 case XTAL_LOW_CAP_20P: 506 val = range->xtal_cap20p | 0x08; 507 break; 508 case XTAL_LOW_CAP_10P: 509 val = range->xtal_cap10p | 0x08; 510 break; 511 case XTAL_HIGH_CAP_0P: 512 val = range->xtal_cap0p | 0x00; 513 break; 514 default: 515 case XTAL_LOW_CAP_0P: 516 val = range->xtal_cap0p | 0x08; 517 break; 518 } 519 rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b); 520 if (rc < 0) 521 return rc; 522 523 if (priv->imr_done) { 524 reg08 = priv->imr_data[range->imr_mem].gain_x; 525 reg09 = priv->imr_data[range->imr_mem].phase_y; 526 } else { 527 reg08 = 0; 528 reg09 = 0; 529 } 530 rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f); 531 if (rc < 0) 532 return rc; 533 534 rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f); 535 536 return rc; 537} 538 539static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type, 540 u32 freq) 541{ 542 u32 vco_freq; 543 int rc, i; 544 unsigned sleep_time = 10000; 545 u32 vco_fra; /* VCO contribution by SDM (kHz) */ 546 u32 vco_min = 1770000; 547 u32 vco_max = vco_min * 2; 548 u32 pll_ref; 549 u16 n_sdm = 2; 550 u16 sdm = 0; 551 u8 mix_div = 2; 552 u8 div_buf = 0; 553 u8 div_num = 0; 554 u8 refdiv2 = 0; 555 u8 ni, si, nint, vco_fine_tune, val; 556 u8 data[5]; 557 558 /* Frequency in kHz */ 559 freq = freq / 1000; 560 pll_ref = priv->cfg->xtal / 1000; 561 562#if 0 563 /* Doesn't exist on rtl-sdk, and on field tests, caused troubles */ 564 if ((priv->cfg->rafael_chip == CHIP_R620D) || 565 (priv->cfg->rafael_chip == CHIP_R828D) || 566 (priv->cfg->rafael_chip == CHIP_R828)) { 567 /* ref set refdiv2, reffreq = Xtal/2 on ATV application */ 568 if (type != V4L2_TUNER_DIGITAL_TV) { 569 pll_ref /= 2; 570 refdiv2 = 0x10; 571 sleep_time = 20000; 572 } 573 } else { 574 if (priv->cfg->xtal > 24000000) { 575 pll_ref /= 2; 576 refdiv2 = 0x10; 577 } 578 } 579#endif 580 581 rc = r820t_write_reg_mask(priv, 0x10, refdiv2, 0x10); 582 if (rc < 0) 583 return rc; 584 585 /* set pll autotune = 128kHz */ 586 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c); 587 if (rc < 0) 588 return rc; 589 590 /* set VCO current = 100 */ 591 rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0); 592 if (rc < 0) 593 return rc; 594 595 /* Calculate divider */ 596 while (mix_div <= 64) { 597 if (((freq * mix_div) >= vco_min) && 598 ((freq * mix_div) < vco_max)) { 599 div_buf = mix_div; 600 while (div_buf > 2) { 601 div_buf = div_buf >> 1; 602 div_num++; 603 } 604 break; 605 } 606 mix_div = mix_div << 1; 607 } 608 609 rc = r820t_read(priv, 0x00, data, sizeof(data)); 610 if (rc < 0) 611 return rc; 612 613 vco_fine_tune = (data[4] & 0x30) >> 4; 614 615 tuner_dbg("mix_div=%d div_num=%d vco_fine_tune=%d\n", 616 mix_div, div_num, vco_fine_tune); 617 618 /* 619 * XXX: R828D/16MHz seems to have always vco_fine_tune=1. 620 * Due to that, this calculation goes wrong. 621 */ 622 if (priv->cfg->rafael_chip != CHIP_R828D) { 623 if (vco_fine_tune > VCO_POWER_REF) 624 div_num = div_num - 1; 625 else if (vco_fine_tune < VCO_POWER_REF) 626 div_num = div_num + 1; 627 } 628 629 rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0); 630 if (rc < 0) 631 return rc; 632 633 vco_freq = freq * mix_div; 634 nint = vco_freq / (2 * pll_ref); 635 vco_fra = vco_freq - 2 * pll_ref * nint; 636 637 /* boundary spur prevention */ 638 if (vco_fra < pll_ref / 64) { 639 vco_fra = 0; 640 } else if (vco_fra > pll_ref * 127 / 64) { 641 vco_fra = 0; 642 nint++; 643 } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) { 644 vco_fra = pll_ref * 127 / 128; 645 } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) { 646 vco_fra = pll_ref * 129 / 128; 647 } 648 649 ni = (nint - 13) / 4; 650 si = nint - 4 * ni - 13; 651 652 rc = r820t_write_reg(priv, 0x14, ni + (si << 6)); 653 if (rc < 0) 654 return rc; 655 656 /* pw_sdm */ 657 if (!vco_fra) 658 val = 0x08; 659 else 660 val = 0x00; 661 662 rc = r820t_write_reg_mask(priv, 0x12, val, 0x08); 663 if (rc < 0) 664 return rc; 665 666 /* sdm calculator */ 667 while (vco_fra > 1) { 668 if (vco_fra > (2 * pll_ref / n_sdm)) { 669 sdm = sdm + 32768 / (n_sdm / 2); 670 vco_fra = vco_fra - 2 * pll_ref / n_sdm; 671 if (n_sdm >= 0x8000) 672 break; 673 } 674 n_sdm = n_sdm << 1; 675 } 676 677 tuner_dbg("freq %d kHz, pll ref %d%s, sdm=0x%04x\n", 678 freq, pll_ref, refdiv2 ? " / 2" : "", sdm); 679 680 rc = r820t_write_reg(priv, 0x16, sdm >> 8); 681 if (rc < 0) 682 return rc; 683 rc = r820t_write_reg(priv, 0x15, sdm & 0xff); 684 if (rc < 0) 685 return rc; 686 687 for (i = 0; i < 2; i++) { 688 usleep_range(sleep_time, sleep_time + 1000); 689 690 /* Check if PLL has locked */ 691 rc = r820t_read(priv, 0x00, data, 3); 692 if (rc < 0) 693 return rc; 694 if (data[2] & 0x40) 695 break; 696 697 if (!i) { 698 /* Didn't lock. Increase VCO current */ 699 rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0); 700 if (rc < 0) 701 return rc; 702 } 703 } 704 705 if (!(data[2] & 0x40)) { 706 priv->has_lock = false; 707 return 0; 708 } 709 710 priv->has_lock = true; 711 tuner_dbg("tuner has lock at frequency %d kHz\n", freq); 712 713 /* set pll autotune = 8kHz */ 714 rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08); 715 716 return rc; 717} 718 719static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq, 720 enum v4l2_tuner_type type, 721 v4l2_std_id std, 722 u32 delsys) 723{ 724 int rc; 725 u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l; 726 u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur; 727 728 tuner_dbg("adjusting tuner parameters for the standard\n"); 729 730 switch (delsys) { 731 case SYS_DVBT: 732 if ((freq == 506000000) || (freq == 666000000) || 733 (freq == 818000000)) { 734 mixer_top = 0x14; /* mixer top:14 , top-1, low-discharge */ 735 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 736 cp_cur = 0x28; /* 101, 0.2 */ 737 div_buf_cur = 0x20; /* 10, 200u */ 738 } else { 739 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ 740 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 741 cp_cur = 0x38; /* 111, auto */ 742 div_buf_cur = 0x30; /* 11, 150u */ 743 } 744 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */ 745 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ 746 air_cable1_in = 0x00; 747 cable2_in = 0x00; 748 pre_dect = 0x40; 749 lna_discharge = 14; 750 filter_cur = 0x40; /* 10, low */ 751 break; 752 case SYS_DVBT2: 753 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ 754 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 755 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */ 756 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ 757 air_cable1_in = 0x00; 758 cable2_in = 0x00; 759 pre_dect = 0x40; 760 lna_discharge = 14; 761 cp_cur = 0x38; /* 111, auto */ 762 div_buf_cur = 0x30; /* 11, 150u */ 763 filter_cur = 0x40; /* 10, low */ 764 break; 765 case SYS_ISDBT: 766 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ 767 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 768 lna_vth_l = 0x75; /* lna vth 1.04 , vtl 0.84 */ 769 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ 770 air_cable1_in = 0x00; 771 cable2_in = 0x00; 772 pre_dect = 0x40; 773 lna_discharge = 14; 774 cp_cur = 0x38; /* 111, auto */ 775 div_buf_cur = 0x30; /* 11, 150u */ 776 filter_cur = 0x40; /* 10, low */ 777 break; 778 case SYS_DVBC_ANNEX_A: 779 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ 780 lna_top = 0xe5; 781 lna_vth_l = 0x62; 782 mixer_vth_l = 0x75; 783 air_cable1_in = 0x60; 784 cable2_in = 0x00; 785 pre_dect = 0x40; 786 lna_discharge = 14; 787 cp_cur = 0x38; /* 111, auto */ 788 div_buf_cur = 0x30; /* 11, 150u */ 789 filter_cur = 0x40; /* 10, low */ 790 break; 791 default: /* DVB-T 8M */ 792 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ 793 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 794 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */ 795 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ 796 air_cable1_in = 0x00; 797 cable2_in = 0x00; 798 pre_dect = 0x40; 799 lna_discharge = 14; 800 cp_cur = 0x38; /* 111, auto */ 801 div_buf_cur = 0x30; /* 11, 150u */ 802 filter_cur = 0x40; /* 10, low */ 803 break; 804 } 805 806 if (priv->cfg->use_diplexer && 807 ((priv->cfg->rafael_chip == CHIP_R820T) || 808 (priv->cfg->rafael_chip == CHIP_R828S) || 809 (priv->cfg->rafael_chip == CHIP_R820C))) { 810 if (freq > DIP_FREQ) 811 air_cable1_in = 0x00; 812 else 813 air_cable1_in = 0x60; 814 cable2_in = 0x00; 815 } 816 817 818 if (priv->cfg->use_predetect) { 819 rc = r820t_write_reg_mask(priv, 0x06, pre_dect, 0x40); 820 if (rc < 0) 821 return rc; 822 } 823 824 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7); 825 if (rc < 0) 826 return rc; 827 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8); 828 if (rc < 0) 829 return rc; 830 rc = r820t_write_reg(priv, 0x0d, lna_vth_l); 831 if (rc < 0) 832 return rc; 833 rc = r820t_write_reg(priv, 0x0e, mixer_vth_l); 834 if (rc < 0) 835 return rc; 836 837 /* Air-IN only for Astrometa */ 838 rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60); 839 if (rc < 0) 840 return rc; 841 rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08); 842 if (rc < 0) 843 return rc; 844 845 rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38); 846 if (rc < 0) 847 return rc; 848 rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30); 849 if (rc < 0) 850 return rc; 851 rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60); 852 if (rc < 0) 853 return rc; 854 /* 855 * Original driver initializes regs 0x05 and 0x06 with the 856 * same value again on this point. Probably, it is just an 857 * error there 858 */ 859 860 /* 861 * Set LNA 862 */ 863 864 tuner_dbg("adjusting LNA parameters\n"); 865 if (type != V4L2_TUNER_ANALOG_TV) { 866 /* LNA TOP: lowest */ 867 rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38); 868 if (rc < 0) 869 return rc; 870 871 /* 0: normal mode */ 872 rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04); 873 if (rc < 0) 874 return rc; 875 876 /* 0: PRE_DECT off */ 877 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40); 878 if (rc < 0) 879 return rc; 880 881 /* agc clk 250hz */ 882 rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30); 883 if (rc < 0) 884 return rc; 885 886 msleep(250); 887 888 /* write LNA TOP = 3 */ 889 rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38); 890 if (rc < 0) 891 return rc; 892 893 /* 894 * write discharge mode 895 * FIXME: IMHO, the mask here is wrong, but it matches 896 * what's there at the original driver 897 */ 898 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04); 899 if (rc < 0) 900 return rc; 901 902 /* LNA discharge current */ 903 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f); 904 if (rc < 0) 905 return rc; 906 907 /* agc clk 60hz */ 908 rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30); 909 if (rc < 0) 910 return rc; 911 } else { 912 /* PRE_DECT off */ 913 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40); 914 if (rc < 0) 915 return rc; 916 917 /* write LNA TOP */ 918 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38); 919 if (rc < 0) 920 return rc; 921 922 /* 923 * write discharge mode 924 * FIXME: IMHO, the mask here is wrong, but it matches 925 * what's there at the original driver 926 */ 927 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04); 928 if (rc < 0) 929 return rc; 930 931 /* LNA discharge current */ 932 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f); 933 if (rc < 0) 934 return rc; 935 936 /* agc clk 1Khz, external det1 cap 1u */ 937 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30); 938 if (rc < 0) 939 return rc; 940 941 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04); 942 if (rc < 0) 943 return rc; 944 } 945 return 0; 946} 947 948static int r820t_set_tv_standard(struct r820t_priv *priv, 949 unsigned bw, 950 enum v4l2_tuner_type type, 951 v4l2_std_id std, u32 delsys) 952 953{ 954 int rc, i; 955 u32 if_khz, filt_cal_lo; 956 u8 data[5], val; 957 u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through; 958 u8 lt_att, flt_ext_widest, polyfil_cur; 959 bool need_calibration; 960 961 tuner_dbg("selecting the delivery system\n"); 962 963 if (delsys == SYS_ISDBT) { 964 if_khz = 4063; 965 filt_cal_lo = 59000; 966 filt_gain = 0x10; /* +3db, 6mhz on */ 967 img_r = 0x00; /* image negative */ 968 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 969 hp_cor = 0x6a; /* 1.7m disable, +2cap, 1.25mhz */ 970 ext_enable = 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */ 971 loop_through = 0x00; /* r5[7], lt on */ 972 lt_att = 0x00; /* r31[7], lt att enable */ 973 flt_ext_widest = 0x80; /* r15[7]: flt_ext_wide on */ 974 polyfil_cur = 0x60; /* r25[6:5]:min */ 975 } else if (delsys == SYS_DVBC_ANNEX_A) { 976 if_khz = 5070; 977 filt_cal_lo = 73500; 978 filt_gain = 0x10; /* +3db, 6mhz on */ 979 img_r = 0x00; /* image negative */ 980 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 981 hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */ 982 ext_enable = 0x40; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 983 loop_through = 0x00; /* r5[7], lt on */ 984 lt_att = 0x00; /* r31[7], lt att enable */ 985 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 986 polyfil_cur = 0x60; /* r25[6:5]:min */ 987 } else if (delsys == SYS_DVBC_ANNEX_C) { 988 if_khz = 4063; 989 filt_cal_lo = 55000; 990 filt_gain = 0x10; /* +3db, 6mhz on */ 991 img_r = 0x00; /* image negative */ 992 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 993 hp_cor = 0x6a; /* 1.7m disable, +0cap, 1.0mhz */ 994 ext_enable = 0x40; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 995 loop_through = 0x00; /* r5[7], lt on */ 996 lt_att = 0x00; /* r31[7], lt att enable */ 997 flt_ext_widest = 0x80; /* r15[7]: flt_ext_wide on */ 998 polyfil_cur = 0x60; /* r25[6:5]:min */ 999 } else { 1000 if (bw <= 6) { 1001 if_khz = 3570; 1002 filt_cal_lo = 56000; /* 52000->56000 */ 1003 filt_gain = 0x10; /* +3db, 6mhz on */ 1004 img_r = 0x00; /* image negative */ 1005 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 1006 hp_cor = 0x6b; /* 1.7m disable, +2cap, 1.0mhz */ 1007 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 1008 loop_through = 0x00; /* r5[7], lt on */ 1009 lt_att = 0x00; /* r31[7], lt att enable */ 1010 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 1011 polyfil_cur = 0x60; /* r25[6:5]:min */ 1012 } else if (bw == 7) { 1013#if 0 1014 /* 1015 * There are two 7 MHz tables defined on the original 1016 * driver, but just the second one seems to be visible 1017 * by rtl2832. Keep this one here commented, as it 1018 * might be needed in the future 1019 */ 1020 1021 if_khz = 4070; 1022 filt_cal_lo = 60000; 1023 filt_gain = 0x10; /* +3db, 6mhz on */ 1024 img_r = 0x00; /* image negative */ 1025 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 1026 hp_cor = 0x2b; /* 1.7m disable, +1cap, 1.0mhz */ 1027 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 1028 loop_through = 0x00; /* r5[7], lt on */ 1029 lt_att = 0x00; /* r31[7], lt att enable */ 1030 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 1031 polyfil_cur = 0x60; /* r25[6:5]:min */ 1032#endif 1033 /* 7 MHz, second table */ 1034 if_khz = 4570; 1035 filt_cal_lo = 63000; 1036 filt_gain = 0x10; /* +3db, 6mhz on */ 1037 img_r = 0x00; /* image negative */ 1038 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 1039 hp_cor = 0x2a; /* 1.7m disable, +1cap, 1.25mhz */ 1040 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 1041 loop_through = 0x00; /* r5[7], lt on */ 1042 lt_att = 0x00; /* r31[7], lt att enable */ 1043 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 1044 polyfil_cur = 0x60; /* r25[6:5]:min */ 1045 } else { 1046 if_khz = 4570; 1047 filt_cal_lo = 68500; 1048 filt_gain = 0x10; /* +3db, 6mhz on */ 1049 img_r = 0x00; /* image negative */ 1050 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 1051 hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */ 1052 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 1053 loop_through = 0x00; /* r5[7], lt on */ 1054 lt_att = 0x00; /* r31[7], lt att enable */ 1055 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 1056 polyfil_cur = 0x60; /* r25[6:5]:min */ 1057 } 1058 } 1059 1060 /* Initialize the shadow registers */ 1061 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array)); 1062 1063 /* Init Flag & Xtal_check Result */ 1064 if (priv->imr_done) 1065 val = 1 | priv->xtal_cap_sel << 1; 1066 else 1067 val = 0; 1068 rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f); 1069 if (rc < 0) 1070 return rc; 1071 1072 /* version */ 1073 rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f); 1074 if (rc < 0) 1075 return rc; 1076 1077 /* for LT Gain test */ 1078 if (type != V4L2_TUNER_ANALOG_TV) { 1079 rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38); 1080 if (rc < 0) 1081 return rc; 1082 usleep_range(1000, 2000); 1083 } 1084 priv->int_freq = if_khz * 1000; 1085 1086 /* Check if standard changed. If so, filter calibration is needed */ 1087 if (type != priv->type) 1088 need_calibration = true; 1089 else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std)) 1090 need_calibration = true; 1091 else if ((type == V4L2_TUNER_DIGITAL_TV) && 1092 ((delsys != priv->delsys) || bw != priv->bw)) 1093 need_calibration = true; 1094 else 1095 need_calibration = false; 1096 1097 if (need_calibration) { 1098 tuner_dbg("calibrating the tuner\n"); 1099 for (i = 0; i < 2; i++) { 1100 /* Set filt_cap */ 1101 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60); 1102 if (rc < 0) 1103 return rc; 1104 1105 /* set cali clk =on */ 1106 rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04); 1107 if (rc < 0) 1108 return rc; 1109 1110 /* X'tal cap 0pF for PLL */ 1111 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03); 1112 if (rc < 0) 1113 return rc; 1114 1115 rc = r820t_set_pll(priv, type, filt_cal_lo * 1000); 1116 if (rc < 0 || !priv->has_lock) 1117 return rc; 1118 1119 /* Start Trigger */ 1120 rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10); 1121 if (rc < 0) 1122 return rc; 1123 1124 usleep_range(1000, 2000); 1125 1126 /* Stop Trigger */ 1127 rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10); 1128 if (rc < 0) 1129 return rc; 1130 1131 /* set cali clk =off */ 1132 rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04); 1133 if (rc < 0) 1134 return rc; 1135 1136 /* Check if calibration worked */ 1137 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1138 if (rc < 0) 1139 return rc; 1140 1141 priv->fil_cal_code = data[4] & 0x0f; 1142 if (priv->fil_cal_code && priv->fil_cal_code != 0x0f) 1143 break; 1144 } 1145 /* narrowest */ 1146 if (priv->fil_cal_code == 0x0f) 1147 priv->fil_cal_code = 0; 1148 } 1149 1150 rc = r820t_write_reg_mask(priv, 0x0a, 1151 filt_q | priv->fil_cal_code, 0x1f); 1152 if (rc < 0) 1153 return rc; 1154 1155 /* Set BW, Filter_gain, & HP corner */ 1156 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0xef); 1157 if (rc < 0) 1158 return rc; 1159 1160 1161 /* Set Img_R */ 1162 rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80); 1163 if (rc < 0) 1164 return rc; 1165 1166 /* Set filt_3dB, V6MHz */ 1167 rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30); 1168 if (rc < 0) 1169 return rc; 1170 1171 /* channel filter extension */ 1172 rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60); 1173 if (rc < 0) 1174 return rc; 1175 1176 /* Loop through */ 1177 rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80); 1178 if (rc < 0) 1179 return rc; 1180 1181 /* Loop through attenuation */ 1182 rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80); 1183 if (rc < 0) 1184 return rc; 1185 1186 /* filter extension widest */ 1187 rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80); 1188 if (rc < 0) 1189 return rc; 1190 1191 /* RF poly filter current */ 1192 rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60); 1193 if (rc < 0) 1194 return rc; 1195 1196 /* Store current standard. If it changes, re-calibrate the tuner */ 1197 priv->delsys = delsys; 1198 priv->type = type; 1199 priv->std = std; 1200 priv->bw = bw; 1201 1202 return 0; 1203} 1204 1205static int r820t_read_gain(struct r820t_priv *priv) 1206{ 1207 u8 data[4]; 1208 int rc; 1209 1210 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1211 if (rc < 0) 1212 return rc; 1213 1214 return ((data[3] & 0x08) << 1) + ((data[3] & 0xf0) >> 4); 1215} 1216 1217#if 0 1218/* FIXME: This routine requires more testing */ 1219static int r820t_set_gain_mode(struct r820t_priv *priv, 1220 bool set_manual_gain, 1221 int gain) 1222{ 1223 int rc; 1224 1225 if (set_manual_gain) { 1226 int i, total_gain = 0; 1227 uint8_t mix_index = 0, lna_index = 0; 1228 u8 data[4]; 1229 1230 /* LNA auto off */ 1231 rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10); 1232 if (rc < 0) 1233 return rc; 1234 1235 /* Mixer auto off */ 1236 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10); 1237 if (rc < 0) 1238 return rc; 1239 1240 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1241 if (rc < 0) 1242 return rc; 1243 1244 /* set fixed VGA gain for now (16.3 dB) */ 1245 rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f); 1246 if (rc < 0) 1247 return rc; 1248 1249 for (i = 0; i < 15; i++) { 1250 if (total_gain >= gain) 1251 break; 1252 1253 total_gain += r820t_lna_gain_steps[++lna_index]; 1254 1255 if (total_gain >= gain) 1256 break; 1257 1258 total_gain += r820t_mixer_gain_steps[++mix_index]; 1259 } 1260 1261 /* set LNA gain */ 1262 rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f); 1263 if (rc < 0) 1264 return rc; 1265 1266 /* set Mixer gain */ 1267 rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f); 1268 if (rc < 0) 1269 return rc; 1270 } else { 1271 /* LNA */ 1272 rc = r820t_write_reg_mask(priv, 0x05, 0, 0x10); 1273 if (rc < 0) 1274 return rc; 1275 1276 /* Mixer */ 1277 rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0x10); 1278 if (rc < 0) 1279 return rc; 1280 1281 /* set fixed VGA gain for now (26.5 dB) */ 1282 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f); 1283 if (rc < 0) 1284 return rc; 1285 } 1286 1287 return 0; 1288} 1289#endif 1290 1291static int generic_set_freq(struct dvb_frontend *fe, 1292 u32 freq /* in HZ */, 1293 unsigned bw, 1294 enum v4l2_tuner_type type, 1295 v4l2_std_id std, u32 delsys) 1296{ 1297 struct r820t_priv *priv = fe->tuner_priv; 1298 int rc = -EINVAL; 1299 u32 lo_freq; 1300 1301 tuner_dbg("should set frequency to %d kHz, bw %d MHz\n", 1302 freq / 1000, bw); 1303 1304 rc = r820t_set_tv_standard(priv, bw, type, std, delsys); 1305 if (rc < 0) 1306 goto err; 1307 1308 if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC)) 1309 lo_freq = freq - priv->int_freq; 1310 else 1311 lo_freq = freq + priv->int_freq; 1312 1313 rc = r820t_set_mux(priv, lo_freq); 1314 if (rc < 0) 1315 goto err; 1316 1317 rc = r820t_set_pll(priv, type, lo_freq); 1318 if (rc < 0 || !priv->has_lock) 1319 goto err; 1320 1321 rc = r820t_sysfreq_sel(priv, freq, type, std, delsys); 1322 if (rc < 0) 1323 goto err; 1324 1325 tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n", 1326 __func__, freq, r820t_read_gain(priv)); 1327 1328err: 1329 1330 if (rc < 0) 1331 tuner_dbg("%s: failed=%d\n", __func__, rc); 1332 return rc; 1333} 1334 1335/* 1336 * r820t standby logic 1337 */ 1338 1339static int r820t_standby(struct r820t_priv *priv) 1340{ 1341 int rc; 1342 1343 /* If device was not initialized yet, don't need to standby */ 1344 if (!priv->init_done) 1345 return 0; 1346 1347 rc = r820t_write_reg(priv, 0x06, 0xb1); 1348 if (rc < 0) 1349 return rc; 1350 rc = r820t_write_reg(priv, 0x05, 0x03); 1351 if (rc < 0) 1352 return rc; 1353 rc = r820t_write_reg(priv, 0x07, 0x3a); 1354 if (rc < 0) 1355 return rc; 1356 rc = r820t_write_reg(priv, 0x08, 0x40); 1357 if (rc < 0) 1358 return rc; 1359 rc = r820t_write_reg(priv, 0x09, 0xc0); 1360 if (rc < 0) 1361 return rc; 1362 rc = r820t_write_reg(priv, 0x0a, 0x36); 1363 if (rc < 0) 1364 return rc; 1365 rc = r820t_write_reg(priv, 0x0c, 0x35); 1366 if (rc < 0) 1367 return rc; 1368 rc = r820t_write_reg(priv, 0x0f, 0x68); 1369 if (rc < 0) 1370 return rc; 1371 rc = r820t_write_reg(priv, 0x11, 0x03); 1372 if (rc < 0) 1373 return rc; 1374 rc = r820t_write_reg(priv, 0x17, 0xf4); 1375 if (rc < 0) 1376 return rc; 1377 rc = r820t_write_reg(priv, 0x19, 0x0c); 1378 1379 /* Force initial calibration */ 1380 priv->type = -1; 1381 1382 return rc; 1383} 1384 1385/* 1386 * r820t device init logic 1387 */ 1388 1389static int r820t_xtal_check(struct r820t_priv *priv) 1390{ 1391 int rc, i; 1392 u8 data[3], val; 1393 1394 /* Initialize the shadow registers */ 1395 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array)); 1396 1397 /* cap 30pF & Drive Low */ 1398 rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b); 1399 if (rc < 0) 1400 return rc; 1401 1402 /* set pll autotune = 128kHz */ 1403 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c); 1404 if (rc < 0) 1405 return rc; 1406 1407 /* set manual initial reg = 111111; */ 1408 rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f); 1409 if (rc < 0) 1410 return rc; 1411 1412 /* set auto */ 1413 rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40); 1414 if (rc < 0) 1415 return rc; 1416 1417 /* Try several xtal capacitor alternatives */ 1418 for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) { 1419 rc = r820t_write_reg_mask(priv, 0x10, 1420 r820t_xtal_capacitor[i][0], 0x1b); 1421 if (rc < 0) 1422 return rc; 1423 1424 usleep_range(5000, 6000); 1425 1426 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1427 if (rc < 0) 1428 return rc; 1429 if (!(data[2] & 0x40)) 1430 continue; 1431 1432 val = data[2] & 0x3f; 1433 1434 if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23)) 1435 break; 1436 1437 if (val != 0x3f) 1438 break; 1439 } 1440 1441 if (i == ARRAY_SIZE(r820t_xtal_capacitor)) 1442 return -EINVAL; 1443 1444 return r820t_xtal_capacitor[i][1]; 1445} 1446 1447static int r820t_imr_prepare(struct r820t_priv *priv) 1448{ 1449 int rc; 1450 1451 /* Initialize the shadow registers */ 1452 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array)); 1453 1454 /* lna off (air-in off) */ 1455 rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20); 1456 if (rc < 0) 1457 return rc; 1458 1459 /* mixer gain mode = manual */ 1460 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10); 1461 if (rc < 0) 1462 return rc; 1463 1464 /* filter corner = lowest */ 1465 rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f); 1466 if (rc < 0) 1467 return rc; 1468 1469 /* filter bw=+2cap, hp=5M */ 1470 rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f); 1471 if (rc < 0) 1472 return rc; 1473 1474 /* adc=on, vga code mode, gain = 26.5dB */ 1475 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f); 1476 if (rc < 0) 1477 return rc; 1478 1479 /* ring clk = on */ 1480 rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08); 1481 if (rc < 0) 1482 return rc; 1483 1484 /* ring power = on */ 1485 rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10); 1486 if (rc < 0) 1487 return rc; 1488 1489 /* from ring = ring pll in */ 1490 rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02); 1491 if (rc < 0) 1492 return rc; 1493 1494 /* sw_pdect = det3 */ 1495 rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80); 1496 if (rc < 0) 1497 return rc; 1498 1499 /* Set filt_3dB */ 1500 rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20); 1501 1502 return rc; 1503} 1504 1505static int r820t_multi_read(struct r820t_priv *priv) 1506{ 1507 int rc, i; 1508 u16 sum = 0; 1509 u8 data[2], min = 255, max = 0; 1510 1511 usleep_range(5000, 6000); 1512 1513 for (i = 0; i < 6; i++) { 1514 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1515 if (rc < 0) 1516 return rc; 1517 1518 sum += data[1]; 1519 1520 if (data[1] < min) 1521 min = data[1]; 1522 1523 if (data[1] > max) 1524 max = data[1]; 1525 } 1526 rc = sum - max - min; 1527 1528 return rc; 1529} 1530 1531static int r820t_imr_cross(struct r820t_priv *priv, 1532 struct r820t_sect_type iq_point[3], 1533 u8 *x_direct) 1534{ 1535 struct r820t_sect_type cross[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */ 1536 struct r820t_sect_type tmp; 1537 int i, rc; 1538 u8 reg08, reg09; 1539 1540 reg08 = r820t_read_cache_reg(priv, 8) & 0xc0; 1541 reg09 = r820t_read_cache_reg(priv, 9) & 0xc0; 1542 1543 tmp.gain_x = 0; 1544 tmp.phase_y = 0; 1545 tmp.value = 255; 1546 1547 for (i = 0; i < 5; i++) { 1548 switch (i) { 1549 case 0: 1550 cross[i].gain_x = reg08; 1551 cross[i].phase_y = reg09; 1552 break; 1553 case 1: 1554 cross[i].gain_x = reg08; /* 0 */ 1555 cross[i].phase_y = reg09 + 1; /* Q-1 */ 1556 break; 1557 case 2: 1558 cross[i].gain_x = reg08; /* 0 */ 1559 cross[i].phase_y = (reg09 | 0x20) + 1; /* I-1 */ 1560 break; 1561 case 3: 1562 cross[i].gain_x = reg08 + 1; /* Q-1 */ 1563 cross[i].phase_y = reg09; 1564 break; 1565 default: 1566 cross[i].gain_x = (reg08 | 0x20) + 1; /* I-1 */ 1567 cross[i].phase_y = reg09; 1568 } 1569 1570 rc = r820t_write_reg(priv, 0x08, cross[i].gain_x); 1571 if (rc < 0) 1572 return rc; 1573 1574 rc = r820t_write_reg(priv, 0x09, cross[i].phase_y); 1575 if (rc < 0) 1576 return rc; 1577 1578 rc = r820t_multi_read(priv); 1579 if (rc < 0) 1580 return rc; 1581 1582 cross[i].value = rc; 1583 1584 if (cross[i].value < tmp.value) 1585 tmp = cross[i]; 1586 } 1587 1588 if ((tmp.phase_y & 0x1f) == 1) { /* y-direction */ 1589 *x_direct = 0; 1590 1591 iq_point[0] = cross[0]; 1592 iq_point[1] = cross[1]; 1593 iq_point[2] = cross[2]; 1594 } else { /* (0,0) or x-direction */ 1595 *x_direct = 1; 1596 1597 iq_point[0] = cross[0]; 1598 iq_point[1] = cross[3]; 1599 iq_point[2] = cross[4]; 1600 } 1601 return 0; 1602} 1603 1604static void r820t_compre_cor(struct r820t_sect_type iq[3]) 1605{ 1606 int i; 1607 1608 for (i = 3; i > 0; i--) { 1609 if (iq[0].value > iq[i - 1].value) 1610 swap(iq[0], iq[i - 1]); 1611 } 1612} 1613 1614static int r820t_compre_step(struct r820t_priv *priv, 1615 struct r820t_sect_type iq[3], u8 reg) 1616{ 1617 int rc; 1618 struct r820t_sect_type tmp; 1619 1620 /* 1621 * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare 1622 * with min value: 1623 * new < min => update to min and continue 1624 * new > min => Exit 1625 */ 1626 1627 /* min value already saved in iq[0] */ 1628 tmp.phase_y = iq[0].phase_y; 1629 tmp.gain_x = iq[0].gain_x; 1630 1631 while (((tmp.gain_x & 0x1f) < IMR_TRIAL) && 1632 ((tmp.phase_y & 0x1f) < IMR_TRIAL)) { 1633 if (reg == 0x08) 1634 tmp.gain_x++; 1635 else 1636 tmp.phase_y++; 1637 1638 rc = r820t_write_reg(priv, 0x08, tmp.gain_x); 1639 if (rc < 0) 1640 return rc; 1641 1642 rc = r820t_write_reg(priv, 0x09, tmp.phase_y); 1643 if (rc < 0) 1644 return rc; 1645 1646 rc = r820t_multi_read(priv); 1647 if (rc < 0) 1648 return rc; 1649 tmp.value = rc; 1650 1651 if (tmp.value <= iq[0].value) { 1652 iq[0].gain_x = tmp.gain_x; 1653 iq[0].phase_y = tmp.phase_y; 1654 iq[0].value = tmp.value; 1655 } else { 1656 return 0; 1657 } 1658 1659 } 1660 1661 return 0; 1662} 1663 1664static int r820t_iq_tree(struct r820t_priv *priv, 1665 struct r820t_sect_type iq[3], 1666 u8 fix_val, u8 var_val, u8 fix_reg) 1667{ 1668 int rc, i; 1669 u8 tmp, var_reg; 1670 1671 /* 1672 * record IMC results by input gain/phase location then adjust 1673 * gain or phase positive 1 step and negtive 1 step, 1674 * both record results 1675 */ 1676 1677 if (fix_reg == 0x08) 1678 var_reg = 0x09; 1679 else 1680 var_reg = 0x08; 1681 1682 for (i = 0; i < 3; i++) { 1683 rc = r820t_write_reg(priv, fix_reg, fix_val); 1684 if (rc < 0) 1685 return rc; 1686 1687 rc = r820t_write_reg(priv, var_reg, var_val); 1688 if (rc < 0) 1689 return rc; 1690 1691 rc = r820t_multi_read(priv); 1692 if (rc < 0) 1693 return rc; 1694 iq[i].value = rc; 1695 1696 if (fix_reg == 0x08) { 1697 iq[i].gain_x = fix_val; 1698 iq[i].phase_y = var_val; 1699 } else { 1700 iq[i].phase_y = fix_val; 1701 iq[i].gain_x = var_val; 1702 } 1703 1704 if (i == 0) { /* try right-side point */ 1705 var_val++; 1706 } else if (i == 1) { /* try left-side point */ 1707 /* if absolute location is 1, change I/Q direction */ 1708 if ((var_val & 0x1f) < 0x02) { 1709 tmp = 2 - (var_val & 0x1f); 1710 1711 /* b[5]:I/Q selection. 0:Q-path, 1:I-path */ 1712 if (var_val & 0x20) { 1713 var_val &= 0xc0; 1714 var_val |= tmp; 1715 } else { 1716 var_val |= 0x20 | tmp; 1717 } 1718 } else { 1719 var_val -= 2; 1720 } 1721 } 1722 } 1723 1724 return 0; 1725} 1726 1727static int r820t_section(struct r820t_priv *priv, 1728 struct r820t_sect_type *iq_point) 1729{ 1730 int rc; 1731 struct r820t_sect_type compare_iq[3], compare_bet[3]; 1732 1733 /* Try X-1 column and save min result to compare_bet[0] */ 1734 if (!(iq_point->gain_x & 0x1f)) 1735 compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1; /* Q-path, Gain=1 */ 1736 else 1737 compare_iq[0].gain_x = iq_point->gain_x - 1; /* left point */ 1738 compare_iq[0].phase_y = iq_point->phase_y; 1739 1740 /* y-direction */ 1741 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1742 compare_iq[0].phase_y, 0x08); 1743 if (rc < 0) 1744 return rc; 1745 1746 r820t_compre_cor(compare_iq); 1747 1748 compare_bet[0] = compare_iq[0]; 1749 1750 /* Try X column and save min result to compare_bet[1] */ 1751 compare_iq[0].gain_x = iq_point->gain_x; 1752 compare_iq[0].phase_y = iq_point->phase_y; 1753 1754 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1755 compare_iq[0].phase_y, 0x08); 1756 if (rc < 0) 1757 return rc; 1758 1759 r820t_compre_cor(compare_iq); 1760 1761 compare_bet[1] = compare_iq[0]; 1762 1763 /* Try X+1 column and save min result to compare_bet[2] */ 1764 if ((iq_point->gain_x & 0x1f) == 0x00) 1765 compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1; /* I-path, Gain=1 */ 1766 else 1767 compare_iq[0].gain_x = iq_point->gain_x + 1; 1768 compare_iq[0].phase_y = iq_point->phase_y; 1769 1770 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1771 compare_iq[0].phase_y, 0x08); 1772 if (rc < 0) 1773 return rc; 1774 1775 r820t_compre_cor(compare_iq); 1776 1777 compare_bet[2] = compare_iq[0]; 1778 1779 r820t_compre_cor(compare_bet); 1780 1781 *iq_point = compare_bet[0]; 1782 1783 return 0; 1784} 1785 1786static int r820t_vga_adjust(struct r820t_priv *priv) 1787{ 1788 int rc; 1789 u8 vga_count; 1790 1791 /* increase vga power to let image significant */ 1792 for (vga_count = 12; vga_count < 16; vga_count++) { 1793 rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f); 1794 if (rc < 0) 1795 return rc; 1796 1797 usleep_range(10000, 11000); 1798 1799 rc = r820t_multi_read(priv); 1800 if (rc < 0) 1801 return rc; 1802 1803 if (rc > 40 * 4) 1804 break; 1805 } 1806 1807 return 0; 1808} 1809 1810static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont) 1811{ 1812 struct r820t_sect_type compare_iq[3]; 1813 int rc; 1814 u8 x_direction = 0; /* 1:x, 0:y */ 1815 u8 dir_reg, other_reg; 1816 1817 r820t_vga_adjust(priv); 1818 1819 rc = r820t_imr_cross(priv, compare_iq, &x_direction); 1820 if (rc < 0) 1821 return rc; 1822 1823 if (x_direction == 1) { 1824 dir_reg = 0x08; 1825 other_reg = 0x09; 1826 } else { 1827 dir_reg = 0x09; 1828 other_reg = 0x08; 1829 } 1830 1831 /* compare and find min of 3 points. determine i/q direction */ 1832 r820t_compre_cor(compare_iq); 1833 1834 /* increase step to find min value of this direction */ 1835 rc = r820t_compre_step(priv, compare_iq, dir_reg); 1836 if (rc < 0) 1837 return rc; 1838 1839 /* the other direction */ 1840 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1841 compare_iq[0].phase_y, dir_reg); 1842 if (rc < 0) 1843 return rc; 1844 1845 /* compare and find min of 3 points. determine i/q direction */ 1846 r820t_compre_cor(compare_iq); 1847 1848 /* increase step to find min value on this direction */ 1849 rc = r820t_compre_step(priv, compare_iq, other_reg); 1850 if (rc < 0) 1851 return rc; 1852 1853 /* check 3 points again */ 1854 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1855 compare_iq[0].phase_y, other_reg); 1856 if (rc < 0) 1857 return rc; 1858 1859 r820t_compre_cor(compare_iq); 1860 1861 /* section-9 check */ 1862 rc = r820t_section(priv, compare_iq); 1863 1864 *iq_pont = compare_iq[0]; 1865 1866 /* reset gain/phase control setting */ 1867 rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f); 1868 if (rc < 0) 1869 return rc; 1870 1871 rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f); 1872 1873 return rc; 1874} 1875 1876static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont) 1877{ 1878 int rc; 1879 1880 r820t_vga_adjust(priv); 1881 1882 /* 1883 * search surrounding points from previous point 1884 * try (x-1), (x), (x+1) columns, and find min IMR result point 1885 */ 1886 rc = r820t_section(priv, iq_pont); 1887 if (rc < 0) 1888 return rc; 1889 1890 return 0; 1891} 1892 1893static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag) 1894{ 1895 struct r820t_sect_type imr_point; 1896 int rc; 1897 u32 ring_vco, ring_freq, ring_ref; 1898 u8 n_ring, n; 1899 int reg18, reg19, reg1f; 1900 1901 if (priv->cfg->xtal > 24000000) 1902 ring_ref = priv->cfg->xtal / 2000; 1903 else 1904 ring_ref = priv->cfg->xtal / 1000; 1905 1906 n_ring = 15; 1907 for (n = 0; n < 16; n++) { 1908 if ((16 + n) * 8 * ring_ref >= 3100000) { 1909 n_ring = n; 1910 break; 1911 } 1912 } 1913 1914 reg18 = r820t_read_cache_reg(priv, 0x18); 1915 reg19 = r820t_read_cache_reg(priv, 0x19); 1916 reg1f = r820t_read_cache_reg(priv, 0x1f); 1917 1918 reg18 &= 0xf0; /* set ring[3:0] */ 1919 reg18 |= n_ring; 1920 1921 ring_vco = (16 + n_ring) * 8 * ring_ref; 1922 1923 reg18 &= 0xdf; /* clear ring_se23 */ 1924 reg19 &= 0xfc; /* clear ring_seldiv */ 1925 reg1f &= 0xfc; /* clear ring_att */ 1926 1927 switch (imr_mem) { 1928 case 0: 1929 ring_freq = ring_vco / 48; 1930 reg18 |= 0x20; /* ring_se23 = 1 */ 1931 reg19 |= 0x03; /* ring_seldiv = 3 */ 1932 reg1f |= 0x02; /* ring_att 10 */ 1933 break; 1934 case 1: 1935 ring_freq = ring_vco / 16; 1936 reg18 |= 0x00; /* ring_se23 = 0 */ 1937 reg19 |= 0x02; /* ring_seldiv = 2 */ 1938 reg1f |= 0x00; /* pw_ring 00 */ 1939 break; 1940 case 2: 1941 ring_freq = ring_vco / 8; 1942 reg18 |= 0x00; /* ring_se23 = 0 */ 1943 reg19 |= 0x01; /* ring_seldiv = 1 */ 1944 reg1f |= 0x03; /* pw_ring 11 */ 1945 break; 1946 case 3: 1947 ring_freq = ring_vco / 6; 1948 reg18 |= 0x20; /* ring_se23 = 1 */ 1949 reg19 |= 0x00; /* ring_seldiv = 0 */ 1950 reg1f |= 0x03; /* pw_ring 11 */ 1951 break; 1952 case 4: 1953 ring_freq = ring_vco / 4; 1954 reg18 |= 0x00; /* ring_se23 = 0 */ 1955 reg19 |= 0x00; /* ring_seldiv = 0 */ 1956 reg1f |= 0x01; /* pw_ring 01 */ 1957 break; 1958 default: 1959 ring_freq = ring_vco / 4; 1960 reg18 |= 0x00; /* ring_se23 = 0 */ 1961 reg19 |= 0x00; /* ring_seldiv = 0 */ 1962 reg1f |= 0x01; /* pw_ring 01 */ 1963 break; 1964 } 1965 1966 1967 /* write pw_ring, n_ring, ringdiv2 registers */ 1968 1969 /* n_ring, ring_se23 */ 1970 rc = r820t_write_reg(priv, 0x18, reg18); 1971 if (rc < 0) 1972 return rc; 1973 1974 /* ring_sediv */ 1975 rc = r820t_write_reg(priv, 0x19, reg19); 1976 if (rc < 0) 1977 return rc; 1978 1979 /* pw_ring */ 1980 rc = r820t_write_reg(priv, 0x1f, reg1f); 1981 if (rc < 0) 1982 return rc; 1983 1984 /* mux input freq ~ rf_in freq */ 1985 rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000); 1986 if (rc < 0) 1987 return rc; 1988 1989 rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV, 1990 (ring_freq - 5300) * 1000); 1991 if (!priv->has_lock) 1992 rc = -EINVAL; 1993 if (rc < 0) 1994 return rc; 1995 1996 if (im_flag) { 1997 rc = r820t_iq(priv, &imr_point); 1998 } else { 1999 imr_point.gain_x = priv->imr_data[3].gain_x; 2000 imr_point.phase_y = priv->imr_data[3].phase_y; 2001 imr_point.value = priv->imr_data[3].value; 2002 2003 rc = r820t_f_imr(priv, &imr_point); 2004 } 2005 if (rc < 0) 2006 return rc; 2007 2008 /* save IMR value */ 2009 switch (imr_mem) { 2010 case 0: 2011 priv->imr_data[0].gain_x = imr_point.gain_x; 2012 priv->imr_data[0].phase_y = imr_point.phase_y; 2013 priv->imr_data[0].value = imr_point.value; 2014 break; 2015 case 1: 2016 priv->imr_data[1].gain_x = imr_point.gain_x; 2017 priv->imr_data[1].phase_y = imr_point.phase_y; 2018 priv->imr_data[1].value = imr_point.value; 2019 break; 2020 case 2: 2021 priv->imr_data[2].gain_x = imr_point.gain_x; 2022 priv->imr_data[2].phase_y = imr_point.phase_y; 2023 priv->imr_data[2].value = imr_point.value; 2024 break; 2025 case 3: 2026 priv->imr_data[3].gain_x = imr_point.gain_x; 2027 priv->imr_data[3].phase_y = imr_point.phase_y; 2028 priv->imr_data[3].value = imr_point.value; 2029 break; 2030 case 4: 2031 priv->imr_data[4].gain_x = imr_point.gain_x; 2032 priv->imr_data[4].phase_y = imr_point.phase_y; 2033 priv->imr_data[4].value = imr_point.value; 2034 break; 2035 default: 2036 priv->imr_data[4].gain_x = imr_point.gain_x; 2037 priv->imr_data[4].phase_y = imr_point.phase_y; 2038 priv->imr_data[4].value = imr_point.value; 2039 break; 2040 } 2041 2042 return 0; 2043} 2044 2045static int r820t_imr_callibrate(struct r820t_priv *priv) 2046{ 2047 int rc, i; 2048 int xtal_cap = 0; 2049 2050 if (priv->init_done) 2051 return 0; 2052 2053 /* Detect Xtal capacitance */ 2054 if ((priv->cfg->rafael_chip == CHIP_R820T) || 2055 (priv->cfg->rafael_chip == CHIP_R828S) || 2056 (priv->cfg->rafael_chip == CHIP_R820C)) { 2057 priv->xtal_cap_sel = XTAL_HIGH_CAP_0P; 2058 } else { 2059 /* Initialize registers */ 2060 rc = r820t_write(priv, 0x05, 2061 r820t_init_array, sizeof(r820t_init_array)); 2062 if (rc < 0) 2063 return rc; 2064 for (i = 0; i < 3; i++) { 2065 rc = r820t_xtal_check(priv); 2066 if (rc < 0) 2067 return rc; 2068 if (!i || rc > xtal_cap) 2069 xtal_cap = rc; 2070 } 2071 priv->xtal_cap_sel = xtal_cap; 2072 } 2073 2074 /* 2075 * Disables IMR callibration. That emulates the same behaviour 2076 * as what is done by rtl-sdr userspace library. Useful for testing 2077 */ 2078 if (no_imr_cal) { 2079 priv->init_done = true; 2080 2081 return 0; 2082 } 2083 2084 /* Initialize registers */ 2085 rc = r820t_write(priv, 0x05, 2086 r820t_init_array, sizeof(r820t_init_array)); 2087 if (rc < 0) 2088 return rc; 2089 2090 rc = r820t_imr_prepare(priv); 2091 if (rc < 0) 2092 return rc; 2093 2094 rc = r820t_imr(priv, 3, true); 2095 if (rc < 0) 2096 return rc; 2097 rc = r820t_imr(priv, 1, false); 2098 if (rc < 0) 2099 return rc; 2100 rc = r820t_imr(priv, 0, false); 2101 if (rc < 0) 2102 return rc; 2103 rc = r820t_imr(priv, 2, false); 2104 if (rc < 0) 2105 return rc; 2106 rc = r820t_imr(priv, 4, false); 2107 if (rc < 0) 2108 return rc; 2109 2110 priv->init_done = true; 2111 priv->imr_done = true; 2112 2113 return 0; 2114} 2115 2116#if 0 2117/* Not used, for now */ 2118static int r820t_gpio(struct r820t_priv *priv, bool enable) 2119{ 2120 return r820t_write_reg_mask(priv, 0x0f, enable ? 1 : 0, 0x01); 2121} 2122#endif 2123 2124/* 2125 * r820t frontend operations and tuner attach code 2126 * 2127 * All driver locks and i2c control are only in this part of the code 2128 */ 2129 2130static int r820t_init(struct dvb_frontend *fe) 2131{ 2132 struct r820t_priv *priv = fe->tuner_priv; 2133 int rc; 2134 2135 tuner_dbg("%s:\n", __func__); 2136 2137 mutex_lock(&priv->lock); 2138 if (fe->ops.i2c_gate_ctrl) 2139 fe->ops.i2c_gate_ctrl(fe, 1); 2140 2141 rc = r820t_imr_callibrate(priv); 2142 if (rc < 0) 2143 goto err; 2144 2145 /* Initialize registers */ 2146 rc = r820t_write(priv, 0x05, 2147 r820t_init_array, sizeof(r820t_init_array)); 2148 2149err: 2150 if (fe->ops.i2c_gate_ctrl) 2151 fe->ops.i2c_gate_ctrl(fe, 0); 2152 mutex_unlock(&priv->lock); 2153 2154 if (rc < 0) 2155 tuner_dbg("%s: failed=%d\n", __func__, rc); 2156 return rc; 2157} 2158 2159static int r820t_sleep(struct dvb_frontend *fe) 2160{ 2161 struct r820t_priv *priv = fe->tuner_priv; 2162 int rc; 2163 2164 tuner_dbg("%s:\n", __func__); 2165 2166 mutex_lock(&priv->lock); 2167 if (fe->ops.i2c_gate_ctrl) 2168 fe->ops.i2c_gate_ctrl(fe, 1); 2169 2170 rc = r820t_standby(priv); 2171 2172 if (fe->ops.i2c_gate_ctrl) 2173 fe->ops.i2c_gate_ctrl(fe, 0); 2174 mutex_unlock(&priv->lock); 2175 2176 tuner_dbg("%s: failed=%d\n", __func__, rc); 2177 return rc; 2178} 2179 2180static int r820t_set_analog_freq(struct dvb_frontend *fe, 2181 struct analog_parameters *p) 2182{ 2183 struct r820t_priv *priv = fe->tuner_priv; 2184 unsigned bw; 2185 int rc; 2186 2187 tuner_dbg("%s called\n", __func__); 2188 2189 /* if std is not defined, choose one */ 2190 if (!p->std) 2191 p->std = V4L2_STD_MN; 2192 2193 if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC)) 2194 bw = 6; 2195 else 2196 bw = 8; 2197 2198 mutex_lock(&priv->lock); 2199 if (fe->ops.i2c_gate_ctrl) 2200 fe->ops.i2c_gate_ctrl(fe, 1); 2201 2202 rc = generic_set_freq(fe, 62500l * p->frequency, bw, 2203 V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED); 2204 2205 if (fe->ops.i2c_gate_ctrl) 2206 fe->ops.i2c_gate_ctrl(fe, 0); 2207 mutex_unlock(&priv->lock); 2208 2209 return rc; 2210} 2211 2212static int r820t_set_params(struct dvb_frontend *fe) 2213{ 2214 struct r820t_priv *priv = fe->tuner_priv; 2215 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 2216 int rc; 2217 unsigned bw; 2218 2219 tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n", 2220 __func__, c->delivery_system, c->frequency, c->bandwidth_hz); 2221 2222 mutex_lock(&priv->lock); 2223 if (fe->ops.i2c_gate_ctrl) 2224 fe->ops.i2c_gate_ctrl(fe, 1); 2225 2226 bw = (c->bandwidth_hz + 500000) / 1000000; 2227 if (!bw) 2228 bw = 8; 2229 2230 rc = generic_set_freq(fe, c->frequency, bw, 2231 V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system); 2232 2233 if (fe->ops.i2c_gate_ctrl) 2234 fe->ops.i2c_gate_ctrl(fe, 0); 2235 mutex_unlock(&priv->lock); 2236 2237 if (rc) 2238 tuner_dbg("%s: failed=%d\n", __func__, rc); 2239 return rc; 2240} 2241 2242static int r820t_signal(struct dvb_frontend *fe, u16 *strength) 2243{ 2244 struct r820t_priv *priv = fe->tuner_priv; 2245 int rc = 0; 2246 2247 mutex_lock(&priv->lock); 2248 if (fe->ops.i2c_gate_ctrl) 2249 fe->ops.i2c_gate_ctrl(fe, 1); 2250 2251 if (priv->has_lock) { 2252 rc = r820t_read_gain(priv); 2253 if (rc < 0) 2254 goto err; 2255 2256 /* A higher gain at LNA means a lower signal strength */ 2257 *strength = (45 - rc) << 4 | 0xff; 2258 if (*strength == 0xff) 2259 *strength = 0; 2260 } else { 2261 *strength = 0; 2262 } 2263 2264err: 2265 if (fe->ops.i2c_gate_ctrl) 2266 fe->ops.i2c_gate_ctrl(fe, 0); 2267 mutex_unlock(&priv->lock); 2268 2269 tuner_dbg("%s: %s, gain=%d strength=%d\n", 2270 __func__, 2271 priv->has_lock ? "PLL locked" : "no signal", 2272 rc, *strength); 2273 2274 return 0; 2275} 2276 2277static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) 2278{ 2279 struct r820t_priv *priv = fe->tuner_priv; 2280 2281 tuner_dbg("%s:\n", __func__); 2282 2283 *frequency = priv->int_freq; 2284 2285 return 0; 2286} 2287 2288static int r820t_release(struct dvb_frontend *fe) 2289{ 2290 struct r820t_priv *priv = fe->tuner_priv; 2291 2292 tuner_dbg("%s:\n", __func__); 2293 2294 mutex_lock(&r820t_list_mutex); 2295 2296 if (priv) 2297 hybrid_tuner_release_state(priv); 2298 2299 mutex_unlock(&r820t_list_mutex); 2300 2301 fe->tuner_priv = NULL; 2302 2303 return 0; 2304} 2305 2306static const struct dvb_tuner_ops r820t_tuner_ops = { 2307 .info = { 2308 .name = "Rafael Micro R820T", 2309 .frequency_min = 42000000, 2310 .frequency_max = 1002000000, 2311 }, 2312 .init = r820t_init, 2313 .release = r820t_release, 2314 .sleep = r820t_sleep, 2315 .set_params = r820t_set_params, 2316 .set_analog_params = r820t_set_analog_freq, 2317 .get_if_frequency = r820t_get_if_frequency, 2318 .get_rf_strength = r820t_signal, 2319}; 2320 2321struct dvb_frontend *r820t_attach(struct dvb_frontend *fe, 2322 struct i2c_adapter *i2c, 2323 const struct r820t_config *cfg) 2324{ 2325 struct r820t_priv *priv; 2326 int rc = -ENODEV; 2327 u8 data[5]; 2328 int instance; 2329 2330 mutex_lock(&r820t_list_mutex); 2331 2332 instance = hybrid_tuner_request_state(struct r820t_priv, priv, 2333 hybrid_tuner_instance_list, 2334 i2c, cfg->i2c_addr, 2335 "r820t"); 2336 switch (instance) { 2337 case 0: 2338 /* memory allocation failure */ 2339 goto err_no_gate; 2340 case 1: 2341 /* new tuner instance */ 2342 priv->cfg = cfg; 2343 2344 mutex_init(&priv->lock); 2345 2346 fe->tuner_priv = priv; 2347 break; 2348 case 2: 2349 /* existing tuner instance */ 2350 fe->tuner_priv = priv; 2351 break; 2352 } 2353 2354 if (fe->ops.i2c_gate_ctrl) 2355 fe->ops.i2c_gate_ctrl(fe, 1); 2356 2357 /* check if the tuner is there */ 2358 rc = r820t_read(priv, 0x00, data, sizeof(data)); 2359 if (rc < 0) 2360 goto err; 2361 2362 rc = r820t_sleep(fe); 2363 if (rc < 0) 2364 goto err; 2365 2366 tuner_info("Rafael Micro r820t successfully identified\n"); 2367 2368 if (fe->ops.i2c_gate_ctrl) 2369 fe->ops.i2c_gate_ctrl(fe, 0); 2370 2371 mutex_unlock(&r820t_list_mutex); 2372 2373 memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops, 2374 sizeof(struct dvb_tuner_ops)); 2375 2376 return fe; 2377err: 2378 if (fe->ops.i2c_gate_ctrl) 2379 fe->ops.i2c_gate_ctrl(fe, 0); 2380 2381err_no_gate: 2382 mutex_unlock(&r820t_list_mutex); 2383 2384 tuner_info("%s: failed=%d\n", __func__, rc); 2385 r820t_release(fe); 2386 return NULL; 2387} 2388EXPORT_SYMBOL_GPL(r820t_attach); 2389 2390MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver"); 2391MODULE_AUTHOR("Mauro Carvalho Chehab"); 2392MODULE_LICENSE("GPL"); 2393