1/* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14#include <linux/blkdev.h> 15#include <linux/clk.h> 16#include <linux/debugfs.h> 17#include <linux/device.h> 18#include <linux/dma-mapping.h> 19#include <linux/err.h> 20#include <linux/init.h> 21#include <linux/interrupt.h> 22#include <linux/ioport.h> 23#include <linux/module.h> 24#include <linux/platform_device.h> 25#include <linux/seq_file.h> 26#include <linux/slab.h> 27#include <linux/stat.h> 28#include <linux/delay.h> 29#include <linux/irq.h> 30#include <linux/mmc/card.h> 31#include <linux/mmc/host.h> 32#include <linux/mmc/mmc.h> 33#include <linux/mmc/sd.h> 34#include <linux/mmc/sdio.h> 35#include <linux/mmc/dw_mmc.h> 36#include <linux/bitops.h> 37#include <linux/regulator/consumer.h> 38#include <linux/of.h> 39#include <linux/of_gpio.h> 40#include <linux/mmc/slot-gpio.h> 41 42#include "dw_mmc.h" 43 44/* Common flag combinations */ 45#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 46 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 47 SDMMC_INT_EBE) 48#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 49 SDMMC_INT_RESP_ERR) 50#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) 52#define DW_MCI_SEND_STATUS 1 53#define DW_MCI_RECV_STATUS 2 54#define DW_MCI_DMA_THRESHOLD 16 55 56#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 57#define DW_MCI_FREQ_MIN 400000 /* unit: HZ */ 58 59#ifdef CONFIG_MMC_DW_IDMAC 60#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63 SDMMC_IDMAC_INT_TI) 64 65struct idmac_desc_64addr { 66 u32 des0; /* Control Descriptor */ 67 68 u32 des1; /* Reserved */ 69 70 u32 des2; /*Buffer sizes */ 71#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 72 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 73 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 74 75 u32 des3; /* Reserved */ 76 77 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 78 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 79 80 u32 des6; /* Lower 32-bits of Next Descriptor Address */ 81 u32 des7; /* Upper 32-bits of Next Descriptor Address */ 82}; 83 84struct idmac_desc { 85 __le32 des0; /* Control Descriptor */ 86#define IDMAC_DES0_DIC BIT(1) 87#define IDMAC_DES0_LD BIT(2) 88#define IDMAC_DES0_FD BIT(3) 89#define IDMAC_DES0_CH BIT(4) 90#define IDMAC_DES0_ER BIT(5) 91#define IDMAC_DES0_CES BIT(30) 92#define IDMAC_DES0_OWN BIT(31) 93 94 __le32 des1; /* Buffer sizes */ 95#define IDMAC_SET_BUFFER1_SIZE(d, s) \ 96 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) 97 98 __le32 des2; /* buffer 1 physical address */ 99 100 __le32 des3; /* buffer 2 physical address */ 101}; 102 103/* Each descriptor can transfer up to 4KB of data in chained mode */ 104#define DW_MCI_DESC_DATA_LENGTH 0x1000 105#endif /* CONFIG_MMC_DW_IDMAC */ 106 107static bool dw_mci_reset(struct dw_mci *host); 108static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); 109static int dw_mci_card_busy(struct mmc_host *mmc); 110 111#if defined(CONFIG_DEBUG_FS) 112static int dw_mci_req_show(struct seq_file *s, void *v) 113{ 114 struct dw_mci_slot *slot = s->private; 115 struct mmc_request *mrq; 116 struct mmc_command *cmd; 117 struct mmc_command *stop; 118 struct mmc_data *data; 119 120 /* Make sure we get a consistent snapshot */ 121 spin_lock_bh(&slot->host->lock); 122 mrq = slot->mrq; 123 124 if (mrq) { 125 cmd = mrq->cmd; 126 data = mrq->data; 127 stop = mrq->stop; 128 129 if (cmd) 130 seq_printf(s, 131 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 132 cmd->opcode, cmd->arg, cmd->flags, 133 cmd->resp[0], cmd->resp[1], cmd->resp[2], 134 cmd->resp[2], cmd->error); 135 if (data) 136 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 137 data->bytes_xfered, data->blocks, 138 data->blksz, data->flags, data->error); 139 if (stop) 140 seq_printf(s, 141 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 142 stop->opcode, stop->arg, stop->flags, 143 stop->resp[0], stop->resp[1], stop->resp[2], 144 stop->resp[2], stop->error); 145 } 146 147 spin_unlock_bh(&slot->host->lock); 148 149 return 0; 150} 151 152static int dw_mci_req_open(struct inode *inode, struct file *file) 153{ 154 return single_open(file, dw_mci_req_show, inode->i_private); 155} 156 157static const struct file_operations dw_mci_req_fops = { 158 .owner = THIS_MODULE, 159 .open = dw_mci_req_open, 160 .read = seq_read, 161 .llseek = seq_lseek, 162 .release = single_release, 163}; 164 165static int dw_mci_regs_show(struct seq_file *s, void *v) 166{ 167 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 168 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 169 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 170 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 171 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 172 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 173 174 return 0; 175} 176 177static int dw_mci_regs_open(struct inode *inode, struct file *file) 178{ 179 return single_open(file, dw_mci_regs_show, inode->i_private); 180} 181 182static const struct file_operations dw_mci_regs_fops = { 183 .owner = THIS_MODULE, 184 .open = dw_mci_regs_open, 185 .read = seq_read, 186 .llseek = seq_lseek, 187 .release = single_release, 188}; 189 190static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 191{ 192 struct mmc_host *mmc = slot->mmc; 193 struct dw_mci *host = slot->host; 194 struct dentry *root; 195 struct dentry *node; 196 197 root = mmc->debugfs_root; 198 if (!root) 199 return; 200 201 node = debugfs_create_file("regs", S_IRUSR, root, host, 202 &dw_mci_regs_fops); 203 if (!node) 204 goto err; 205 206 node = debugfs_create_file("req", S_IRUSR, root, slot, 207 &dw_mci_req_fops); 208 if (!node) 209 goto err; 210 211 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 212 if (!node) 213 goto err; 214 215 node = debugfs_create_x32("pending_events", S_IRUSR, root, 216 (u32 *)&host->pending_events); 217 if (!node) 218 goto err; 219 220 node = debugfs_create_x32("completed_events", S_IRUSR, root, 221 (u32 *)&host->completed_events); 222 if (!node) 223 goto err; 224 225 return; 226 227err: 228 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 229} 230#endif /* defined(CONFIG_DEBUG_FS) */ 231 232static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg); 233 234static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 235{ 236 struct mmc_data *data; 237 struct dw_mci_slot *slot = mmc_priv(mmc); 238 struct dw_mci *host = slot->host; 239 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 240 u32 cmdr; 241 cmd->error = -EINPROGRESS; 242 243 cmdr = cmd->opcode; 244 245 if (cmd->opcode == MMC_STOP_TRANSMISSION || 246 cmd->opcode == MMC_GO_IDLE_STATE || 247 cmd->opcode == MMC_GO_INACTIVE_STATE || 248 (cmd->opcode == SD_IO_RW_DIRECT && 249 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 250 cmdr |= SDMMC_CMD_STOP; 251 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 252 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 253 254 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 255 u32 clk_en_a; 256 257 /* Special bit makes CMD11 not die */ 258 cmdr |= SDMMC_CMD_VOLT_SWITCH; 259 260 /* Change state to continue to handle CMD11 weirdness */ 261 WARN_ON(slot->host->state != STATE_SENDING_CMD); 262 slot->host->state = STATE_SENDING_CMD11; 263 264 /* 265 * We need to disable low power mode (automatic clock stop) 266 * while doing voltage switch so we don't confuse the card, 267 * since stopping the clock is a specific part of the UHS 268 * voltage change dance. 269 * 270 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 271 * unconditionally turned back on in dw_mci_setup_bus() if it's 272 * ever called with a non-zero clock. That shouldn't happen 273 * until the voltage change is all done. 274 */ 275 clk_en_a = mci_readl(host, CLKENA); 276 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 277 mci_writel(host, CLKENA, clk_en_a); 278 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 279 SDMMC_CMD_PRV_DAT_WAIT, 0); 280 } 281 282 if (cmd->flags & MMC_RSP_PRESENT) { 283 /* We expect a response, so set this bit */ 284 cmdr |= SDMMC_CMD_RESP_EXP; 285 if (cmd->flags & MMC_RSP_136) 286 cmdr |= SDMMC_CMD_RESP_LONG; 287 } 288 289 if (cmd->flags & MMC_RSP_CRC) 290 cmdr |= SDMMC_CMD_RESP_CRC; 291 292 data = cmd->data; 293 if (data) { 294 cmdr |= SDMMC_CMD_DAT_EXP; 295 if (data->flags & MMC_DATA_STREAM) 296 cmdr |= SDMMC_CMD_STRM_MODE; 297 if (data->flags & MMC_DATA_WRITE) 298 cmdr |= SDMMC_CMD_DAT_WR; 299 } 300 301 if (drv_data && drv_data->prepare_command) 302 drv_data->prepare_command(slot->host, &cmdr); 303 304 return cmdr; 305} 306 307static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 308{ 309 struct mmc_command *stop; 310 u32 cmdr; 311 312 if (!cmd->data) 313 return 0; 314 315 stop = &host->stop_abort; 316 cmdr = cmd->opcode; 317 memset(stop, 0, sizeof(struct mmc_command)); 318 319 if (cmdr == MMC_READ_SINGLE_BLOCK || 320 cmdr == MMC_READ_MULTIPLE_BLOCK || 321 cmdr == MMC_WRITE_BLOCK || 322 cmdr == MMC_WRITE_MULTIPLE_BLOCK || 323 cmdr == MMC_SEND_TUNING_BLOCK || 324 cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 325 stop->opcode = MMC_STOP_TRANSMISSION; 326 stop->arg = 0; 327 stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 328 } else if (cmdr == SD_IO_RW_EXTENDED) { 329 stop->opcode = SD_IO_RW_DIRECT; 330 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 331 ((cmd->arg >> 28) & 0x7); 332 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 333 } else { 334 return 0; 335 } 336 337 cmdr = stop->opcode | SDMMC_CMD_STOP | 338 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 339 340 return cmdr; 341} 342 343static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 344{ 345 unsigned long timeout = jiffies + msecs_to_jiffies(500); 346 347 /* 348 * Databook says that before issuing a new data transfer command 349 * we need to check to see if the card is busy. Data transfer commands 350 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 351 * 352 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 353 * expected. 354 */ 355 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 356 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 357 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) { 358 if (time_after(jiffies, timeout)) { 359 /* Command will fail; we'll pass error then */ 360 dev_err(host->dev, "Busy; trying anyway\n"); 361 break; 362 } 363 udelay(10); 364 } 365 } 366} 367 368static void dw_mci_start_command(struct dw_mci *host, 369 struct mmc_command *cmd, u32 cmd_flags) 370{ 371 host->cmd = cmd; 372 dev_vdbg(host->dev, 373 "start command: ARGR=0x%08x CMDR=0x%08x\n", 374 cmd->arg, cmd_flags); 375 376 mci_writel(host, CMDARG, cmd->arg); 377 wmb(); 378 dw_mci_wait_while_busy(host, cmd_flags); 379 380 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 381} 382 383static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 384{ 385 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort; 386 dw_mci_start_command(host, stop, host->stop_cmdr); 387} 388 389/* DMA interface functions */ 390static void dw_mci_stop_dma(struct dw_mci *host) 391{ 392 if (host->using_dma) { 393 host->dma_ops->stop(host); 394 host->dma_ops->cleanup(host); 395 } 396 397 /* Data transfer was stopped by the interrupt handler */ 398 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 399} 400 401static int dw_mci_get_dma_dir(struct mmc_data *data) 402{ 403 if (data->flags & MMC_DATA_WRITE) 404 return DMA_TO_DEVICE; 405 else 406 return DMA_FROM_DEVICE; 407} 408 409#ifdef CONFIG_MMC_DW_IDMAC 410static void dw_mci_dma_cleanup(struct dw_mci *host) 411{ 412 struct mmc_data *data = host->data; 413 414 if (data) 415 if (!data->host_cookie) 416 dma_unmap_sg(host->dev, 417 data->sg, 418 data->sg_len, 419 dw_mci_get_dma_dir(data)); 420} 421 422static void dw_mci_idmac_reset(struct dw_mci *host) 423{ 424 u32 bmod = mci_readl(host, BMOD); 425 /* Software reset of DMA */ 426 bmod |= SDMMC_IDMAC_SWRESET; 427 mci_writel(host, BMOD, bmod); 428} 429 430static void dw_mci_idmac_stop_dma(struct dw_mci *host) 431{ 432 u32 temp; 433 434 /* Disable and reset the IDMAC interface */ 435 temp = mci_readl(host, CTRL); 436 temp &= ~SDMMC_CTRL_USE_IDMAC; 437 temp |= SDMMC_CTRL_DMA_RESET; 438 mci_writel(host, CTRL, temp); 439 440 /* Stop the IDMAC running */ 441 temp = mci_readl(host, BMOD); 442 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 443 temp |= SDMMC_IDMAC_SWRESET; 444 mci_writel(host, BMOD, temp); 445} 446 447static void dw_mci_idmac_complete_dma(struct dw_mci *host) 448{ 449 struct mmc_data *data = host->data; 450 451 dev_vdbg(host->dev, "DMA complete\n"); 452 453 host->dma_ops->cleanup(host); 454 455 /* 456 * If the card was removed, data will be NULL. No point in trying to 457 * send the stop command or waiting for NBUSY in this case. 458 */ 459 if (data) { 460 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 461 tasklet_schedule(&host->tasklet); 462 } 463} 464 465static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, 466 unsigned int sg_len) 467{ 468 unsigned int desc_len; 469 int i; 470 if (host->dma_64bit_address == 1) { 471 struct idmac_desc_64addr *desc_first, *desc_last, *desc; 472 473 desc_first = desc_last = desc = host->sg_cpu; 474 475 for (i = 0; i < sg_len; i++) { 476 unsigned int length = sg_dma_len(&data->sg[i]); 477 u64 mem_addr = sg_dma_address(&data->sg[i]); 478 479 for ( ; length ; desc++) { 480 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 481 length : DW_MCI_DESC_DATA_LENGTH; 482 483 length -= desc_len; 484 485 /* 486 * Set the OWN bit and disable interrupts 487 * for this descriptor 488 */ 489 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 490 IDMAC_DES0_CH; 491 492 /* Buffer length */ 493 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 494 495 /* Physical address to DMA to/from */ 496 desc->des4 = mem_addr & 0xffffffff; 497 desc->des5 = mem_addr >> 32; 498 499 /* Update physical address for the next desc */ 500 mem_addr += desc_len; 501 502 /* Save pointer to the last descriptor */ 503 desc_last = desc; 504 } 505 } 506 507 /* Set first descriptor */ 508 desc_first->des0 |= IDMAC_DES0_FD; 509 510 /* Set last descriptor */ 511 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 512 desc_last->des0 |= IDMAC_DES0_LD; 513 514 } else { 515 struct idmac_desc *desc_first, *desc_last, *desc; 516 517 desc_first = desc_last = desc = host->sg_cpu; 518 519 for (i = 0; i < sg_len; i++) { 520 unsigned int length = sg_dma_len(&data->sg[i]); 521 u32 mem_addr = sg_dma_address(&data->sg[i]); 522 523 for ( ; length ; desc++) { 524 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 525 length : DW_MCI_DESC_DATA_LENGTH; 526 527 length -= desc_len; 528 529 /* 530 * Set the OWN bit and disable interrupts 531 * for this descriptor 532 */ 533 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 534 IDMAC_DES0_DIC | 535 IDMAC_DES0_CH); 536 537 /* Buffer length */ 538 IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 539 540 /* Physical address to DMA to/from */ 541 desc->des2 = cpu_to_le32(mem_addr); 542 543 /* Update physical address for the next desc */ 544 mem_addr += desc_len; 545 546 /* Save pointer to the last descriptor */ 547 desc_last = desc; 548 } 549 } 550 551 /* Set first descriptor */ 552 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 553 554 /* Set last descriptor */ 555 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 556 IDMAC_DES0_DIC)); 557 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 558 } 559 560 wmb(); 561} 562 563static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 564{ 565 u32 temp; 566 567 dw_mci_translate_sglist(host, host->data, sg_len); 568 569 /* Make sure to reset DMA in case we did PIO before this */ 570 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 571 dw_mci_idmac_reset(host); 572 573 /* Select IDMAC interface */ 574 temp = mci_readl(host, CTRL); 575 temp |= SDMMC_CTRL_USE_IDMAC; 576 mci_writel(host, CTRL, temp); 577 578 wmb(); 579 580 /* Enable the IDMAC */ 581 temp = mci_readl(host, BMOD); 582 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 583 mci_writel(host, BMOD, temp); 584 585 /* Start it running */ 586 mci_writel(host, PLDMND, 1); 587} 588 589static int dw_mci_idmac_init(struct dw_mci *host) 590{ 591 int i; 592 593 if (host->dma_64bit_address == 1) { 594 struct idmac_desc_64addr *p; 595 /* Number of descriptors in the ring buffer */ 596 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr); 597 598 /* Forward link the descriptor list */ 599 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 600 i++, p++) { 601 p->des6 = (host->sg_dma + 602 (sizeof(struct idmac_desc_64addr) * 603 (i + 1))) & 0xffffffff; 604 605 p->des7 = (u64)(host->sg_dma + 606 (sizeof(struct idmac_desc_64addr) * 607 (i + 1))) >> 32; 608 /* Initialize reserved and buffer size fields to "0" */ 609 p->des1 = 0; 610 p->des2 = 0; 611 p->des3 = 0; 612 } 613 614 /* Set the last descriptor as the end-of-ring descriptor */ 615 p->des6 = host->sg_dma & 0xffffffff; 616 p->des7 = (u64)host->sg_dma >> 32; 617 p->des0 = IDMAC_DES0_ER; 618 619 } else { 620 struct idmac_desc *p; 621 /* Number of descriptors in the ring buffer */ 622 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); 623 624 /* Forward link the descriptor list */ 625 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) { 626 p->des3 = cpu_to_le32(host->sg_dma + 627 (sizeof(struct idmac_desc) * (i + 1))); 628 p->des1 = 0; 629 } 630 631 /* Set the last descriptor as the end-of-ring descriptor */ 632 p->des3 = cpu_to_le32(host->sg_dma); 633 p->des0 = cpu_to_le32(IDMAC_DES0_ER); 634 } 635 636 dw_mci_idmac_reset(host); 637 638 if (host->dma_64bit_address == 1) { 639 /* Mask out interrupts - get Tx & Rx complete only */ 640 mci_writel(host, IDSTS64, IDMAC_INT_CLR); 641 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 642 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 643 644 /* Set the descriptor base address */ 645 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 646 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 647 648 } else { 649 /* Mask out interrupts - get Tx & Rx complete only */ 650 mci_writel(host, IDSTS, IDMAC_INT_CLR); 651 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 652 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 653 654 /* Set the descriptor base address */ 655 mci_writel(host, DBADDR, host->sg_dma); 656 } 657 658 return 0; 659} 660 661static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 662 .init = dw_mci_idmac_init, 663 .start = dw_mci_idmac_start_dma, 664 .stop = dw_mci_idmac_stop_dma, 665 .complete = dw_mci_idmac_complete_dma, 666 .cleanup = dw_mci_dma_cleanup, 667}; 668#endif /* CONFIG_MMC_DW_IDMAC */ 669 670static int dw_mci_pre_dma_transfer(struct dw_mci *host, 671 struct mmc_data *data, 672 bool next) 673{ 674 struct scatterlist *sg; 675 unsigned int i, sg_len; 676 677 if (!next && data->host_cookie) 678 return data->host_cookie; 679 680 /* 681 * We don't do DMA on "complex" transfers, i.e. with 682 * non-word-aligned buffers or lengths. Also, we don't bother 683 * with all the DMA setup overhead for short transfers. 684 */ 685 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 686 return -EINVAL; 687 688 if (data->blksz & 3) 689 return -EINVAL; 690 691 for_each_sg(data->sg, sg, data->sg_len, i) { 692 if (sg->offset & 3 || sg->length & 3) 693 return -EINVAL; 694 } 695 696 sg_len = dma_map_sg(host->dev, 697 data->sg, 698 data->sg_len, 699 dw_mci_get_dma_dir(data)); 700 if (sg_len == 0) 701 return -EINVAL; 702 703 if (next) 704 data->host_cookie = sg_len; 705 706 return sg_len; 707} 708 709static void dw_mci_pre_req(struct mmc_host *mmc, 710 struct mmc_request *mrq, 711 bool is_first_req) 712{ 713 struct dw_mci_slot *slot = mmc_priv(mmc); 714 struct mmc_data *data = mrq->data; 715 716 if (!slot->host->use_dma || !data) 717 return; 718 719 if (data->host_cookie) { 720 data->host_cookie = 0; 721 return; 722 } 723 724 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 725 data->host_cookie = 0; 726} 727 728static void dw_mci_post_req(struct mmc_host *mmc, 729 struct mmc_request *mrq, 730 int err) 731{ 732 struct dw_mci_slot *slot = mmc_priv(mmc); 733 struct mmc_data *data = mrq->data; 734 735 if (!slot->host->use_dma || !data) 736 return; 737 738 if (data->host_cookie) 739 dma_unmap_sg(slot->host->dev, 740 data->sg, 741 data->sg_len, 742 dw_mci_get_dma_dir(data)); 743 data->host_cookie = 0; 744} 745 746static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 747{ 748#ifdef CONFIG_MMC_DW_IDMAC 749 unsigned int blksz = data->blksz; 750 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 751 u32 fifo_width = 1 << host->data_shift; 752 u32 blksz_depth = blksz / fifo_width, fifoth_val; 753 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 754 int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1; 755 756 tx_wmark = (host->fifo_depth) / 2; 757 tx_wmark_invers = host->fifo_depth - tx_wmark; 758 759 /* 760 * MSIZE is '1', 761 * if blksz is not a multiple of the FIFO width 762 */ 763 if (blksz % fifo_width) { 764 msize = 0; 765 rx_wmark = 1; 766 goto done; 767 } 768 769 do { 770 if (!((blksz_depth % mszs[idx]) || 771 (tx_wmark_invers % mszs[idx]))) { 772 msize = idx; 773 rx_wmark = mszs[idx] - 1; 774 break; 775 } 776 } while (--idx > 0); 777 /* 778 * If idx is '0', it won't be tried 779 * Thus, initial values are uesed 780 */ 781done: 782 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 783 mci_writel(host, FIFOTH, fifoth_val); 784#endif 785} 786 787static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data) 788{ 789 unsigned int blksz = data->blksz; 790 u32 blksz_depth, fifo_depth; 791 u16 thld_size; 792 793 WARN_ON(!(data->flags & MMC_DATA_READ)); 794 795 /* 796 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 797 * in the FIFO region, so we really shouldn't access it). 798 */ 799 if (host->verid < DW_MMC_240A) 800 return; 801 802 if (host->timing != MMC_TIMING_MMC_HS200 && 803 host->timing != MMC_TIMING_MMC_HS400 && 804 host->timing != MMC_TIMING_UHS_SDR104) 805 goto disable; 806 807 blksz_depth = blksz / (1 << host->data_shift); 808 fifo_depth = host->fifo_depth; 809 810 if (blksz_depth > fifo_depth) 811 goto disable; 812 813 /* 814 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 815 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 816 * Currently just choose blksz. 817 */ 818 thld_size = blksz; 819 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1)); 820 return; 821 822disable: 823 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0)); 824} 825 826static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 827{ 828 unsigned long irqflags; 829 int sg_len; 830 u32 temp; 831 832 host->using_dma = 0; 833 834 /* If we don't have a channel, we can't do DMA */ 835 if (!host->use_dma) 836 return -ENODEV; 837 838 sg_len = dw_mci_pre_dma_transfer(host, data, 0); 839 if (sg_len < 0) { 840 host->dma_ops->stop(host); 841 return sg_len; 842 } 843 844 host->using_dma = 1; 845 846 dev_vdbg(host->dev, 847 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 848 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, 849 sg_len); 850 851 /* 852 * Decide the MSIZE and RX/TX Watermark. 853 * If current block size is same with previous size, 854 * no need to update fifoth. 855 */ 856 if (host->prev_blksz != data->blksz) 857 dw_mci_adjust_fifoth(host, data); 858 859 /* Enable the DMA interface */ 860 temp = mci_readl(host, CTRL); 861 temp |= SDMMC_CTRL_DMA_ENABLE; 862 mci_writel(host, CTRL, temp); 863 864 /* Disable RX/TX IRQs, let DMA handle it */ 865 spin_lock_irqsave(&host->irq_lock, irqflags); 866 temp = mci_readl(host, INTMASK); 867 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 868 mci_writel(host, INTMASK, temp); 869 spin_unlock_irqrestore(&host->irq_lock, irqflags); 870 871 host->dma_ops->start(host, sg_len); 872 873 return 0; 874} 875 876static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 877{ 878 unsigned long irqflags; 879 u32 temp; 880 881 data->error = -EINPROGRESS; 882 883 WARN_ON(host->data); 884 host->sg = NULL; 885 host->data = data; 886 887 if (data->flags & MMC_DATA_READ) { 888 host->dir_status = DW_MCI_RECV_STATUS; 889 dw_mci_ctrl_rd_thld(host, data); 890 } else { 891 host->dir_status = DW_MCI_SEND_STATUS; 892 } 893 894 if (dw_mci_submit_data_dma(host, data)) { 895 int flags = SG_MITER_ATOMIC; 896 if (host->data->flags & MMC_DATA_READ) 897 flags |= SG_MITER_TO_SG; 898 else 899 flags |= SG_MITER_FROM_SG; 900 901 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 902 host->sg = data->sg; 903 host->part_buf_start = 0; 904 host->part_buf_count = 0; 905 906 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 907 908 spin_lock_irqsave(&host->irq_lock, irqflags); 909 temp = mci_readl(host, INTMASK); 910 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 911 mci_writel(host, INTMASK, temp); 912 spin_unlock_irqrestore(&host->irq_lock, irqflags); 913 914 temp = mci_readl(host, CTRL); 915 temp &= ~SDMMC_CTRL_DMA_ENABLE; 916 mci_writel(host, CTRL, temp); 917 918 /* 919 * Use the initial fifoth_val for PIO mode. 920 * If next issued data may be transfered by DMA mode, 921 * prev_blksz should be invalidated. 922 */ 923 mci_writel(host, FIFOTH, host->fifoth_val); 924 host->prev_blksz = 0; 925 } else { 926 /* 927 * Keep the current block size. 928 * It will be used to decide whether to update 929 * fifoth register next time. 930 */ 931 host->prev_blksz = data->blksz; 932 } 933} 934 935static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 936{ 937 struct dw_mci *host = slot->host; 938 unsigned long timeout = jiffies + msecs_to_jiffies(500); 939 unsigned int cmd_status = 0; 940 941 mci_writel(host, CMDARG, arg); 942 wmb(); 943 dw_mci_wait_while_busy(host, cmd); 944 mci_writel(host, CMD, SDMMC_CMD_START | cmd); 945 946 while (time_before(jiffies, timeout)) { 947 cmd_status = mci_readl(host, CMD); 948 if (!(cmd_status & SDMMC_CMD_START)) 949 return; 950 } 951 dev_err(&slot->mmc->class_dev, 952 "Timeout sending command (cmd %#x arg %#x status %#x)\n", 953 cmd, arg, cmd_status); 954} 955 956static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 957{ 958 struct dw_mci *host = slot->host; 959 unsigned int clock = slot->clock; 960 u32 div; 961 u32 clk_en_a; 962 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 963 964 /* We must continue to set bit 28 in CMD until the change is complete */ 965 if (host->state == STATE_WAITING_CMD11_DONE) 966 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 967 968 if (!clock) { 969 mci_writel(host, CLKENA, 0); 970 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 971 } else if (clock != host->current_speed || force_clkinit) { 972 div = host->bus_hz / clock; 973 if (host->bus_hz % clock && host->bus_hz > clock) 974 /* 975 * move the + 1 after the divide to prevent 976 * over-clocking the card. 977 */ 978 div += 1; 979 980 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 981 982 if ((clock << div) != slot->__clk_old || force_clkinit) 983 dev_info(&slot->mmc->class_dev, 984 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 985 slot->id, host->bus_hz, clock, 986 div ? ((host->bus_hz / div) >> 1) : 987 host->bus_hz, div); 988 989 /* disable clock */ 990 mci_writel(host, CLKENA, 0); 991 mci_writel(host, CLKSRC, 0); 992 993 /* inform CIU */ 994 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 995 996 /* set clock to desired speed */ 997 mci_writel(host, CLKDIV, div); 998 999 /* inform CIU */ 1000 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1001 1002 /* enable clock; only low power if no SDIO */ 1003 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1004 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 1005 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 1006 mci_writel(host, CLKENA, clk_en_a); 1007 1008 /* inform CIU */ 1009 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1010 1011 /* keep the clock with reflecting clock dividor */ 1012 slot->__clk_old = clock << div; 1013 } 1014 1015 host->current_speed = clock; 1016 1017 /* Set the current slot bus width */ 1018 mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1019} 1020 1021static void __dw_mci_start_request(struct dw_mci *host, 1022 struct dw_mci_slot *slot, 1023 struct mmc_command *cmd) 1024{ 1025 struct mmc_request *mrq; 1026 struct mmc_data *data; 1027 u32 cmdflags; 1028 1029 mrq = slot->mrq; 1030 1031 host->cur_slot = slot; 1032 host->mrq = mrq; 1033 1034 host->pending_events = 0; 1035 host->completed_events = 0; 1036 host->cmd_status = 0; 1037 host->data_status = 0; 1038 host->dir_status = 0; 1039 1040 data = cmd->data; 1041 if (data) { 1042 mci_writel(host, TMOUT, 0xFFFFFFFF); 1043 mci_writel(host, BYTCNT, data->blksz*data->blocks); 1044 mci_writel(host, BLKSIZ, data->blksz); 1045 } 1046 1047 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1048 1049 /* this is the first command, send the initialization clock */ 1050 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1051 cmdflags |= SDMMC_CMD_INIT; 1052 1053 if (data) { 1054 dw_mci_submit_data(host, data); 1055 wmb(); 1056 } 1057 1058 dw_mci_start_command(host, cmd, cmdflags); 1059 1060 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 1061 unsigned long irqflags; 1062 1063 /* 1064 * Databook says to fail after 2ms w/ no response, but evidence 1065 * shows that sometimes the cmd11 interrupt takes over 130ms. 1066 * We'll set to 500ms, plus an extra jiffy just in case jiffies 1067 * is just about to roll over. 1068 * 1069 * We do this whole thing under spinlock and only if the 1070 * command hasn't already completed (indicating the the irq 1071 * already ran so we don't want the timeout). 1072 */ 1073 spin_lock_irqsave(&host->irq_lock, irqflags); 1074 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1075 mod_timer(&host->cmd11_timer, 1076 jiffies + msecs_to_jiffies(500) + 1); 1077 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1078 } 1079 1080 if (mrq->stop) 1081 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 1082 else 1083 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1084} 1085 1086static void dw_mci_start_request(struct dw_mci *host, 1087 struct dw_mci_slot *slot) 1088{ 1089 struct mmc_request *mrq = slot->mrq; 1090 struct mmc_command *cmd; 1091 1092 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1093 __dw_mci_start_request(host, slot, cmd); 1094} 1095 1096/* must be called with host->lock held */ 1097static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1098 struct mmc_request *mrq) 1099{ 1100 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1101 host->state); 1102 1103 slot->mrq = mrq; 1104 1105 if (host->state == STATE_WAITING_CMD11_DONE) { 1106 dev_warn(&slot->mmc->class_dev, 1107 "Voltage change didn't complete\n"); 1108 /* 1109 * this case isn't expected to happen, so we can 1110 * either crash here or just try to continue on 1111 * in the closest possible state 1112 */ 1113 host->state = STATE_IDLE; 1114 } 1115 1116 if (host->state == STATE_IDLE) { 1117 host->state = STATE_SENDING_CMD; 1118 dw_mci_start_request(host, slot); 1119 } else { 1120 list_add_tail(&slot->queue_node, &host->queue); 1121 } 1122} 1123 1124static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1125{ 1126 struct dw_mci_slot *slot = mmc_priv(mmc); 1127 struct dw_mci *host = slot->host; 1128 1129 WARN_ON(slot->mrq); 1130 1131 /* 1132 * The check for card presence and queueing of the request must be 1133 * atomic, otherwise the card could be removed in between and the 1134 * request wouldn't fail until another card was inserted. 1135 */ 1136 spin_lock_bh(&host->lock); 1137 1138 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 1139 spin_unlock_bh(&host->lock); 1140 mrq->cmd->error = -ENOMEDIUM; 1141 mmc_request_done(mmc, mrq); 1142 return; 1143 } 1144 1145 dw_mci_queue_request(host, slot, mrq); 1146 1147 spin_unlock_bh(&host->lock); 1148} 1149 1150static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1151{ 1152 struct dw_mci_slot *slot = mmc_priv(mmc); 1153 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 1154 u32 regs; 1155 int ret; 1156 1157 switch (ios->bus_width) { 1158 case MMC_BUS_WIDTH_4: 1159 slot->ctype = SDMMC_CTYPE_4BIT; 1160 break; 1161 case MMC_BUS_WIDTH_8: 1162 slot->ctype = SDMMC_CTYPE_8BIT; 1163 break; 1164 default: 1165 /* set default 1 bit mode */ 1166 slot->ctype = SDMMC_CTYPE_1BIT; 1167 } 1168 1169 regs = mci_readl(slot->host, UHS_REG); 1170 1171 /* DDR mode set */ 1172 if (ios->timing == MMC_TIMING_MMC_DDR52 || 1173 ios->timing == MMC_TIMING_MMC_HS400) 1174 regs |= ((0x1 << slot->id) << 16); 1175 else 1176 regs &= ~((0x1 << slot->id) << 16); 1177 1178 mci_writel(slot->host, UHS_REG, regs); 1179 slot->host->timing = ios->timing; 1180 1181 /* 1182 * Use mirror of ios->clock to prevent race with mmc 1183 * core ios update when finding the minimum. 1184 */ 1185 slot->clock = ios->clock; 1186 1187 if (drv_data && drv_data->set_ios) 1188 drv_data->set_ios(slot->host, ios); 1189 1190 switch (ios->power_mode) { 1191 case MMC_POWER_UP: 1192 if (!IS_ERR(mmc->supply.vmmc)) { 1193 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1194 ios->vdd); 1195 if (ret) { 1196 dev_err(slot->host->dev, 1197 "failed to enable vmmc regulator\n"); 1198 /*return, if failed turn on vmmc*/ 1199 return; 1200 } 1201 } 1202 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 1203 regs = mci_readl(slot->host, PWREN); 1204 regs |= (1 << slot->id); 1205 mci_writel(slot->host, PWREN, regs); 1206 break; 1207 case MMC_POWER_ON: 1208 if (!slot->host->vqmmc_enabled) { 1209 if (!IS_ERR(mmc->supply.vqmmc)) { 1210 ret = regulator_enable(mmc->supply.vqmmc); 1211 if (ret < 0) 1212 dev_err(slot->host->dev, 1213 "failed to enable vqmmc\n"); 1214 else 1215 slot->host->vqmmc_enabled = true; 1216 1217 } else { 1218 /* Keep track so we don't reset again */ 1219 slot->host->vqmmc_enabled = true; 1220 } 1221 1222 /* Reset our state machine after powering on */ 1223 dw_mci_ctrl_reset(slot->host, 1224 SDMMC_CTRL_ALL_RESET_FLAGS); 1225 } 1226 1227 /* Adjust clock / bus width after power is up */ 1228 dw_mci_setup_bus(slot, false); 1229 1230 break; 1231 case MMC_POWER_OFF: 1232 /* Turn clock off before power goes down */ 1233 dw_mci_setup_bus(slot, false); 1234 1235 if (!IS_ERR(mmc->supply.vmmc)) 1236 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1237 1238 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 1239 regulator_disable(mmc->supply.vqmmc); 1240 slot->host->vqmmc_enabled = false; 1241 1242 regs = mci_readl(slot->host, PWREN); 1243 regs &= ~(1 << slot->id); 1244 mci_writel(slot->host, PWREN, regs); 1245 break; 1246 default: 1247 break; 1248 } 1249 1250 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1251 slot->host->state = STATE_IDLE; 1252} 1253 1254static int dw_mci_card_busy(struct mmc_host *mmc) 1255{ 1256 struct dw_mci_slot *slot = mmc_priv(mmc); 1257 u32 status; 1258 1259 /* 1260 * Check the busy bit which is low when DAT[3:0] 1261 * (the data lines) are 0000 1262 */ 1263 status = mci_readl(slot->host, STATUS); 1264 1265 return !!(status & SDMMC_STATUS_BUSY); 1266} 1267 1268static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1269{ 1270 struct dw_mci_slot *slot = mmc_priv(mmc); 1271 struct dw_mci *host = slot->host; 1272 u32 uhs; 1273 u32 v18 = SDMMC_UHS_18V << slot->id; 1274 int min_uv, max_uv; 1275 int ret; 1276 1277 /* 1278 * Program the voltage. Note that some instances of dw_mmc may use 1279 * the UHS_REG for this. For other instances (like exynos) the UHS_REG 1280 * does no harm but you need to set the regulator directly. Try both. 1281 */ 1282 uhs = mci_readl(host, UHS_REG); 1283 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 1284 min_uv = 2700000; 1285 max_uv = 3600000; 1286 uhs &= ~v18; 1287 } else { 1288 min_uv = 1700000; 1289 max_uv = 1950000; 1290 uhs |= v18; 1291 } 1292 if (!IS_ERR(mmc->supply.vqmmc)) { 1293 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); 1294 1295 if (ret) { 1296 dev_dbg(&mmc->class_dev, 1297 "Regulator set error %d: %d - %d\n", 1298 ret, min_uv, max_uv); 1299 return ret; 1300 } 1301 } 1302 mci_writel(host, UHS_REG, uhs); 1303 1304 return 0; 1305} 1306 1307static int dw_mci_get_ro(struct mmc_host *mmc) 1308{ 1309 int read_only; 1310 struct dw_mci_slot *slot = mmc_priv(mmc); 1311 int gpio_ro = mmc_gpio_get_ro(mmc); 1312 1313 /* Use platform get_ro function, else try on board write protect */ 1314 if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) || 1315 (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT)) 1316 read_only = 0; 1317 else if (!IS_ERR_VALUE(gpio_ro)) 1318 read_only = gpio_ro; 1319 else 1320 read_only = 1321 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1322 1323 dev_dbg(&mmc->class_dev, "card is %s\n", 1324 read_only ? "read-only" : "read-write"); 1325 1326 return read_only; 1327} 1328 1329static int dw_mci_get_cd(struct mmc_host *mmc) 1330{ 1331 int present; 1332 struct dw_mci_slot *slot = mmc_priv(mmc); 1333 struct dw_mci_board *brd = slot->host->pdata; 1334 struct dw_mci *host = slot->host; 1335 int gpio_cd = mmc_gpio_get_cd(mmc); 1336 1337 /* Use platform get_cd function, else try onboard card detect */ 1338 if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) || 1339 (mmc->caps & MMC_CAP_NONREMOVABLE)) 1340 present = 1; 1341 else if (!IS_ERR_VALUE(gpio_cd)) 1342 present = gpio_cd; 1343 else 1344 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 1345 == 0 ? 1 : 0; 1346 1347 spin_lock_bh(&host->lock); 1348 if (present) { 1349 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1350 dev_dbg(&mmc->class_dev, "card is present\n"); 1351 } else { 1352 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1353 dev_dbg(&mmc->class_dev, "card is not present\n"); 1354 } 1355 spin_unlock_bh(&host->lock); 1356 1357 return present; 1358} 1359 1360static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1361{ 1362 struct dw_mci_slot *slot = mmc_priv(mmc); 1363 struct dw_mci *host = slot->host; 1364 1365 /* 1366 * Low power mode will stop the card clock when idle. According to the 1367 * description of the CLKENA register we should disable low power mode 1368 * for SDIO cards if we need SDIO interrupts to work. 1369 */ 1370 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1371 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1372 u32 clk_en_a_old; 1373 u32 clk_en_a; 1374 1375 clk_en_a_old = mci_readl(host, CLKENA); 1376 1377 if (card->type == MMC_TYPE_SDIO || 1378 card->type == MMC_TYPE_SD_COMBO) { 1379 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1380 clk_en_a = clk_en_a_old & ~clken_low_pwr; 1381 } else { 1382 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1383 clk_en_a = clk_en_a_old | clken_low_pwr; 1384 } 1385 1386 if (clk_en_a != clk_en_a_old) { 1387 mci_writel(host, CLKENA, clk_en_a); 1388 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 1389 SDMMC_CMD_PRV_DAT_WAIT, 0); 1390 } 1391 } 1392} 1393 1394static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 1395{ 1396 struct dw_mci_slot *slot = mmc_priv(mmc); 1397 struct dw_mci *host = slot->host; 1398 unsigned long irqflags; 1399 u32 int_mask; 1400 1401 spin_lock_irqsave(&host->irq_lock, irqflags); 1402 1403 /* Enable/disable Slot Specific SDIO interrupt */ 1404 int_mask = mci_readl(host, INTMASK); 1405 if (enb) 1406 int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1407 else 1408 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1409 mci_writel(host, INTMASK, int_mask); 1410 1411 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1412} 1413 1414static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1415{ 1416 struct dw_mci_slot *slot = mmc_priv(mmc); 1417 struct dw_mci *host = slot->host; 1418 const struct dw_mci_drv_data *drv_data = host->drv_data; 1419 int err = -ENOSYS; 1420 1421 if (drv_data && drv_data->execute_tuning) 1422 err = drv_data->execute_tuning(slot); 1423 return err; 1424} 1425 1426static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1427{ 1428 struct dw_mci_slot *slot = mmc_priv(mmc); 1429 struct dw_mci *host = slot->host; 1430 const struct dw_mci_drv_data *drv_data = host->drv_data; 1431 1432 if (drv_data && drv_data->prepare_hs400_tuning) 1433 return drv_data->prepare_hs400_tuning(host, ios); 1434 1435 return 0; 1436} 1437 1438static const struct mmc_host_ops dw_mci_ops = { 1439 .request = dw_mci_request, 1440 .pre_req = dw_mci_pre_req, 1441 .post_req = dw_mci_post_req, 1442 .set_ios = dw_mci_set_ios, 1443 .get_ro = dw_mci_get_ro, 1444 .get_cd = dw_mci_get_cd, 1445 .enable_sdio_irq = dw_mci_enable_sdio_irq, 1446 .execute_tuning = dw_mci_execute_tuning, 1447 .card_busy = dw_mci_card_busy, 1448 .start_signal_voltage_switch = dw_mci_switch_voltage, 1449 .init_card = dw_mci_init_card, 1450 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1451}; 1452 1453static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1454 __releases(&host->lock) 1455 __acquires(&host->lock) 1456{ 1457 struct dw_mci_slot *slot; 1458 struct mmc_host *prev_mmc = host->cur_slot->mmc; 1459 1460 WARN_ON(host->cmd || host->data); 1461 1462 host->cur_slot->mrq = NULL; 1463 host->mrq = NULL; 1464 if (!list_empty(&host->queue)) { 1465 slot = list_entry(host->queue.next, 1466 struct dw_mci_slot, queue_node); 1467 list_del(&slot->queue_node); 1468 dev_vdbg(host->dev, "list not empty: %s is next\n", 1469 mmc_hostname(slot->mmc)); 1470 host->state = STATE_SENDING_CMD; 1471 dw_mci_start_request(host, slot); 1472 } else { 1473 dev_vdbg(host->dev, "list empty\n"); 1474 1475 if (host->state == STATE_SENDING_CMD11) 1476 host->state = STATE_WAITING_CMD11_DONE; 1477 else 1478 host->state = STATE_IDLE; 1479 } 1480 1481 spin_unlock(&host->lock); 1482 mmc_request_done(prev_mmc, mrq); 1483 spin_lock(&host->lock); 1484} 1485 1486static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1487{ 1488 u32 status = host->cmd_status; 1489 1490 host->cmd_status = 0; 1491 1492 /* Read the response from the card (up to 16 bytes) */ 1493 if (cmd->flags & MMC_RSP_PRESENT) { 1494 if (cmd->flags & MMC_RSP_136) { 1495 cmd->resp[3] = mci_readl(host, RESP0); 1496 cmd->resp[2] = mci_readl(host, RESP1); 1497 cmd->resp[1] = mci_readl(host, RESP2); 1498 cmd->resp[0] = mci_readl(host, RESP3); 1499 } else { 1500 cmd->resp[0] = mci_readl(host, RESP0); 1501 cmd->resp[1] = 0; 1502 cmd->resp[2] = 0; 1503 cmd->resp[3] = 0; 1504 } 1505 } 1506 1507 if (status & SDMMC_INT_RTO) 1508 cmd->error = -ETIMEDOUT; 1509 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1510 cmd->error = -EILSEQ; 1511 else if (status & SDMMC_INT_RESP_ERR) 1512 cmd->error = -EIO; 1513 else 1514 cmd->error = 0; 1515 1516 if (cmd->error) { 1517 /* newer ip versions need a delay between retries */ 1518 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) 1519 mdelay(20); 1520 } 1521 1522 return cmd->error; 1523} 1524 1525static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1526{ 1527 u32 status = host->data_status; 1528 1529 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1530 if (status & SDMMC_INT_DRTO) { 1531 data->error = -ETIMEDOUT; 1532 } else if (status & SDMMC_INT_DCRC) { 1533 data->error = -EILSEQ; 1534 } else if (status & SDMMC_INT_EBE) { 1535 if (host->dir_status == 1536 DW_MCI_SEND_STATUS) { 1537 /* 1538 * No data CRC status was returned. 1539 * The number of bytes transferred 1540 * will be exaggerated in PIO mode. 1541 */ 1542 data->bytes_xfered = 0; 1543 data->error = -ETIMEDOUT; 1544 } else if (host->dir_status == 1545 DW_MCI_RECV_STATUS) { 1546 data->error = -EIO; 1547 } 1548 } else { 1549 /* SDMMC_INT_SBE is included */ 1550 data->error = -EIO; 1551 } 1552 1553 dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1554 1555 /* 1556 * After an error, there may be data lingering 1557 * in the FIFO 1558 */ 1559 dw_mci_reset(host); 1560 } else { 1561 data->bytes_xfered = data->blocks * data->blksz; 1562 data->error = 0; 1563 } 1564 1565 return data->error; 1566} 1567 1568static void dw_mci_tasklet_func(unsigned long priv) 1569{ 1570 struct dw_mci *host = (struct dw_mci *)priv; 1571 struct mmc_data *data; 1572 struct mmc_command *cmd; 1573 struct mmc_request *mrq; 1574 enum dw_mci_state state; 1575 enum dw_mci_state prev_state; 1576 unsigned int err; 1577 1578 spin_lock(&host->lock); 1579 1580 state = host->state; 1581 data = host->data; 1582 mrq = host->mrq; 1583 1584 do { 1585 prev_state = state; 1586 1587 switch (state) { 1588 case STATE_IDLE: 1589 case STATE_WAITING_CMD11_DONE: 1590 break; 1591 1592 case STATE_SENDING_CMD11: 1593 case STATE_SENDING_CMD: 1594 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1595 &host->pending_events)) 1596 break; 1597 1598 cmd = host->cmd; 1599 host->cmd = NULL; 1600 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1601 err = dw_mci_command_complete(host, cmd); 1602 if (cmd == mrq->sbc && !err) { 1603 prev_state = state = STATE_SENDING_CMD; 1604 __dw_mci_start_request(host, host->cur_slot, 1605 mrq->cmd); 1606 goto unlock; 1607 } 1608 1609 if (cmd->data && err) { 1610 dw_mci_stop_dma(host); 1611 send_stop_abort(host, data); 1612 state = STATE_SENDING_STOP; 1613 break; 1614 } 1615 1616 if (!cmd->data || err) { 1617 dw_mci_request_end(host, mrq); 1618 goto unlock; 1619 } 1620 1621 prev_state = state = STATE_SENDING_DATA; 1622 /* fall through */ 1623 1624 case STATE_SENDING_DATA: 1625 /* 1626 * We could get a data error and never a transfer 1627 * complete so we'd better check for it here. 1628 * 1629 * Note that we don't really care if we also got a 1630 * transfer complete; stopping the DMA and sending an 1631 * abort won't hurt. 1632 */ 1633 if (test_and_clear_bit(EVENT_DATA_ERROR, 1634 &host->pending_events)) { 1635 dw_mci_stop_dma(host); 1636 if (data->stop || 1637 !(host->data_status & (SDMMC_INT_DRTO | 1638 SDMMC_INT_EBE))) 1639 send_stop_abort(host, data); 1640 state = STATE_DATA_ERROR; 1641 break; 1642 } 1643 1644 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1645 &host->pending_events)) 1646 break; 1647 1648 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 1649 1650 /* 1651 * Handle an EVENT_DATA_ERROR that might have shown up 1652 * before the transfer completed. This might not have 1653 * been caught by the check above because the interrupt 1654 * could have gone off between the previous check and 1655 * the check for transfer complete. 1656 * 1657 * Technically this ought not be needed assuming we 1658 * get a DATA_COMPLETE eventually (we'll notice the 1659 * error and end the request), but it shouldn't hurt. 1660 * 1661 * This has the advantage of sending the stop command. 1662 */ 1663 if (test_and_clear_bit(EVENT_DATA_ERROR, 1664 &host->pending_events)) { 1665 dw_mci_stop_dma(host); 1666 if (data->stop || 1667 !(host->data_status & (SDMMC_INT_DRTO | 1668 SDMMC_INT_EBE))) 1669 send_stop_abort(host, data); 1670 state = STATE_DATA_ERROR; 1671 break; 1672 } 1673 prev_state = state = STATE_DATA_BUSY; 1674 1675 /* fall through */ 1676 1677 case STATE_DATA_BUSY: 1678 if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 1679 &host->pending_events)) 1680 break; 1681 1682 host->data = NULL; 1683 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1684 err = dw_mci_data_complete(host, data); 1685 1686 if (!err) { 1687 if (!data->stop || mrq->sbc) { 1688 if (mrq->sbc && data->stop) 1689 data->stop->error = 0; 1690 dw_mci_request_end(host, mrq); 1691 goto unlock; 1692 } 1693 1694 /* stop command for open-ended transfer*/ 1695 if (data->stop) 1696 send_stop_abort(host, data); 1697 } else { 1698 /* 1699 * If we don't have a command complete now we'll 1700 * never get one since we just reset everything; 1701 * better end the request. 1702 * 1703 * If we do have a command complete we'll fall 1704 * through to the SENDING_STOP command and 1705 * everything will be peachy keen. 1706 */ 1707 if (!test_bit(EVENT_CMD_COMPLETE, 1708 &host->pending_events)) { 1709 host->cmd = NULL; 1710 dw_mci_request_end(host, mrq); 1711 goto unlock; 1712 } 1713 } 1714 1715 /* 1716 * If err has non-zero, 1717 * stop-abort command has been already issued. 1718 */ 1719 prev_state = state = STATE_SENDING_STOP; 1720 1721 /* fall through */ 1722 1723 case STATE_SENDING_STOP: 1724 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1725 &host->pending_events)) 1726 break; 1727 1728 /* CMD error in data command */ 1729 if (mrq->cmd->error && mrq->data) 1730 dw_mci_reset(host); 1731 1732 host->cmd = NULL; 1733 host->data = NULL; 1734 1735 if (mrq->stop) 1736 dw_mci_command_complete(host, mrq->stop); 1737 else 1738 host->cmd_status = 0; 1739 1740 dw_mci_request_end(host, mrq); 1741 goto unlock; 1742 1743 case STATE_DATA_ERROR: 1744 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1745 &host->pending_events)) 1746 break; 1747 1748 state = STATE_DATA_BUSY; 1749 break; 1750 } 1751 } while (state != prev_state); 1752 1753 host->state = state; 1754unlock: 1755 spin_unlock(&host->lock); 1756 1757} 1758 1759/* push final bytes to part_buf, only use during push */ 1760static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 1761{ 1762 memcpy((void *)&host->part_buf, buf, cnt); 1763 host->part_buf_count = cnt; 1764} 1765 1766/* append bytes to part_buf, only use during push */ 1767static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 1768{ 1769 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 1770 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 1771 host->part_buf_count += cnt; 1772 return cnt; 1773} 1774 1775/* pull first bytes from part_buf, only use during pull */ 1776static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 1777{ 1778 cnt = min(cnt, (int)host->part_buf_count); 1779 if (cnt) { 1780 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 1781 cnt); 1782 host->part_buf_count -= cnt; 1783 host->part_buf_start += cnt; 1784 } 1785 return cnt; 1786} 1787 1788/* pull final bytes from the part_buf, assuming it's just been filled */ 1789static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 1790{ 1791 memcpy(buf, &host->part_buf, cnt); 1792 host->part_buf_start = cnt; 1793 host->part_buf_count = (1 << host->data_shift) - cnt; 1794} 1795 1796static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 1797{ 1798 struct mmc_data *data = host->data; 1799 int init_cnt = cnt; 1800 1801 /* try and push anything in the part_buf */ 1802 if (unlikely(host->part_buf_count)) { 1803 int len = dw_mci_push_part_bytes(host, buf, cnt); 1804 buf += len; 1805 cnt -= len; 1806 if (host->part_buf_count == 2) { 1807 mci_fifo_writew(host->fifo_reg, host->part_buf16); 1808 host->part_buf_count = 0; 1809 } 1810 } 1811#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1812 if (unlikely((unsigned long)buf & 0x1)) { 1813 while (cnt >= 2) { 1814 u16 aligned_buf[64]; 1815 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 1816 int items = len >> 1; 1817 int i; 1818 /* memcpy from input buffer into aligned buffer */ 1819 memcpy(aligned_buf, buf, len); 1820 buf += len; 1821 cnt -= len; 1822 /* push data from aligned buffer into fifo */ 1823 for (i = 0; i < items; ++i) 1824 mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 1825 } 1826 } else 1827#endif 1828 { 1829 u16 *pdata = buf; 1830 for (; cnt >= 2; cnt -= 2) 1831 mci_fifo_writew(host->fifo_reg, *pdata++); 1832 buf = pdata; 1833 } 1834 /* put anything remaining in the part_buf */ 1835 if (cnt) { 1836 dw_mci_set_part_bytes(host, buf, cnt); 1837 /* Push data if we have reached the expected data length */ 1838 if ((data->bytes_xfered + init_cnt) == 1839 (data->blksz * data->blocks)) 1840 mci_fifo_writew(host->fifo_reg, host->part_buf16); 1841 } 1842} 1843 1844static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 1845{ 1846#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1847 if (unlikely((unsigned long)buf & 0x1)) { 1848 while (cnt >= 2) { 1849 /* pull data from fifo into aligned buffer */ 1850 u16 aligned_buf[64]; 1851 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 1852 int items = len >> 1; 1853 int i; 1854 for (i = 0; i < items; ++i) 1855 aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 1856 /* memcpy from aligned buffer into output buffer */ 1857 memcpy(buf, aligned_buf, len); 1858 buf += len; 1859 cnt -= len; 1860 } 1861 } else 1862#endif 1863 { 1864 u16 *pdata = buf; 1865 for (; cnt >= 2; cnt -= 2) 1866 *pdata++ = mci_fifo_readw(host->fifo_reg); 1867 buf = pdata; 1868 } 1869 if (cnt) { 1870 host->part_buf16 = mci_fifo_readw(host->fifo_reg); 1871 dw_mci_pull_final_bytes(host, buf, cnt); 1872 } 1873} 1874 1875static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 1876{ 1877 struct mmc_data *data = host->data; 1878 int init_cnt = cnt; 1879 1880 /* try and push anything in the part_buf */ 1881 if (unlikely(host->part_buf_count)) { 1882 int len = dw_mci_push_part_bytes(host, buf, cnt); 1883 buf += len; 1884 cnt -= len; 1885 if (host->part_buf_count == 4) { 1886 mci_fifo_writel(host->fifo_reg, host->part_buf32); 1887 host->part_buf_count = 0; 1888 } 1889 } 1890#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1891 if (unlikely((unsigned long)buf & 0x3)) { 1892 while (cnt >= 4) { 1893 u32 aligned_buf[32]; 1894 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 1895 int items = len >> 2; 1896 int i; 1897 /* memcpy from input buffer into aligned buffer */ 1898 memcpy(aligned_buf, buf, len); 1899 buf += len; 1900 cnt -= len; 1901 /* push data from aligned buffer into fifo */ 1902 for (i = 0; i < items; ++i) 1903 mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 1904 } 1905 } else 1906#endif 1907 { 1908 u32 *pdata = buf; 1909 for (; cnt >= 4; cnt -= 4) 1910 mci_fifo_writel(host->fifo_reg, *pdata++); 1911 buf = pdata; 1912 } 1913 /* put anything remaining in the part_buf */ 1914 if (cnt) { 1915 dw_mci_set_part_bytes(host, buf, cnt); 1916 /* Push data if we have reached the expected data length */ 1917 if ((data->bytes_xfered + init_cnt) == 1918 (data->blksz * data->blocks)) 1919 mci_fifo_writel(host->fifo_reg, host->part_buf32); 1920 } 1921} 1922 1923static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 1924{ 1925#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1926 if (unlikely((unsigned long)buf & 0x3)) { 1927 while (cnt >= 4) { 1928 /* pull data from fifo into aligned buffer */ 1929 u32 aligned_buf[32]; 1930 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 1931 int items = len >> 2; 1932 int i; 1933 for (i = 0; i < items; ++i) 1934 aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 1935 /* memcpy from aligned buffer into output buffer */ 1936 memcpy(buf, aligned_buf, len); 1937 buf += len; 1938 cnt -= len; 1939 } 1940 } else 1941#endif 1942 { 1943 u32 *pdata = buf; 1944 for (; cnt >= 4; cnt -= 4) 1945 *pdata++ = mci_fifo_readl(host->fifo_reg); 1946 buf = pdata; 1947 } 1948 if (cnt) { 1949 host->part_buf32 = mci_fifo_readl(host->fifo_reg); 1950 dw_mci_pull_final_bytes(host, buf, cnt); 1951 } 1952} 1953 1954static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 1955{ 1956 struct mmc_data *data = host->data; 1957 int init_cnt = cnt; 1958 1959 /* try and push anything in the part_buf */ 1960 if (unlikely(host->part_buf_count)) { 1961 int len = dw_mci_push_part_bytes(host, buf, cnt); 1962 buf += len; 1963 cnt -= len; 1964 1965 if (host->part_buf_count == 8) { 1966 mci_fifo_writeq(host->fifo_reg, host->part_buf); 1967 host->part_buf_count = 0; 1968 } 1969 } 1970#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1971 if (unlikely((unsigned long)buf & 0x7)) { 1972 while (cnt >= 8) { 1973 u64 aligned_buf[16]; 1974 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 1975 int items = len >> 3; 1976 int i; 1977 /* memcpy from input buffer into aligned buffer */ 1978 memcpy(aligned_buf, buf, len); 1979 buf += len; 1980 cnt -= len; 1981 /* push data from aligned buffer into fifo */ 1982 for (i = 0; i < items; ++i) 1983 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 1984 } 1985 } else 1986#endif 1987 { 1988 u64 *pdata = buf; 1989 for (; cnt >= 8; cnt -= 8) 1990 mci_fifo_writeq(host->fifo_reg, *pdata++); 1991 buf = pdata; 1992 } 1993 /* put anything remaining in the part_buf */ 1994 if (cnt) { 1995 dw_mci_set_part_bytes(host, buf, cnt); 1996 /* Push data if we have reached the expected data length */ 1997 if ((data->bytes_xfered + init_cnt) == 1998 (data->blksz * data->blocks)) 1999 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2000 } 2001} 2002 2003static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2004{ 2005#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2006 if (unlikely((unsigned long)buf & 0x7)) { 2007 while (cnt >= 8) { 2008 /* pull data from fifo into aligned buffer */ 2009 u64 aligned_buf[16]; 2010 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2011 int items = len >> 3; 2012 int i; 2013 for (i = 0; i < items; ++i) 2014 aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 2015 2016 /* memcpy from aligned buffer into output buffer */ 2017 memcpy(buf, aligned_buf, len); 2018 buf += len; 2019 cnt -= len; 2020 } 2021 } else 2022#endif 2023 { 2024 u64 *pdata = buf; 2025 for (; cnt >= 8; cnt -= 8) 2026 *pdata++ = mci_fifo_readq(host->fifo_reg); 2027 buf = pdata; 2028 } 2029 if (cnt) { 2030 host->part_buf = mci_fifo_readq(host->fifo_reg); 2031 dw_mci_pull_final_bytes(host, buf, cnt); 2032 } 2033} 2034 2035static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 2036{ 2037 int len; 2038 2039 /* get remaining partial bytes */ 2040 len = dw_mci_pull_part_bytes(host, buf, cnt); 2041 if (unlikely(len == cnt)) 2042 return; 2043 buf += len; 2044 cnt -= len; 2045 2046 /* get the rest of the data */ 2047 host->pull_data(host, buf, cnt); 2048} 2049 2050static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2051{ 2052 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2053 void *buf; 2054 unsigned int offset; 2055 struct mmc_data *data = host->data; 2056 int shift = host->data_shift; 2057 u32 status; 2058 unsigned int len; 2059 unsigned int remain, fcnt; 2060 2061 do { 2062 if (!sg_miter_next(sg_miter)) 2063 goto done; 2064 2065 host->sg = sg_miter->piter.sg; 2066 buf = sg_miter->addr; 2067 remain = sg_miter->length; 2068 offset = 0; 2069 2070 do { 2071 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2072 << shift) + host->part_buf_count; 2073 len = min(remain, fcnt); 2074 if (!len) 2075 break; 2076 dw_mci_pull_data(host, (void *)(buf + offset), len); 2077 data->bytes_xfered += len; 2078 offset += len; 2079 remain -= len; 2080 } while (remain); 2081 2082 sg_miter->consumed = offset; 2083 status = mci_readl(host, MINTSTS); 2084 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2085 /* if the RXDR is ready read again */ 2086 } while ((status & SDMMC_INT_RXDR) || 2087 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2088 2089 if (!remain) { 2090 if (!sg_miter_next(sg_miter)) 2091 goto done; 2092 sg_miter->consumed = 0; 2093 } 2094 sg_miter_stop(sg_miter); 2095 return; 2096 2097done: 2098 sg_miter_stop(sg_miter); 2099 host->sg = NULL; 2100 smp_wmb(); 2101 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2102} 2103 2104static void dw_mci_write_data_pio(struct dw_mci *host) 2105{ 2106 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2107 void *buf; 2108 unsigned int offset; 2109 struct mmc_data *data = host->data; 2110 int shift = host->data_shift; 2111 u32 status; 2112 unsigned int len; 2113 unsigned int fifo_depth = host->fifo_depth; 2114 unsigned int remain, fcnt; 2115 2116 do { 2117 if (!sg_miter_next(sg_miter)) 2118 goto done; 2119 2120 host->sg = sg_miter->piter.sg; 2121 buf = sg_miter->addr; 2122 remain = sg_miter->length; 2123 offset = 0; 2124 2125 do { 2126 fcnt = ((fifo_depth - 2127 SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2128 << shift) - host->part_buf_count; 2129 len = min(remain, fcnt); 2130 if (!len) 2131 break; 2132 host->push_data(host, (void *)(buf + offset), len); 2133 data->bytes_xfered += len; 2134 offset += len; 2135 remain -= len; 2136 } while (remain); 2137 2138 sg_miter->consumed = offset; 2139 status = mci_readl(host, MINTSTS); 2140 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2141 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2142 2143 if (!remain) { 2144 if (!sg_miter_next(sg_miter)) 2145 goto done; 2146 sg_miter->consumed = 0; 2147 } 2148 sg_miter_stop(sg_miter); 2149 return; 2150 2151done: 2152 sg_miter_stop(sg_miter); 2153 host->sg = NULL; 2154 smp_wmb(); 2155 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2156} 2157 2158static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2159{ 2160 if (!host->cmd_status) 2161 host->cmd_status = status; 2162 2163 smp_wmb(); 2164 2165 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2166 tasklet_schedule(&host->tasklet); 2167} 2168 2169static void dw_mci_handle_cd(struct dw_mci *host) 2170{ 2171 int i; 2172 2173 for (i = 0; i < host->num_slots; i++) { 2174 struct dw_mci_slot *slot = host->slot[i]; 2175 2176 if (!slot) 2177 continue; 2178 2179 if (slot->mmc->ops->card_event) 2180 slot->mmc->ops->card_event(slot->mmc); 2181 mmc_detect_change(slot->mmc, 2182 msecs_to_jiffies(host->pdata->detect_delay_ms)); 2183 } 2184} 2185 2186static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2187{ 2188 struct dw_mci *host = dev_id; 2189 u32 pending; 2190 int i; 2191 2192 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2193 2194 /* 2195 * DTO fix - version 2.10a and below, and only if internal DMA 2196 * is configured. 2197 */ 2198 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { 2199 if (!pending && 2200 ((mci_readl(host, STATUS) >> 17) & 0x1fff)) 2201 pending |= SDMMC_INT_DATA_OVER; 2202 } 2203 2204 if (pending) { 2205 /* Check volt switch first, since it can look like an error */ 2206 if ((host->state == STATE_SENDING_CMD11) && 2207 (pending & SDMMC_INT_VOLT_SWITCH)) { 2208 unsigned long irqflags; 2209 2210 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 2211 pending &= ~SDMMC_INT_VOLT_SWITCH; 2212 2213 /* 2214 * Hold the lock; we know cmd11_timer can't be kicked 2215 * off after the lock is released, so safe to delete. 2216 */ 2217 spin_lock_irqsave(&host->irq_lock, irqflags); 2218 dw_mci_cmd_interrupt(host, pending); 2219 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2220 2221 del_timer(&host->cmd11_timer); 2222 } 2223 2224 if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2225 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2226 host->cmd_status = pending; 2227 smp_wmb(); 2228 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2229 } 2230 2231 if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2232 /* if there is an error report DATA_ERROR */ 2233 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2234 host->data_status = pending; 2235 smp_wmb(); 2236 set_bit(EVENT_DATA_ERROR, &host->pending_events); 2237 tasklet_schedule(&host->tasklet); 2238 } 2239 2240 if (pending & SDMMC_INT_DATA_OVER) { 2241 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2242 if (!host->data_status) 2243 host->data_status = pending; 2244 smp_wmb(); 2245 if (host->dir_status == DW_MCI_RECV_STATUS) { 2246 if (host->sg != NULL) 2247 dw_mci_read_data_pio(host, true); 2248 } 2249 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2250 tasklet_schedule(&host->tasklet); 2251 } 2252 2253 if (pending & SDMMC_INT_RXDR) { 2254 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2255 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 2256 dw_mci_read_data_pio(host, false); 2257 } 2258 2259 if (pending & SDMMC_INT_TXDR) { 2260 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2261 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2262 dw_mci_write_data_pio(host); 2263 } 2264 2265 if (pending & SDMMC_INT_CMD_DONE) { 2266 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2267 dw_mci_cmd_interrupt(host, pending); 2268 } 2269 2270 if (pending & SDMMC_INT_CD) { 2271 mci_writel(host, RINTSTS, SDMMC_INT_CD); 2272 dw_mci_handle_cd(host); 2273 } 2274 2275 /* Handle SDIO Interrupts */ 2276 for (i = 0; i < host->num_slots; i++) { 2277 struct dw_mci_slot *slot = host->slot[i]; 2278 2279 if (!slot) 2280 continue; 2281 2282 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 2283 mci_writel(host, RINTSTS, 2284 SDMMC_INT_SDIO(slot->sdio_id)); 2285 mmc_signal_sdio_irq(slot->mmc); 2286 } 2287 } 2288 2289 } 2290 2291#ifdef CONFIG_MMC_DW_IDMAC 2292 /* Handle DMA interrupts */ 2293 if (host->dma_64bit_address == 1) { 2294 pending = mci_readl(host, IDSTS64); 2295 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2296 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 2297 SDMMC_IDMAC_INT_RI); 2298 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2299 host->dma_ops->complete(host); 2300 } 2301 } else { 2302 pending = mci_readl(host, IDSTS); 2303 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2304 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 2305 SDMMC_IDMAC_INT_RI); 2306 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2307 host->dma_ops->complete(host); 2308 } 2309 } 2310#endif 2311 2312 return IRQ_HANDLED; 2313} 2314 2315#ifdef CONFIG_OF 2316/* given a slot id, find out the device node representing that slot */ 2317static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) 2318{ 2319 struct device_node *np; 2320 const __be32 *addr; 2321 int len; 2322 2323 if (!dev || !dev->of_node) 2324 return NULL; 2325 2326 for_each_child_of_node(dev->of_node, np) { 2327 addr = of_get_property(np, "reg", &len); 2328 if (!addr || (len < sizeof(int))) 2329 continue; 2330 if (be32_to_cpup(addr) == slot) 2331 return np; 2332 } 2333 return NULL; 2334} 2335 2336static struct dw_mci_of_slot_quirks { 2337 char *quirk; 2338 int id; 2339} of_slot_quirks[] = { 2340 { 2341 .quirk = "disable-wp", 2342 .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT, 2343 }, 2344}; 2345 2346static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) 2347{ 2348 struct device_node *np = dw_mci_of_find_slot_node(dev, slot); 2349 int quirks = 0; 2350 int idx; 2351 2352 /* get quirks */ 2353 for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++) 2354 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) { 2355 dev_warn(dev, "Slot quirk %s is deprecated\n", 2356 of_slot_quirks[idx].quirk); 2357 quirks |= of_slot_quirks[idx].id; 2358 } 2359 2360 return quirks; 2361} 2362#else /* CONFIG_OF */ 2363static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) 2364{ 2365 return 0; 2366} 2367#endif /* CONFIG_OF */ 2368 2369static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2370{ 2371 struct mmc_host *mmc; 2372 struct dw_mci_slot *slot; 2373 const struct dw_mci_drv_data *drv_data = host->drv_data; 2374 int ctrl_id, ret; 2375 u32 freq[2]; 2376 2377 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2378 if (!mmc) 2379 return -ENOMEM; 2380 2381 slot = mmc_priv(mmc); 2382 slot->id = id; 2383 slot->sdio_id = host->sdio_id0 + id; 2384 slot->mmc = mmc; 2385 slot->host = host; 2386 host->slot[id] = slot; 2387 2388 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id); 2389 2390 mmc->ops = &dw_mci_ops; 2391 if (of_property_read_u32_array(host->dev->of_node, 2392 "clock-freq-min-max", freq, 2)) { 2393 mmc->f_min = DW_MCI_FREQ_MIN; 2394 mmc->f_max = DW_MCI_FREQ_MAX; 2395 } else { 2396 mmc->f_min = freq[0]; 2397 mmc->f_max = freq[1]; 2398 } 2399 2400 /*if there are external regulators, get them*/ 2401 ret = mmc_regulator_get_supply(mmc); 2402 if (ret == -EPROBE_DEFER) 2403 goto err_host_allocated; 2404 2405 if (!mmc->ocr_avail) 2406 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2407 2408 if (host->pdata->caps) 2409 mmc->caps = host->pdata->caps; 2410 2411 if (host->pdata->pm_caps) 2412 mmc->pm_caps = host->pdata->pm_caps; 2413 2414 if (host->dev->of_node) { 2415 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2416 if (ctrl_id < 0) 2417 ctrl_id = 0; 2418 } else { 2419 ctrl_id = to_platform_device(host->dev)->id; 2420 } 2421 if (drv_data && drv_data->caps) 2422 mmc->caps |= drv_data->caps[ctrl_id]; 2423 2424 if (host->pdata->caps2) 2425 mmc->caps2 = host->pdata->caps2; 2426 2427 ret = mmc_of_parse(mmc); 2428 if (ret) 2429 goto err_host_allocated; 2430 2431 if (host->pdata->blk_settings) { 2432 mmc->max_segs = host->pdata->blk_settings->max_segs; 2433 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size; 2434 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count; 2435 mmc->max_req_size = host->pdata->blk_settings->max_req_size; 2436 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size; 2437 } else { 2438 /* Useful defaults if platform data is unset. */ 2439#ifdef CONFIG_MMC_DW_IDMAC 2440 mmc->max_segs = host->ring_size; 2441 mmc->max_blk_size = 65536; 2442 mmc->max_seg_size = DW_MCI_DESC_DATA_LENGTH; 2443 mmc->max_req_size = mmc->max_seg_size * host->ring_size; 2444 mmc->max_blk_count = mmc->max_req_size / 512; 2445#else 2446 mmc->max_segs = 64; 2447 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ 2448 mmc->max_blk_count = 512; 2449 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2450 mmc->max_seg_size = mmc->max_req_size; 2451#endif /* CONFIG_MMC_DW_IDMAC */ 2452 } 2453 2454 if (dw_mci_get_cd(mmc)) 2455 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2456 else 2457 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2458 2459 ret = mmc_add_host(mmc); 2460 if (ret) 2461 goto err_host_allocated; 2462 2463#if defined(CONFIG_DEBUG_FS) 2464 dw_mci_init_debugfs(slot); 2465#endif 2466 2467 return 0; 2468 2469err_host_allocated: 2470 mmc_free_host(mmc); 2471 return ret; 2472} 2473 2474static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2475{ 2476 /* Debugfs stuff is cleaned up by mmc core */ 2477 mmc_remove_host(slot->mmc); 2478 slot->host->slot[id] = NULL; 2479 mmc_free_host(slot->mmc); 2480} 2481 2482static void dw_mci_init_dma(struct dw_mci *host) 2483{ 2484 int addr_config; 2485 /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */ 2486 addr_config = (mci_readl(host, HCON) >> 27) & 0x01; 2487 2488 if (addr_config == 1) { 2489 /* host supports IDMAC in 64-bit address mode */ 2490 host->dma_64bit_address = 1; 2491 dev_info(host->dev, "IDMAC supports 64-bit address mode.\n"); 2492 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 2493 dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64)); 2494 } else { 2495 /* host supports IDMAC in 32-bit address mode */ 2496 host->dma_64bit_address = 0; 2497 dev_info(host->dev, "IDMAC supports 32-bit address mode.\n"); 2498 } 2499 2500 /* Alloc memory for sg translation */ 2501 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, 2502 &host->sg_dma, GFP_KERNEL); 2503 if (!host->sg_cpu) { 2504 dev_err(host->dev, "%s: could not alloc DMA memory\n", 2505 __func__); 2506 goto no_dma; 2507 } 2508 2509 /* Determine which DMA interface to use */ 2510#ifdef CONFIG_MMC_DW_IDMAC 2511 host->dma_ops = &dw_mci_idmac_ops; 2512 dev_info(host->dev, "Using internal DMA controller.\n"); 2513#endif 2514 2515 if (!host->dma_ops) 2516 goto no_dma; 2517 2518 if (host->dma_ops->init && host->dma_ops->start && 2519 host->dma_ops->stop && host->dma_ops->cleanup) { 2520 if (host->dma_ops->init(host)) { 2521 dev_err(host->dev, "%s: Unable to initialize " 2522 "DMA Controller.\n", __func__); 2523 goto no_dma; 2524 } 2525 } else { 2526 dev_err(host->dev, "DMA initialization not found.\n"); 2527 goto no_dma; 2528 } 2529 2530 host->use_dma = 1; 2531 return; 2532 2533no_dma: 2534 dev_info(host->dev, "Using PIO mode.\n"); 2535 host->use_dma = 0; 2536 return; 2537} 2538 2539static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2540{ 2541 unsigned long timeout = jiffies + msecs_to_jiffies(500); 2542 u32 ctrl; 2543 2544 ctrl = mci_readl(host, CTRL); 2545 ctrl |= reset; 2546 mci_writel(host, CTRL, ctrl); 2547 2548 /* wait till resets clear */ 2549 do { 2550 ctrl = mci_readl(host, CTRL); 2551 if (!(ctrl & reset)) 2552 return true; 2553 } while (time_before(jiffies, timeout)); 2554 2555 dev_err(host->dev, 2556 "Timeout resetting block (ctrl reset %#x)\n", 2557 ctrl & reset); 2558 2559 return false; 2560} 2561 2562static bool dw_mci_reset(struct dw_mci *host) 2563{ 2564 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 2565 bool ret = false; 2566 2567 /* 2568 * Reseting generates a block interrupt, hence setting 2569 * the scatter-gather pointer to NULL. 2570 */ 2571 if (host->sg) { 2572 sg_miter_stop(&host->sg_miter); 2573 host->sg = NULL; 2574 } 2575 2576 if (host->use_dma) 2577 flags |= SDMMC_CTRL_DMA_RESET; 2578 2579 if (dw_mci_ctrl_reset(host, flags)) { 2580 /* 2581 * In all cases we clear the RAWINTS register to clear any 2582 * interrupts. 2583 */ 2584 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2585 2586 /* if using dma we wait for dma_req to clear */ 2587 if (host->use_dma) { 2588 unsigned long timeout = jiffies + msecs_to_jiffies(500); 2589 u32 status; 2590 do { 2591 status = mci_readl(host, STATUS); 2592 if (!(status & SDMMC_STATUS_DMA_REQ)) 2593 break; 2594 cpu_relax(); 2595 } while (time_before(jiffies, timeout)); 2596 2597 if (status & SDMMC_STATUS_DMA_REQ) { 2598 dev_err(host->dev, 2599 "%s: Timeout waiting for dma_req to " 2600 "clear during reset\n", __func__); 2601 goto ciu_out; 2602 } 2603 2604 /* when using DMA next we reset the fifo again */ 2605 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 2606 goto ciu_out; 2607 } 2608 } else { 2609 /* if the controller reset bit did clear, then set clock regs */ 2610 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 2611 dev_err(host->dev, "%s: fifo/dma reset bits didn't " 2612 "clear but ciu was reset, doing clock update\n", 2613 __func__); 2614 goto ciu_out; 2615 } 2616 } 2617 2618#if IS_ENABLED(CONFIG_MMC_DW_IDMAC) 2619 /* It is also recommended that we reset and reprogram idmac */ 2620 dw_mci_idmac_reset(host); 2621#endif 2622 2623 ret = true; 2624 2625ciu_out: 2626 /* After a CTRL reset we need to have CIU set clock registers */ 2627 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 2628 2629 return ret; 2630} 2631 2632static void dw_mci_cmd11_timer(unsigned long arg) 2633{ 2634 struct dw_mci *host = (struct dw_mci *)arg; 2635 2636 if (host->state != STATE_SENDING_CMD11) { 2637 dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 2638 return; 2639 } 2640 2641 host->cmd_status = SDMMC_INT_RTO; 2642 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2643 tasklet_schedule(&host->tasklet); 2644} 2645 2646#ifdef CONFIG_OF 2647static struct dw_mci_of_quirks { 2648 char *quirk; 2649 int id; 2650} of_quirks[] = { 2651 { 2652 .quirk = "broken-cd", 2653 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, 2654 }, { 2655 .quirk = "disable-wp", 2656 .id = DW_MCI_QUIRK_NO_WRITE_PROTECT, 2657 }, 2658}; 2659 2660static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2661{ 2662 struct dw_mci_board *pdata; 2663 struct device *dev = host->dev; 2664 struct device_node *np = dev->of_node; 2665 const struct dw_mci_drv_data *drv_data = host->drv_data; 2666 int idx, ret; 2667 u32 clock_frequency; 2668 2669 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2670 if (!pdata) 2671 return ERR_PTR(-ENOMEM); 2672 2673 /* find out number of slots supported */ 2674 if (of_property_read_u32(dev->of_node, "num-slots", 2675 &pdata->num_slots)) { 2676 dev_info(dev, "num-slots property not found, " 2677 "assuming 1 slot is available\n"); 2678 pdata->num_slots = 1; 2679 } 2680 2681 /* get quirks */ 2682 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++) 2683 if (of_get_property(np, of_quirks[idx].quirk, NULL)) 2684 pdata->quirks |= of_quirks[idx].id; 2685 2686 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 2687 dev_info(dev, "fifo-depth property not found, using " 2688 "value of FIFOTH register as default\n"); 2689 2690 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2691 2692 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 2693 pdata->bus_hz = clock_frequency; 2694 2695 if (drv_data && drv_data->parse_dt) { 2696 ret = drv_data->parse_dt(host); 2697 if (ret) 2698 return ERR_PTR(ret); 2699 } 2700 2701 if (of_find_property(np, "supports-highspeed", NULL)) 2702 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 2703 2704 return pdata; 2705} 2706 2707#else /* CONFIG_OF */ 2708static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2709{ 2710 return ERR_PTR(-EINVAL); 2711} 2712#endif /* CONFIG_OF */ 2713 2714static void dw_mci_enable_cd(struct dw_mci *host) 2715{ 2716 struct dw_mci_board *brd = host->pdata; 2717 unsigned long irqflags; 2718 u32 temp; 2719 int i; 2720 2721 /* No need for CD if broken card detection */ 2722 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 2723 return; 2724 2725 /* No need for CD if all slots have a non-error GPIO */ 2726 for (i = 0; i < host->num_slots; i++) { 2727 struct dw_mci_slot *slot = host->slot[i]; 2728 2729 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc))) 2730 break; 2731 } 2732 if (i == host->num_slots) 2733 return; 2734 2735 spin_lock_irqsave(&host->irq_lock, irqflags); 2736 temp = mci_readl(host, INTMASK); 2737 temp |= SDMMC_INT_CD; 2738 mci_writel(host, INTMASK, temp); 2739 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2740} 2741 2742int dw_mci_probe(struct dw_mci *host) 2743{ 2744 const struct dw_mci_drv_data *drv_data = host->drv_data; 2745 int width, i, ret = 0; 2746 u32 fifo_size; 2747 int init_slots = 0; 2748 2749 if (!host->pdata) { 2750 host->pdata = dw_mci_parse_dt(host); 2751 if (IS_ERR(host->pdata)) { 2752 dev_err(host->dev, "platform data not available\n"); 2753 return -EINVAL; 2754 } 2755 } 2756 2757 if (host->pdata->num_slots > 1) { 2758 dev_err(host->dev, 2759 "Platform data must supply num_slots.\n"); 2760 return -ENODEV; 2761 } 2762 2763 host->biu_clk = devm_clk_get(host->dev, "biu"); 2764 if (IS_ERR(host->biu_clk)) { 2765 dev_dbg(host->dev, "biu clock not available\n"); 2766 } else { 2767 ret = clk_prepare_enable(host->biu_clk); 2768 if (ret) { 2769 dev_err(host->dev, "failed to enable biu clock\n"); 2770 return ret; 2771 } 2772 } 2773 2774 host->ciu_clk = devm_clk_get(host->dev, "ciu"); 2775 if (IS_ERR(host->ciu_clk)) { 2776 dev_dbg(host->dev, "ciu clock not available\n"); 2777 host->bus_hz = host->pdata->bus_hz; 2778 } else { 2779 ret = clk_prepare_enable(host->ciu_clk); 2780 if (ret) { 2781 dev_err(host->dev, "failed to enable ciu clock\n"); 2782 goto err_clk_biu; 2783 } 2784 2785 if (host->pdata->bus_hz) { 2786 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 2787 if (ret) 2788 dev_warn(host->dev, 2789 "Unable to set bus rate to %uHz\n", 2790 host->pdata->bus_hz); 2791 } 2792 host->bus_hz = clk_get_rate(host->ciu_clk); 2793 } 2794 2795 if (!host->bus_hz) { 2796 dev_err(host->dev, 2797 "Platform data must supply bus speed\n"); 2798 ret = -ENODEV; 2799 goto err_clk_ciu; 2800 } 2801 2802 if (drv_data && drv_data->init) { 2803 ret = drv_data->init(host); 2804 if (ret) { 2805 dev_err(host->dev, 2806 "implementation specific init failed\n"); 2807 goto err_clk_ciu; 2808 } 2809 } 2810 2811 if (drv_data && drv_data->setup_clock) { 2812 ret = drv_data->setup_clock(host); 2813 if (ret) { 2814 dev_err(host->dev, 2815 "implementation specific clock setup failed\n"); 2816 goto err_clk_ciu; 2817 } 2818 } 2819 2820 setup_timer(&host->cmd11_timer, 2821 dw_mci_cmd11_timer, (unsigned long)host); 2822 2823 host->quirks = host->pdata->quirks; 2824 2825 spin_lock_init(&host->lock); 2826 spin_lock_init(&host->irq_lock); 2827 INIT_LIST_HEAD(&host->queue); 2828 2829 /* 2830 * Get the host data width - this assumes that HCON has been set with 2831 * the correct values. 2832 */ 2833 i = (mci_readl(host, HCON) >> 7) & 0x7; 2834 if (!i) { 2835 host->push_data = dw_mci_push_data16; 2836 host->pull_data = dw_mci_pull_data16; 2837 width = 16; 2838 host->data_shift = 1; 2839 } else if (i == 2) { 2840 host->push_data = dw_mci_push_data64; 2841 host->pull_data = dw_mci_pull_data64; 2842 width = 64; 2843 host->data_shift = 3; 2844 } else { 2845 /* Check for a reserved value, and warn if it is */ 2846 WARN((i != 1), 2847 "HCON reports a reserved host data width!\n" 2848 "Defaulting to 32-bit access.\n"); 2849 host->push_data = dw_mci_push_data32; 2850 host->pull_data = dw_mci_pull_data32; 2851 width = 32; 2852 host->data_shift = 2; 2853 } 2854 2855 /* Reset all blocks */ 2856 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) 2857 return -ENODEV; 2858 2859 host->dma_ops = host->pdata->dma_ops; 2860 dw_mci_init_dma(host); 2861 2862 /* Clear the interrupts for the host controller */ 2863 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2864 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2865 2866 /* Put in max timeout */ 2867 mci_writel(host, TMOUT, 0xFFFFFFFF); 2868 2869 /* 2870 * FIFO threshold settings RxMark = fifo_size / 2 - 1, 2871 * Tx Mark = fifo_size / 2 DMA Size = 8 2872 */ 2873 if (!host->pdata->fifo_depth) { 2874 /* 2875 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 2876 * have been overwritten by the bootloader, just like we're 2877 * about to do, so if you know the value for your hardware, you 2878 * should put it in the platform data. 2879 */ 2880 fifo_size = mci_readl(host, FIFOTH); 2881 fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 2882 } else { 2883 fifo_size = host->pdata->fifo_depth; 2884 } 2885 host->fifo_depth = fifo_size; 2886 host->fifoth_val = 2887 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 2888 mci_writel(host, FIFOTH, host->fifoth_val); 2889 2890 /* disable clock to CIU */ 2891 mci_writel(host, CLKENA, 0); 2892 mci_writel(host, CLKSRC, 0); 2893 2894 /* 2895 * In 2.40a spec, Data offset is changed. 2896 * Need to check the version-id and set data-offset for DATA register. 2897 */ 2898 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 2899 dev_info(host->dev, "Version ID is %04x\n", host->verid); 2900 2901 if (host->verid < DW_MMC_240A) 2902 host->fifo_reg = host->regs + DATA_OFFSET; 2903 else 2904 host->fifo_reg = host->regs + DATA_240A_OFFSET; 2905 2906 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 2907 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 2908 host->irq_flags, "dw-mci", host); 2909 if (ret) 2910 goto err_dmaunmap; 2911 2912 if (host->pdata->num_slots) 2913 host->num_slots = host->pdata->num_slots; 2914 else 2915 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; 2916 2917 /* 2918 * Enable interrupts for command done, data over, data empty, 2919 * receive ready and error such as transmit, receive timeout, crc error 2920 */ 2921 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2922 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 2923 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2924 DW_MCI_ERROR_FLAGS); 2925 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */ 2926 2927 dev_info(host->dev, "DW MMC controller at irq %d, " 2928 "%d bit host data width, " 2929 "%u deep fifo\n", 2930 host->irq, width, fifo_size); 2931 2932 /* We need at least one slot to succeed */ 2933 for (i = 0; i < host->num_slots; i++) { 2934 ret = dw_mci_init_slot(host, i); 2935 if (ret) 2936 dev_dbg(host->dev, "slot %d init failed\n", i); 2937 else 2938 init_slots++; 2939 } 2940 2941 if (init_slots) { 2942 dev_info(host->dev, "%d slots initialized\n", init_slots); 2943 } else { 2944 dev_dbg(host->dev, "attempted to initialize %d slots, " 2945 "but failed on all\n", host->num_slots); 2946 goto err_dmaunmap; 2947 } 2948 2949 /* Now that slots are all setup, we can enable card detect */ 2950 dw_mci_enable_cd(host); 2951 2952 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) 2953 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n"); 2954 2955 return 0; 2956 2957err_dmaunmap: 2958 if (host->use_dma && host->dma_ops->exit) 2959 host->dma_ops->exit(host); 2960 2961err_clk_ciu: 2962 if (!IS_ERR(host->ciu_clk)) 2963 clk_disable_unprepare(host->ciu_clk); 2964 2965err_clk_biu: 2966 if (!IS_ERR(host->biu_clk)) 2967 clk_disable_unprepare(host->biu_clk); 2968 2969 return ret; 2970} 2971EXPORT_SYMBOL(dw_mci_probe); 2972 2973void dw_mci_remove(struct dw_mci *host) 2974{ 2975 int i; 2976 2977 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2978 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2979 2980 for (i = 0; i < host->num_slots; i++) { 2981 dev_dbg(host->dev, "remove slot %d\n", i); 2982 if (host->slot[i]) 2983 dw_mci_cleanup_slot(host->slot[i], i); 2984 } 2985 2986 /* disable clock to CIU */ 2987 mci_writel(host, CLKENA, 0); 2988 mci_writel(host, CLKSRC, 0); 2989 2990 if (host->use_dma && host->dma_ops->exit) 2991 host->dma_ops->exit(host); 2992 2993 if (!IS_ERR(host->ciu_clk)) 2994 clk_disable_unprepare(host->ciu_clk); 2995 2996 if (!IS_ERR(host->biu_clk)) 2997 clk_disable_unprepare(host->biu_clk); 2998} 2999EXPORT_SYMBOL(dw_mci_remove); 3000 3001 3002 3003#ifdef CONFIG_PM_SLEEP 3004/* 3005 * TODO: we should probably disable the clock to the card in the suspend path. 3006 */ 3007int dw_mci_suspend(struct dw_mci *host) 3008{ 3009 return 0; 3010} 3011EXPORT_SYMBOL(dw_mci_suspend); 3012 3013int dw_mci_resume(struct dw_mci *host) 3014{ 3015 int i, ret; 3016 3017 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3018 ret = -ENODEV; 3019 return ret; 3020 } 3021 3022 if (host->use_dma && host->dma_ops->init) 3023 host->dma_ops->init(host); 3024 3025 /* 3026 * Restore the initial value at FIFOTH register 3027 * And Invalidate the prev_blksz with zero 3028 */ 3029 mci_writel(host, FIFOTH, host->fifoth_val); 3030 host->prev_blksz = 0; 3031 3032 /* Put in max timeout */ 3033 mci_writel(host, TMOUT, 0xFFFFFFFF); 3034 3035 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3036 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3037 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3038 DW_MCI_ERROR_FLAGS); 3039 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3040 3041 for (i = 0; i < host->num_slots; i++) { 3042 struct dw_mci_slot *slot = host->slot[i]; 3043 if (!slot) 3044 continue; 3045 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { 3046 dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 3047 dw_mci_setup_bus(slot, true); 3048 } 3049 } 3050 3051 /* Now that slots are all setup, we can enable card detect */ 3052 dw_mci_enable_cd(host); 3053 3054 return 0; 3055} 3056EXPORT_SYMBOL(dw_mci_resume); 3057#endif /* CONFIG_PM_SLEEP */ 3058 3059static int __init dw_mci_init(void) 3060{ 3061 pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 3062 return 0; 3063} 3064 3065static void __exit dw_mci_exit(void) 3066{ 3067} 3068 3069module_init(dw_mci_init); 3070module_exit(dw_mci_exit); 3071 3072MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3073MODULE_AUTHOR("NXP Semiconductor VietNam"); 3074MODULE_AUTHOR("Imagination Technologies Ltd"); 3075MODULE_LICENSE("GPL v2"); 3076