1/*
2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
3 *
4 * Author: Mike Lavender, mike@steroidmicros.com
5 *
6 * Copyright (c) 2005, Intec Automation Inc.
7 *
8 * Some parts are based on lart.c by Abraham Van Der Merwe
9 *
10 * Cleaned up and generalized based on mtd_dataflash.c
11 *
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18#include <linux/err.h>
19#include <linux/errno.h>
20#include <linux/module.h>
21#include <linux/device.h>
22
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/partitions.h>
25
26#include <linux/spi/spi.h>
27#include <linux/spi/flash.h>
28#include <linux/mtd/spi-nor.h>
29
30#define	MAX_CMD_SIZE		6
31struct m25p {
32	struct spi_device	*spi;
33	struct spi_nor		spi_nor;
34	struct mtd_info		mtd;
35	u8			command[MAX_CMD_SIZE];
36};
37
38static int m25p80_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
39{
40	struct m25p *flash = nor->priv;
41	struct spi_device *spi = flash->spi;
42	int ret;
43
44	ret = spi_write_then_read(spi, &code, 1, val, len);
45	if (ret < 0)
46		dev_err(&spi->dev, "error %d reading %x\n", ret, code);
47
48	return ret;
49}
50
51static void m25p_addr2cmd(struct spi_nor *nor, unsigned int addr, u8 *cmd)
52{
53	/* opcode is in cmd[0] */
54	cmd[1] = addr >> (nor->addr_width * 8 -  8);
55	cmd[2] = addr >> (nor->addr_width * 8 - 16);
56	cmd[3] = addr >> (nor->addr_width * 8 - 24);
57	cmd[4] = addr >> (nor->addr_width * 8 - 32);
58}
59
60static int m25p_cmdsz(struct spi_nor *nor)
61{
62	return 1 + nor->addr_width;
63}
64
65static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
66			int wr_en)
67{
68	struct m25p *flash = nor->priv;
69	struct spi_device *spi = flash->spi;
70
71	flash->command[0] = opcode;
72	if (buf)
73		memcpy(&flash->command[1], buf, len);
74
75	return spi_write(spi, flash->command, len + 1);
76}
77
78static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
79			size_t *retlen, const u_char *buf)
80{
81	struct m25p *flash = nor->priv;
82	struct spi_device *spi = flash->spi;
83	struct spi_transfer t[2] = {};
84	struct spi_message m;
85	int cmd_sz = m25p_cmdsz(nor);
86
87	spi_message_init(&m);
88
89	if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
90		cmd_sz = 1;
91
92	flash->command[0] = nor->program_opcode;
93	m25p_addr2cmd(nor, to, flash->command);
94
95	t[0].tx_buf = flash->command;
96	t[0].len = cmd_sz;
97	spi_message_add_tail(&t[0], &m);
98
99	t[1].tx_buf = buf;
100	t[1].len = len;
101	spi_message_add_tail(&t[1], &m);
102
103	spi_sync(spi, &m);
104
105	*retlen += m.actual_length - cmd_sz;
106}
107
108static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor)
109{
110	switch (nor->flash_read) {
111	case SPI_NOR_DUAL:
112		return 2;
113	case SPI_NOR_QUAD:
114		return 4;
115	default:
116		return 0;
117	}
118}
119
120/*
121 * Read an address range from the nor chip.  The address range
122 * may be any size provided it is within the physical boundaries.
123 */
124static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
125			size_t *retlen, u_char *buf)
126{
127	struct m25p *flash = nor->priv;
128	struct spi_device *spi = flash->spi;
129	struct spi_transfer t[2];
130	struct spi_message m;
131	unsigned int dummy = nor->read_dummy;
132
133	/* convert the dummy cycles to the number of bytes */
134	dummy /= 8;
135
136	spi_message_init(&m);
137	memset(t, 0, (sizeof t));
138
139	flash->command[0] = nor->read_opcode;
140	m25p_addr2cmd(nor, from, flash->command);
141
142	t[0].tx_buf = flash->command;
143	t[0].len = m25p_cmdsz(nor) + dummy;
144	spi_message_add_tail(&t[0], &m);
145
146	t[1].rx_buf = buf;
147	t[1].rx_nbits = m25p80_rx_nbits(nor);
148	t[1].len = len;
149	spi_message_add_tail(&t[1], &m);
150
151	spi_sync(spi, &m);
152
153	*retlen = m.actual_length - m25p_cmdsz(nor) - dummy;
154	return 0;
155}
156
157static int m25p80_erase(struct spi_nor *nor, loff_t offset)
158{
159	struct m25p *flash = nor->priv;
160
161	dev_dbg(nor->dev, "%dKiB at 0x%08x\n",
162		flash->mtd.erasesize / 1024, (u32)offset);
163
164	/* Set up command buffer. */
165	flash->command[0] = nor->erase_opcode;
166	m25p_addr2cmd(nor, offset, flash->command);
167
168	spi_write(flash->spi, flash->command, m25p_cmdsz(nor));
169
170	return 0;
171}
172
173/*
174 * board specific setup should have ensured the SPI clock used here
175 * matches what the READ command supports, at least until this driver
176 * understands FAST_READ (for clocks over 25 MHz).
177 */
178static int m25p_probe(struct spi_device *spi)
179{
180	struct mtd_part_parser_data	ppdata;
181	struct flash_platform_data	*data;
182	struct m25p *flash;
183	struct spi_nor *nor;
184	enum read_mode mode = SPI_NOR_NORMAL;
185	char *flash_name = NULL;
186	int ret;
187
188	data = dev_get_platdata(&spi->dev);
189
190	flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
191	if (!flash)
192		return -ENOMEM;
193
194	nor = &flash->spi_nor;
195
196	/* install the hooks */
197	nor->read = m25p80_read;
198	nor->write = m25p80_write;
199	nor->erase = m25p80_erase;
200	nor->write_reg = m25p80_write_reg;
201	nor->read_reg = m25p80_read_reg;
202
203	nor->dev = &spi->dev;
204	nor->mtd = &flash->mtd;
205	nor->priv = flash;
206
207	spi_set_drvdata(spi, flash);
208	flash->mtd.priv = nor;
209	flash->spi = spi;
210
211	if (spi->mode & SPI_RX_QUAD)
212		mode = SPI_NOR_QUAD;
213	else if (spi->mode & SPI_RX_DUAL)
214		mode = SPI_NOR_DUAL;
215
216	if (data && data->name)
217		flash->mtd.name = data->name;
218
219	/* For some (historical?) reason many platforms provide two different
220	 * names in flash_platform_data: "name" and "type". Quite often name is
221	 * set to "m25p80" and then "type" provides a real chip name.
222	 * If that's the case, respect "type" and ignore a "name".
223	 */
224	if (data && data->type)
225		flash_name = data->type;
226	else if (!strcmp(spi->modalias, "spi-nor"))
227		flash_name = NULL; /* auto-detect */
228	else
229		flash_name = spi->modalias;
230
231	ret = spi_nor_scan(nor, flash_name, mode);
232	if (ret)
233		return ret;
234
235	ppdata.of_node = spi->dev.of_node;
236
237	return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
238			data ? data->parts : NULL,
239			data ? data->nr_parts : 0);
240}
241
242
243static int m25p_remove(struct spi_device *spi)
244{
245	struct m25p	*flash = spi_get_drvdata(spi);
246
247	/* Clean up MTD stuff. */
248	return mtd_device_unregister(&flash->mtd);
249}
250
251/*
252 * Do NOT add to this array without reading the following:
253 *
254 * Historically, many flash devices are bound to this driver by their name. But
255 * since most of these flash are compatible to some extent, and their
256 * differences can often be differentiated by the JEDEC read-ID command, we
257 * encourage new users to add support to the spi-nor library, and simply bind
258 * against a generic string here (e.g., "jedec,spi-nor").
259 *
260 * Many flash names are kept here in this list (as well as in spi-nor.c) to
261 * keep them available as module aliases for existing platforms.
262 */
263static const struct spi_device_id m25p_ids[] = {
264	{"at25fs010"},	{"at25fs040"},	{"at25df041a"},	{"at25df321a"},
265	{"at25df641"},	{"at26f004"},	{"at26df081a"},	{"at26df161a"},
266	{"at26df321"},	{"at45db081d"},
267	{"en25f32"},	{"en25p32"},	{"en25q32b"},	{"en25p64"},
268	{"en25q64"},	{"en25qh128"},	{"en25qh256"},
269	{"f25l32pa"},
270	{"mr25h256"},	{"mr25h10"},
271	{"gd25q32"},	{"gd25q64"},
272	{"160s33b"},	{"320s33b"},	{"640s33b"},
273	{"mx25l2005a"},	{"mx25l4005a"},	{"mx25l8005"},	{"mx25l1606e"},
274	{"mx25l3205d"},	{"mx25l3255e"},	{"mx25l6405d"},	{"mx25l12805d"},
275	{"mx25l12855e"},{"mx25l25635e"},{"mx25l25655e"},{"mx66l51235l"},
276	{"mx66l1g55g"},
277	{"n25q064"},	{"n25q128a11"},	{"n25q128a13"},	{"n25q256a"},
278	{"n25q512a"},	{"n25q512ax3"},	{"n25q00"},
279	{"pm25lv512"},	{"pm25lv010"},	{"pm25lq032"},
280	{"s25sl032p"},	{"s25sl064p"},	{"s25fl256s0"},	{"s25fl256s1"},
281	{"s25fl512s"},	{"s70fl01gs"},	{"s25sl12800"},	{"s25sl12801"},
282	{"s25fl129p0"},	{"s25fl129p1"},	{"s25sl004a"},	{"s25sl008a"},
283	{"s25sl016a"},	{"s25sl032a"},	{"s25sl064a"},	{"s25fl008k"},
284	{"s25fl016k"},	{"s25fl064k"},	{"s25fl132k"},
285	{"sst25vf040b"},{"sst25vf080b"},{"sst25vf016b"},{"sst25vf032b"},
286	{"sst25vf064c"},{"sst25wf512"},	{"sst25wf010"},	{"sst25wf020"},
287	{"sst25wf040"},
288	{"m25p05"},	{"m25p10"},	{"m25p20"},	{"m25p40"},
289	{"m25p80"},	{"m25p16"},	{"m25p32"},	{"m25p64"},
290	{"m25p128"},	{"n25q032"},
291	{"m25p05-nonjedec"},	{"m25p10-nonjedec"},	{"m25p20-nonjedec"},
292	{"m25p40-nonjedec"},	{"m25p80-nonjedec"},	{"m25p16-nonjedec"},
293	{"m25p32-nonjedec"},	{"m25p64-nonjedec"},	{"m25p128-nonjedec"},
294	{"m45pe10"},	{"m45pe80"},	{"m45pe16"},
295	{"m25pe20"},	{"m25pe80"},	{"m25pe16"},
296	{"m25px16"},	{"m25px32"},	{"m25px32-s0"},	{"m25px32-s1"},
297	{"m25px64"},	{"m25px80"},
298	{"w25x10"},	{"w25x20"},	{"w25x40"},	{"w25x80"},
299	{"w25x16"},	{"w25x32"},	{"w25q32"},	{"w25q32dw"},
300	{"w25x64"},	{"w25q64"},	{"w25q80"},	{"w25q80bl"},
301	{"w25q128"},	{"w25q256"},	{"cat25c11"},
302	{"cat25c03"},	{"cat25c09"},	{"cat25c17"},	{"cat25128"},
303
304	/*
305	 * Generic support for SPI NOR that can be identified by the JEDEC READ
306	 * ID opcode (0x9F). Use this, if possible.
307	 */
308	{"spi-nor"},
309	{ },
310};
311MODULE_DEVICE_TABLE(spi, m25p_ids);
312
313static struct spi_driver m25p80_driver = {
314	.driver = {
315		.name	= "m25p80",
316		.owner	= THIS_MODULE,
317	},
318	.id_table	= m25p_ids,
319	.probe	= m25p_probe,
320	.remove	= m25p_remove,
321
322	/* REVISIT: many of these chips have deep power-down modes, which
323	 * should clearly be entered on suspend() to minimize power use.
324	 * And also when they're otherwise idle...
325	 */
326};
327
328module_spi_driver(m25p80_driver);
329
330MODULE_LICENSE("GPL");
331MODULE_AUTHOR("Mike Lavender");
332MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
333