1/* 2 * flexcan.c - FLEXCAN CAN controller driver 3 * 4 * Copyright (c) 2005-2006 Varma Electronics Oy 5 * Copyright (c) 2009 Sascha Hauer, Pengutronix 6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix 7 * 8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com> 9 * 10 * LICENCE: 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22#include <linux/netdevice.h> 23#include <linux/can.h> 24#include <linux/can/dev.h> 25#include <linux/can/error.h> 26#include <linux/can/led.h> 27#include <linux/clk.h> 28#include <linux/delay.h> 29#include <linux/if_arp.h> 30#include <linux/if_ether.h> 31#include <linux/interrupt.h> 32#include <linux/io.h> 33#include <linux/kernel.h> 34#include <linux/list.h> 35#include <linux/module.h> 36#include <linux/of.h> 37#include <linux/of_device.h> 38#include <linux/platform_device.h> 39#include <linux/regulator/consumer.h> 40 41#define DRV_NAME "flexcan" 42 43/* 8 for RX fifo and 2 error handling */ 44#define FLEXCAN_NAPI_WEIGHT (8 + 2) 45 46/* FLEXCAN module configuration register (CANMCR) bits */ 47#define FLEXCAN_MCR_MDIS BIT(31) 48#define FLEXCAN_MCR_FRZ BIT(30) 49#define FLEXCAN_MCR_FEN BIT(29) 50#define FLEXCAN_MCR_HALT BIT(28) 51#define FLEXCAN_MCR_NOT_RDY BIT(27) 52#define FLEXCAN_MCR_WAK_MSK BIT(26) 53#define FLEXCAN_MCR_SOFTRST BIT(25) 54#define FLEXCAN_MCR_FRZ_ACK BIT(24) 55#define FLEXCAN_MCR_SUPV BIT(23) 56#define FLEXCAN_MCR_SLF_WAK BIT(22) 57#define FLEXCAN_MCR_WRN_EN BIT(21) 58#define FLEXCAN_MCR_LPM_ACK BIT(20) 59#define FLEXCAN_MCR_WAK_SRC BIT(19) 60#define FLEXCAN_MCR_DOZE BIT(18) 61#define FLEXCAN_MCR_SRX_DIS BIT(17) 62#define FLEXCAN_MCR_BCC BIT(16) 63#define FLEXCAN_MCR_LPRIO_EN BIT(13) 64#define FLEXCAN_MCR_AEN BIT(12) 65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f) 66#define FLEXCAN_MCR_IDAM_A (0 << 8) 67#define FLEXCAN_MCR_IDAM_B (1 << 8) 68#define FLEXCAN_MCR_IDAM_C (2 << 8) 69#define FLEXCAN_MCR_IDAM_D (3 << 8) 70 71/* FLEXCAN control register (CANCTRL) bits */ 72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 76#define FLEXCAN_CTRL_BOFF_MSK BIT(15) 77#define FLEXCAN_CTRL_ERR_MSK BIT(14) 78#define FLEXCAN_CTRL_CLK_SRC BIT(13) 79#define FLEXCAN_CTRL_LPB BIT(12) 80#define FLEXCAN_CTRL_TWRN_MSK BIT(11) 81#define FLEXCAN_CTRL_RWRN_MSK BIT(10) 82#define FLEXCAN_CTRL_SMP BIT(7) 83#define FLEXCAN_CTRL_BOFF_REC BIT(6) 84#define FLEXCAN_CTRL_TSYN BIT(5) 85#define FLEXCAN_CTRL_LBUF BIT(4) 86#define FLEXCAN_CTRL_LOM BIT(3) 87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 89#define FLEXCAN_CTRL_ERR_STATE \ 90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 91 FLEXCAN_CTRL_BOFF_MSK) 92#define FLEXCAN_CTRL_ERR_ALL \ 93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 94 95/* FLEXCAN control register 2 (CTRL2) bits */ 96#define FLEXCAN_CRL2_ECRWRE BIT(29) 97#define FLEXCAN_CRL2_WRMFRZ BIT(28) 98#define FLEXCAN_CRL2_RFFN(x) (((x) & 0x0f) << 24) 99#define FLEXCAN_CRL2_TASD(x) (((x) & 0x1f) << 19) 100#define FLEXCAN_CRL2_MRP BIT(18) 101#define FLEXCAN_CRL2_RRS BIT(17) 102#define FLEXCAN_CRL2_EACEN BIT(16) 103 104/* FLEXCAN memory error control register (MECR) bits */ 105#define FLEXCAN_MECR_ECRWRDIS BIT(31) 106#define FLEXCAN_MECR_HANCEI_MSK BIT(19) 107#define FLEXCAN_MECR_FANCEI_MSK BIT(18) 108#define FLEXCAN_MECR_CEI_MSK BIT(16) 109#define FLEXCAN_MECR_HAERRIE BIT(15) 110#define FLEXCAN_MECR_FAERRIE BIT(14) 111#define FLEXCAN_MECR_EXTERRIE BIT(13) 112#define FLEXCAN_MECR_RERRDIS BIT(9) 113#define FLEXCAN_MECR_ECCDIS BIT(8) 114#define FLEXCAN_MECR_NCEFAFRZ BIT(7) 115 116/* FLEXCAN error and status register (ESR) bits */ 117#define FLEXCAN_ESR_TWRN_INT BIT(17) 118#define FLEXCAN_ESR_RWRN_INT BIT(16) 119#define FLEXCAN_ESR_BIT1_ERR BIT(15) 120#define FLEXCAN_ESR_BIT0_ERR BIT(14) 121#define FLEXCAN_ESR_ACK_ERR BIT(13) 122#define FLEXCAN_ESR_CRC_ERR BIT(12) 123#define FLEXCAN_ESR_FRM_ERR BIT(11) 124#define FLEXCAN_ESR_STF_ERR BIT(10) 125#define FLEXCAN_ESR_TX_WRN BIT(9) 126#define FLEXCAN_ESR_RX_WRN BIT(8) 127#define FLEXCAN_ESR_IDLE BIT(7) 128#define FLEXCAN_ESR_TXRX BIT(6) 129#define FLEXCAN_EST_FLT_CONF_SHIFT (4) 130#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 131#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 132#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 133#define FLEXCAN_ESR_BOFF_INT BIT(2) 134#define FLEXCAN_ESR_ERR_INT BIT(1) 135#define FLEXCAN_ESR_WAK_INT BIT(0) 136#define FLEXCAN_ESR_ERR_BUS \ 137 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 138 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 139 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 140#define FLEXCAN_ESR_ERR_STATE \ 141 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 142#define FLEXCAN_ESR_ERR_ALL \ 143 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 144#define FLEXCAN_ESR_ALL_INT \ 145 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ 146 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) 147 148/* FLEXCAN interrupt flag register (IFLAG) bits */ 149/* Errata ERR005829 step7: Reserve first valid MB */ 150#define FLEXCAN_TX_BUF_RESERVED 8 151#define FLEXCAN_TX_BUF_ID 9 152#define FLEXCAN_IFLAG_BUF(x) BIT(x) 153#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 154#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 155#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 156#define FLEXCAN_IFLAG_DEFAULT \ 157 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ 158 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) 159 160/* FLEXCAN message buffers */ 161#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) 162#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24) 163#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24) 164#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24) 165#define FLEXCAN_MB_CODE_RX_OVERRRUN (0x6 << 24) 166#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24) 167 168#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24) 169#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24) 170#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24) 171#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24) 172 173#define FLEXCAN_MB_CNT_SRR BIT(22) 174#define FLEXCAN_MB_CNT_IDE BIT(21) 175#define FLEXCAN_MB_CNT_RTR BIT(20) 176#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 177#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 178 179#define FLEXCAN_MB_CODE_MASK (0xf0ffffff) 180 181#define FLEXCAN_TIMEOUT_US (50) 182 183/* 184 * FLEXCAN hardware feature flags 185 * 186 * Below is some version info we got: 187 * SOC Version IP-Version Glitch- [TR]WRN_INT Memory err 188 * Filter? connected? detection 189 * MX25 FlexCAN2 03.00.00.00 no no no 190 * MX28 FlexCAN2 03.00.04.00 yes yes no 191 * MX35 FlexCAN2 03.00.00.00 no no no 192 * MX53 FlexCAN2 03.00.00.00 yes no no 193 * MX6s FlexCAN3 10.00.12.00 yes yes no 194 * VF610 FlexCAN3 ? no yes yes 195 * 196 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected. 197 */ 198#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */ 199#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */ 200#define FLEXCAN_HAS_MECR_FEATURES BIT(3) /* Memory error detection */ 201 202/* Structure of the message buffer */ 203struct flexcan_mb { 204 u32 can_ctrl; 205 u32 can_id; 206 u32 data[2]; 207}; 208 209/* Structure of the hardware registers */ 210struct flexcan_regs { 211 u32 mcr; /* 0x00 */ 212 u32 ctrl; /* 0x04 */ 213 u32 timer; /* 0x08 */ 214 u32 _reserved1; /* 0x0c */ 215 u32 rxgmask; /* 0x10 */ 216 u32 rx14mask; /* 0x14 */ 217 u32 rx15mask; /* 0x18 */ 218 u32 ecr; /* 0x1c */ 219 u32 esr; /* 0x20 */ 220 u32 imask2; /* 0x24 */ 221 u32 imask1; /* 0x28 */ 222 u32 iflag2; /* 0x2c */ 223 u32 iflag1; /* 0x30 */ 224 u32 crl2; /* 0x34 */ 225 u32 esr2; /* 0x38 */ 226 u32 imeur; /* 0x3c */ 227 u32 lrfr; /* 0x40 */ 228 u32 crcr; /* 0x44 */ 229 u32 rxfgmask; /* 0x48 */ 230 u32 rxfir; /* 0x4c */ 231 u32 _reserved3[12]; /* 0x50 */ 232 struct flexcan_mb cantxfg[64]; /* 0x80 */ 233 u32 _reserved4[408]; 234 u32 mecr; /* 0xae0 */ 235 u32 erriar; /* 0xae4 */ 236 u32 erridpr; /* 0xae8 */ 237 u32 errippr; /* 0xaec */ 238 u32 rerrar; /* 0xaf0 */ 239 u32 rerrdr; /* 0xaf4 */ 240 u32 rerrsynr; /* 0xaf8 */ 241 u32 errsr; /* 0xafc */ 242}; 243 244struct flexcan_devtype_data { 245 u32 features; /* hardware controller features */ 246}; 247 248struct flexcan_priv { 249 struct can_priv can; 250 struct napi_struct napi; 251 252 void __iomem *base; 253 u32 reg_esr; 254 u32 reg_ctrl_default; 255 256 struct clk *clk_ipg; 257 struct clk *clk_per; 258 struct flexcan_platform_data *pdata; 259 const struct flexcan_devtype_data *devtype_data; 260 struct regulator *reg_xceiver; 261}; 262 263static struct flexcan_devtype_data fsl_p1010_devtype_data = { 264 .features = FLEXCAN_HAS_BROKEN_ERR_STATE, 265}; 266static struct flexcan_devtype_data fsl_imx28_devtype_data; 267static struct flexcan_devtype_data fsl_imx6q_devtype_data = { 268 .features = FLEXCAN_HAS_V10_FEATURES, 269}; 270static struct flexcan_devtype_data fsl_vf610_devtype_data = { 271 .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES, 272}; 273 274static const struct can_bittiming_const flexcan_bittiming_const = { 275 .name = DRV_NAME, 276 .tseg1_min = 4, 277 .tseg1_max = 16, 278 .tseg2_min = 2, 279 .tseg2_max = 8, 280 .sjw_max = 4, 281 .brp_min = 1, 282 .brp_max = 256, 283 .brp_inc = 1, 284}; 285 286/* 287 * Abstract off the read/write for arm versus ppc. This 288 * assumes that PPC uses big-endian registers and everything 289 * else uses little-endian registers, independent of CPU 290 * endianess. 291 */ 292#if defined(CONFIG_PPC) 293static inline u32 flexcan_read(void __iomem *addr) 294{ 295 return in_be32(addr); 296} 297 298static inline void flexcan_write(u32 val, void __iomem *addr) 299{ 300 out_be32(addr, val); 301} 302#else 303static inline u32 flexcan_read(void __iomem *addr) 304{ 305 return readl(addr); 306} 307 308static inline void flexcan_write(u32 val, void __iomem *addr) 309{ 310 writel(val, addr); 311} 312#endif 313 314static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv) 315{ 316 if (!priv->reg_xceiver) 317 return 0; 318 319 return regulator_enable(priv->reg_xceiver); 320} 321 322static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv) 323{ 324 if (!priv->reg_xceiver) 325 return 0; 326 327 return regulator_disable(priv->reg_xceiver); 328} 329 330static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, 331 u32 reg_esr) 332{ 333 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 334 (reg_esr & FLEXCAN_ESR_ERR_BUS); 335} 336 337static int flexcan_chip_enable(struct flexcan_priv *priv) 338{ 339 struct flexcan_regs __iomem *regs = priv->base; 340 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 341 u32 reg; 342 343 reg = flexcan_read(®s->mcr); 344 reg &= ~FLEXCAN_MCR_MDIS; 345 flexcan_write(reg, ®s->mcr); 346 347 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 348 udelay(10); 349 350 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK) 351 return -ETIMEDOUT; 352 353 return 0; 354} 355 356static int flexcan_chip_disable(struct flexcan_priv *priv) 357{ 358 struct flexcan_regs __iomem *regs = priv->base; 359 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 360 u32 reg; 361 362 reg = flexcan_read(®s->mcr); 363 reg |= FLEXCAN_MCR_MDIS; 364 flexcan_write(reg, ®s->mcr); 365 366 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 367 udelay(10); 368 369 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 370 return -ETIMEDOUT; 371 372 return 0; 373} 374 375static int flexcan_chip_freeze(struct flexcan_priv *priv) 376{ 377 struct flexcan_regs __iomem *regs = priv->base; 378 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate; 379 u32 reg; 380 381 reg = flexcan_read(®s->mcr); 382 reg |= FLEXCAN_MCR_HALT; 383 flexcan_write(reg, ®s->mcr); 384 385 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 386 udelay(100); 387 388 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 389 return -ETIMEDOUT; 390 391 return 0; 392} 393 394static int flexcan_chip_unfreeze(struct flexcan_priv *priv) 395{ 396 struct flexcan_regs __iomem *regs = priv->base; 397 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 398 u32 reg; 399 400 reg = flexcan_read(®s->mcr); 401 reg &= ~FLEXCAN_MCR_HALT; 402 flexcan_write(reg, ®s->mcr); 403 404 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 405 udelay(10); 406 407 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK) 408 return -ETIMEDOUT; 409 410 return 0; 411} 412 413static int flexcan_chip_softreset(struct flexcan_priv *priv) 414{ 415 struct flexcan_regs __iomem *regs = priv->base; 416 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 417 418 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 419 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)) 420 udelay(10); 421 422 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST) 423 return -ETIMEDOUT; 424 425 return 0; 426} 427 428 429static int __flexcan_get_berr_counter(const struct net_device *dev, 430 struct can_berr_counter *bec) 431{ 432 const struct flexcan_priv *priv = netdev_priv(dev); 433 struct flexcan_regs __iomem *regs = priv->base; 434 u32 reg = flexcan_read(®s->ecr); 435 436 bec->txerr = (reg >> 0) & 0xff; 437 bec->rxerr = (reg >> 8) & 0xff; 438 439 return 0; 440} 441 442static int flexcan_get_berr_counter(const struct net_device *dev, 443 struct can_berr_counter *bec) 444{ 445 const struct flexcan_priv *priv = netdev_priv(dev); 446 int err; 447 448 err = clk_prepare_enable(priv->clk_ipg); 449 if (err) 450 return err; 451 452 err = clk_prepare_enable(priv->clk_per); 453 if (err) 454 goto out_disable_ipg; 455 456 err = __flexcan_get_berr_counter(dev, bec); 457 458 clk_disable_unprepare(priv->clk_per); 459 out_disable_ipg: 460 clk_disable_unprepare(priv->clk_ipg); 461 462 return err; 463} 464 465static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 466{ 467 const struct flexcan_priv *priv = netdev_priv(dev); 468 struct flexcan_regs __iomem *regs = priv->base; 469 struct can_frame *cf = (struct can_frame *)skb->data; 470 u32 can_id; 471 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); 472 473 if (can_dropped_invalid_skb(dev, skb)) 474 return NETDEV_TX_OK; 475 476 netif_stop_queue(dev); 477 478 if (cf->can_id & CAN_EFF_FLAG) { 479 can_id = cf->can_id & CAN_EFF_MASK; 480 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 481 } else { 482 can_id = (cf->can_id & CAN_SFF_MASK) << 18; 483 } 484 485 if (cf->can_id & CAN_RTR_FLAG) 486 ctrl |= FLEXCAN_MB_CNT_RTR; 487 488 if (cf->can_dlc > 0) { 489 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 490 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 491 } 492 if (cf->can_dlc > 3) { 493 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 494 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 495 } 496 497 can_put_echo_skb(skb, dev, 0); 498 499 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 500 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 501 502 /* Errata ERR005829 step8: 503 * Write twice INACTIVE(0x8) code to first MB. 504 */ 505 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, 506 ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl); 507 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, 508 ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl); 509 510 return NETDEV_TX_OK; 511} 512 513static void do_bus_err(struct net_device *dev, 514 struct can_frame *cf, u32 reg_esr) 515{ 516 struct flexcan_priv *priv = netdev_priv(dev); 517 int rx_errors = 0, tx_errors = 0; 518 519 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 520 521 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 522 netdev_dbg(dev, "BIT1_ERR irq\n"); 523 cf->data[2] |= CAN_ERR_PROT_BIT1; 524 tx_errors = 1; 525 } 526 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 527 netdev_dbg(dev, "BIT0_ERR irq\n"); 528 cf->data[2] |= CAN_ERR_PROT_BIT0; 529 tx_errors = 1; 530 } 531 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 532 netdev_dbg(dev, "ACK_ERR irq\n"); 533 cf->can_id |= CAN_ERR_ACK; 534 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 535 tx_errors = 1; 536 } 537 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 538 netdev_dbg(dev, "CRC_ERR irq\n"); 539 cf->data[2] |= CAN_ERR_PROT_BIT; 540 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 541 rx_errors = 1; 542 } 543 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 544 netdev_dbg(dev, "FRM_ERR irq\n"); 545 cf->data[2] |= CAN_ERR_PROT_FORM; 546 rx_errors = 1; 547 } 548 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 549 netdev_dbg(dev, "STF_ERR irq\n"); 550 cf->data[2] |= CAN_ERR_PROT_STUFF; 551 rx_errors = 1; 552 } 553 554 priv->can.can_stats.bus_error++; 555 if (rx_errors) 556 dev->stats.rx_errors++; 557 if (tx_errors) 558 dev->stats.tx_errors++; 559} 560 561static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) 562{ 563 struct sk_buff *skb; 564 struct can_frame *cf; 565 566 skb = alloc_can_err_skb(dev, &cf); 567 if (unlikely(!skb)) 568 return 0; 569 570 do_bus_err(dev, cf, reg_esr); 571 netif_receive_skb(skb); 572 573 dev->stats.rx_packets++; 574 dev->stats.rx_bytes += cf->can_dlc; 575 576 return 1; 577} 578 579static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) 580{ 581 struct flexcan_priv *priv = netdev_priv(dev); 582 struct sk_buff *skb; 583 struct can_frame *cf; 584 enum can_state new_state = 0, rx_state = 0, tx_state = 0; 585 int flt; 586 struct can_berr_counter bec; 587 588 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 589 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 590 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ? 591 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE; 592 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ? 593 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE; 594 new_state = max(tx_state, rx_state); 595 } else { 596 __flexcan_get_berr_counter(dev, &bec); 597 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ? 598 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF; 599 rx_state = bec.rxerr >= bec.txerr ? new_state : 0; 600 tx_state = bec.rxerr <= bec.txerr ? new_state : 0; 601 } 602 603 /* state hasn't changed */ 604 if (likely(new_state == priv->can.state)) 605 return 0; 606 607 skb = alloc_can_err_skb(dev, &cf); 608 if (unlikely(!skb)) 609 return 0; 610 611 can_change_state(dev, cf, tx_state, rx_state); 612 613 if (unlikely(new_state == CAN_STATE_BUS_OFF)) 614 can_bus_off(dev); 615 616 netif_receive_skb(skb); 617 618 dev->stats.rx_packets++; 619 dev->stats.rx_bytes += cf->can_dlc; 620 621 return 1; 622} 623 624static void flexcan_read_fifo(const struct net_device *dev, 625 struct can_frame *cf) 626{ 627 const struct flexcan_priv *priv = netdev_priv(dev); 628 struct flexcan_regs __iomem *regs = priv->base; 629 struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; 630 u32 reg_ctrl, reg_id; 631 632 reg_ctrl = flexcan_read(&mb->can_ctrl); 633 reg_id = flexcan_read(&mb->can_id); 634 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 635 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 636 else 637 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; 638 639 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 640 cf->can_id |= CAN_RTR_FLAG; 641 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 642 643 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); 644 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); 645 646 /* mark as read */ 647 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 648 flexcan_read(®s->timer); 649} 650 651static int flexcan_read_frame(struct net_device *dev) 652{ 653 struct net_device_stats *stats = &dev->stats; 654 struct can_frame *cf; 655 struct sk_buff *skb; 656 657 skb = alloc_can_skb(dev, &cf); 658 if (unlikely(!skb)) { 659 stats->rx_dropped++; 660 return 0; 661 } 662 663 flexcan_read_fifo(dev, cf); 664 netif_receive_skb(skb); 665 666 stats->rx_packets++; 667 stats->rx_bytes += cf->can_dlc; 668 669 can_led_event(dev, CAN_LED_EVENT_RX); 670 671 return 1; 672} 673 674static int flexcan_poll(struct napi_struct *napi, int quota) 675{ 676 struct net_device *dev = napi->dev; 677 const struct flexcan_priv *priv = netdev_priv(dev); 678 struct flexcan_regs __iomem *regs = priv->base; 679 u32 reg_iflag1, reg_esr; 680 int work_done = 0; 681 682 /* 683 * The error bits are cleared on read, 684 * use saved value from irq handler. 685 */ 686 reg_esr = flexcan_read(®s->esr) | priv->reg_esr; 687 688 /* handle state changes */ 689 work_done += flexcan_poll_state(dev, reg_esr); 690 691 /* handle RX-FIFO */ 692 reg_iflag1 = flexcan_read(®s->iflag1); 693 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 694 work_done < quota) { 695 work_done += flexcan_read_frame(dev); 696 reg_iflag1 = flexcan_read(®s->iflag1); 697 } 698 699 /* report bus errors */ 700 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) 701 work_done += flexcan_poll_bus_err(dev, reg_esr); 702 703 if (work_done < quota) { 704 napi_complete(napi); 705 /* enable IRQs */ 706 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 707 flexcan_write(priv->reg_ctrl_default, ®s->ctrl); 708 } 709 710 return work_done; 711} 712 713static irqreturn_t flexcan_irq(int irq, void *dev_id) 714{ 715 struct net_device *dev = dev_id; 716 struct net_device_stats *stats = &dev->stats; 717 struct flexcan_priv *priv = netdev_priv(dev); 718 struct flexcan_regs __iomem *regs = priv->base; 719 u32 reg_iflag1, reg_esr; 720 721 reg_iflag1 = flexcan_read(®s->iflag1); 722 reg_esr = flexcan_read(®s->esr); 723 /* ACK all bus error and state change IRQ sources */ 724 if (reg_esr & FLEXCAN_ESR_ALL_INT) 725 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); 726 727 /* 728 * schedule NAPI in case of: 729 * - rx IRQ 730 * - state change IRQ 731 * - bus error IRQ and bus error reporting is activated 732 */ 733 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || 734 (reg_esr & FLEXCAN_ESR_ERR_STATE) || 735 flexcan_has_and_handle_berr(priv, reg_esr)) { 736 /* 737 * The error bits are cleared on read, 738 * save them for later use. 739 */ 740 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 741 flexcan_write(FLEXCAN_IFLAG_DEFAULT & 742 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); 743 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 744 ®s->ctrl); 745 napi_schedule(&priv->napi); 746 } 747 748 /* FIFO overflow */ 749 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 750 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); 751 dev->stats.rx_over_errors++; 752 dev->stats.rx_errors++; 753 } 754 755 /* transmission complete interrupt */ 756 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 757 stats->tx_bytes += can_get_echo_skb(dev, 0); 758 stats->tx_packets++; 759 can_led_event(dev, CAN_LED_EVENT_TX); 760 /* after sending a RTR frame mailbox is in RX mode */ 761 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, 762 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 763 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); 764 netif_wake_queue(dev); 765 } 766 767 return IRQ_HANDLED; 768} 769 770static void flexcan_set_bittiming(struct net_device *dev) 771{ 772 const struct flexcan_priv *priv = netdev_priv(dev); 773 const struct can_bittiming *bt = &priv->can.bittiming; 774 struct flexcan_regs __iomem *regs = priv->base; 775 u32 reg; 776 777 reg = flexcan_read(®s->ctrl); 778 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 779 FLEXCAN_CTRL_RJW(0x3) | 780 FLEXCAN_CTRL_PSEG1(0x7) | 781 FLEXCAN_CTRL_PSEG2(0x7) | 782 FLEXCAN_CTRL_PROPSEG(0x7) | 783 FLEXCAN_CTRL_LPB | 784 FLEXCAN_CTRL_SMP | 785 FLEXCAN_CTRL_LOM); 786 787 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 788 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 789 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 790 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 791 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 792 793 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 794 reg |= FLEXCAN_CTRL_LPB; 795 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 796 reg |= FLEXCAN_CTRL_LOM; 797 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 798 reg |= FLEXCAN_CTRL_SMP; 799 800 netdev_info(dev, "writing ctrl=0x%08x\n", reg); 801 flexcan_write(reg, ®s->ctrl); 802 803 /* print chip status */ 804 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 805 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 806} 807 808/* 809 * flexcan_chip_start 810 * 811 * this functions is entered with clocks enabled 812 * 813 */ 814static int flexcan_chip_start(struct net_device *dev) 815{ 816 struct flexcan_priv *priv = netdev_priv(dev); 817 struct flexcan_regs __iomem *regs = priv->base; 818 u32 reg_mcr, reg_ctrl, reg_crl2, reg_mecr; 819 int err, i; 820 821 /* enable module */ 822 err = flexcan_chip_enable(priv); 823 if (err) 824 return err; 825 826 /* soft reset */ 827 err = flexcan_chip_softreset(priv); 828 if (err) 829 goto out_chip_disable; 830 831 flexcan_set_bittiming(dev); 832 833 /* 834 * MCR 835 * 836 * enable freeze 837 * enable fifo 838 * halt now 839 * only supervisor access 840 * enable warning int 841 * choose format C 842 * disable local echo 843 * 844 */ 845 reg_mcr = flexcan_read(®s->mcr); 846 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff); 847 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 848 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 849 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS | 850 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID); 851 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); 852 flexcan_write(reg_mcr, ®s->mcr); 853 854 /* 855 * CTRL 856 * 857 * disable timer sync feature 858 * 859 * disable auto busoff recovery 860 * transmit lowest buffer first 861 * 862 * enable tx and rx warning interrupt 863 * enable bus off interrupt 864 * (== FLEXCAN_CTRL_ERR_STATE) 865 */ 866 reg_ctrl = flexcan_read(®s->ctrl); 867 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 868 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 869 FLEXCAN_CTRL_ERR_STATE; 870 /* 871 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), 872 * on most Flexcan cores, too. Otherwise we don't get 873 * any error warning or passive interrupts. 874 */ 875 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE || 876 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 877 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; 878 else 879 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK; 880 881 /* save for later use */ 882 priv->reg_ctrl_default = reg_ctrl; 883 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 884 flexcan_write(reg_ctrl, ®s->ctrl); 885 886 /* clear and invalidate all mailboxes first */ 887 for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) { 888 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE, 889 ®s->cantxfg[i].can_ctrl); 890 } 891 892 /* Errata ERR005829: mark first TX mailbox as INACTIVE */ 893 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, 894 ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl); 895 896 /* mark TX mailbox as INACTIVE */ 897 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, 898 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 899 900 /* acceptance mask/acceptance code (accept everything) */ 901 flexcan_write(0x0, ®s->rxgmask); 902 flexcan_write(0x0, ®s->rx14mask); 903 flexcan_write(0x0, ®s->rx15mask); 904 905 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) 906 flexcan_write(0x0, ®s->rxfgmask); 907 908 /* 909 * On Vybrid, disable memory error detection interrupts 910 * and freeze mode. 911 * This also works around errata e5295 which generates 912 * false positive memory errors and put the device in 913 * freeze mode. 914 */ 915 if (priv->devtype_data->features & FLEXCAN_HAS_MECR_FEATURES) { 916 /* 917 * Follow the protocol as described in "Detection 918 * and Correction of Memory Errors" to write to 919 * MECR register 920 */ 921 reg_crl2 = flexcan_read(®s->crl2); 922 reg_crl2 |= FLEXCAN_CRL2_ECRWRE; 923 flexcan_write(reg_crl2, ®s->crl2); 924 925 reg_mecr = flexcan_read(®s->mecr); 926 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS; 927 flexcan_write(reg_mecr, ®s->mecr); 928 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK | 929 FLEXCAN_MECR_FANCEI_MSK); 930 flexcan_write(reg_mecr, ®s->mecr); 931 } 932 933 err = flexcan_transceiver_enable(priv); 934 if (err) 935 goto out_chip_disable; 936 937 /* synchronize with the can bus */ 938 err = flexcan_chip_unfreeze(priv); 939 if (err) 940 goto out_transceiver_disable; 941 942 priv->can.state = CAN_STATE_ERROR_ACTIVE; 943 944 /* enable FIFO interrupts */ 945 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 946 947 /* print chip status */ 948 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, 949 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 950 951 return 0; 952 953 out_transceiver_disable: 954 flexcan_transceiver_disable(priv); 955 out_chip_disable: 956 flexcan_chip_disable(priv); 957 return err; 958} 959 960/* 961 * flexcan_chip_stop 962 * 963 * this functions is entered with clocks enabled 964 * 965 */ 966static void flexcan_chip_stop(struct net_device *dev) 967{ 968 struct flexcan_priv *priv = netdev_priv(dev); 969 struct flexcan_regs __iomem *regs = priv->base; 970 971 /* freeze + disable module */ 972 flexcan_chip_freeze(priv); 973 flexcan_chip_disable(priv); 974 975 /* Disable all interrupts */ 976 flexcan_write(0, ®s->imask1); 977 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 978 ®s->ctrl); 979 980 flexcan_transceiver_disable(priv); 981 priv->can.state = CAN_STATE_STOPPED; 982 983 return; 984} 985 986static int flexcan_open(struct net_device *dev) 987{ 988 struct flexcan_priv *priv = netdev_priv(dev); 989 int err; 990 991 err = clk_prepare_enable(priv->clk_ipg); 992 if (err) 993 return err; 994 995 err = clk_prepare_enable(priv->clk_per); 996 if (err) 997 goto out_disable_ipg; 998 999 err = open_candev(dev); 1000 if (err) 1001 goto out_disable_per; 1002 1003 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 1004 if (err) 1005 goto out_close; 1006 1007 /* start chip and queuing */ 1008 err = flexcan_chip_start(dev); 1009 if (err) 1010 goto out_free_irq; 1011 1012 can_led_event(dev, CAN_LED_EVENT_OPEN); 1013 1014 napi_enable(&priv->napi); 1015 netif_start_queue(dev); 1016 1017 return 0; 1018 1019 out_free_irq: 1020 free_irq(dev->irq, dev); 1021 out_close: 1022 close_candev(dev); 1023 out_disable_per: 1024 clk_disable_unprepare(priv->clk_per); 1025 out_disable_ipg: 1026 clk_disable_unprepare(priv->clk_ipg); 1027 1028 return err; 1029} 1030 1031static int flexcan_close(struct net_device *dev) 1032{ 1033 struct flexcan_priv *priv = netdev_priv(dev); 1034 1035 netif_stop_queue(dev); 1036 napi_disable(&priv->napi); 1037 flexcan_chip_stop(dev); 1038 1039 free_irq(dev->irq, dev); 1040 clk_disable_unprepare(priv->clk_per); 1041 clk_disable_unprepare(priv->clk_ipg); 1042 1043 close_candev(dev); 1044 1045 can_led_event(dev, CAN_LED_EVENT_STOP); 1046 1047 return 0; 1048} 1049 1050static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 1051{ 1052 int err; 1053 1054 switch (mode) { 1055 case CAN_MODE_START: 1056 err = flexcan_chip_start(dev); 1057 if (err) 1058 return err; 1059 1060 netif_wake_queue(dev); 1061 break; 1062 1063 default: 1064 return -EOPNOTSUPP; 1065 } 1066 1067 return 0; 1068} 1069 1070static const struct net_device_ops flexcan_netdev_ops = { 1071 .ndo_open = flexcan_open, 1072 .ndo_stop = flexcan_close, 1073 .ndo_start_xmit = flexcan_start_xmit, 1074 .ndo_change_mtu = can_change_mtu, 1075}; 1076 1077static int register_flexcandev(struct net_device *dev) 1078{ 1079 struct flexcan_priv *priv = netdev_priv(dev); 1080 struct flexcan_regs __iomem *regs = priv->base; 1081 u32 reg, err; 1082 1083 err = clk_prepare_enable(priv->clk_ipg); 1084 if (err) 1085 return err; 1086 1087 err = clk_prepare_enable(priv->clk_per); 1088 if (err) 1089 goto out_disable_ipg; 1090 1091 /* select "bus clock", chip must be disabled */ 1092 err = flexcan_chip_disable(priv); 1093 if (err) 1094 goto out_disable_per; 1095 reg = flexcan_read(®s->ctrl); 1096 reg |= FLEXCAN_CTRL_CLK_SRC; 1097 flexcan_write(reg, ®s->ctrl); 1098 1099 err = flexcan_chip_enable(priv); 1100 if (err) 1101 goto out_chip_disable; 1102 1103 /* set freeze, halt and activate FIFO, restrict register access */ 1104 reg = flexcan_read(®s->mcr); 1105 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 1106 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 1107 flexcan_write(reg, ®s->mcr); 1108 1109 /* 1110 * Currently we only support newer versions of this core 1111 * featuring a RX FIFO. Older cores found on some Coldfire 1112 * derivates are not yet supported. 1113 */ 1114 reg = flexcan_read(®s->mcr); 1115 if (!(reg & FLEXCAN_MCR_FEN)) { 1116 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); 1117 err = -ENODEV; 1118 goto out_chip_disable; 1119 } 1120 1121 err = register_candev(dev); 1122 1123 /* disable core and turn off clocks */ 1124 out_chip_disable: 1125 flexcan_chip_disable(priv); 1126 out_disable_per: 1127 clk_disable_unprepare(priv->clk_per); 1128 out_disable_ipg: 1129 clk_disable_unprepare(priv->clk_ipg); 1130 1131 return err; 1132} 1133 1134static void unregister_flexcandev(struct net_device *dev) 1135{ 1136 unregister_candev(dev); 1137} 1138 1139static const struct of_device_id flexcan_of_match[] = { 1140 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, 1141 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, 1142 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, 1143 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, }, 1144 { /* sentinel */ }, 1145}; 1146MODULE_DEVICE_TABLE(of, flexcan_of_match); 1147 1148static const struct platform_device_id flexcan_id_table[] = { 1149 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, }, 1150 { /* sentinel */ }, 1151}; 1152MODULE_DEVICE_TABLE(platform, flexcan_id_table); 1153 1154static int flexcan_probe(struct platform_device *pdev) 1155{ 1156 const struct of_device_id *of_id; 1157 const struct flexcan_devtype_data *devtype_data; 1158 struct net_device *dev; 1159 struct flexcan_priv *priv; 1160 struct regulator *reg_xceiver; 1161 struct resource *mem; 1162 struct clk *clk_ipg = NULL, *clk_per = NULL; 1163 void __iomem *base; 1164 int err, irq; 1165 u32 clock_freq = 0; 1166 1167 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); 1168 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) 1169 return -EPROBE_DEFER; 1170 else if (IS_ERR(reg_xceiver)) 1171 reg_xceiver = NULL; 1172 1173 if (pdev->dev.of_node) 1174 of_property_read_u32(pdev->dev.of_node, 1175 "clock-frequency", &clock_freq); 1176 1177 if (!clock_freq) { 1178 clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1179 if (IS_ERR(clk_ipg)) { 1180 dev_err(&pdev->dev, "no ipg clock defined\n"); 1181 return PTR_ERR(clk_ipg); 1182 } 1183 1184 clk_per = devm_clk_get(&pdev->dev, "per"); 1185 if (IS_ERR(clk_per)) { 1186 dev_err(&pdev->dev, "no per clock defined\n"); 1187 return PTR_ERR(clk_per); 1188 } 1189 clock_freq = clk_get_rate(clk_per); 1190 } 1191 1192 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1193 irq = platform_get_irq(pdev, 0); 1194 if (irq <= 0) 1195 return -ENODEV; 1196 1197 base = devm_ioremap_resource(&pdev->dev, mem); 1198 if (IS_ERR(base)) 1199 return PTR_ERR(base); 1200 1201 of_id = of_match_device(flexcan_of_match, &pdev->dev); 1202 if (of_id) { 1203 devtype_data = of_id->data; 1204 } else if (platform_get_device_id(pdev)->driver_data) { 1205 devtype_data = (struct flexcan_devtype_data *) 1206 platform_get_device_id(pdev)->driver_data; 1207 } else { 1208 return -ENODEV; 1209 } 1210 1211 dev = alloc_candev(sizeof(struct flexcan_priv), 1); 1212 if (!dev) 1213 return -ENOMEM; 1214 1215 dev->netdev_ops = &flexcan_netdev_ops; 1216 dev->irq = irq; 1217 dev->flags |= IFF_ECHO; 1218 1219 priv = netdev_priv(dev); 1220 priv->can.clock.freq = clock_freq; 1221 priv->can.bittiming_const = &flexcan_bittiming_const; 1222 priv->can.do_set_mode = flexcan_set_mode; 1223 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 1224 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1225 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 1226 CAN_CTRLMODE_BERR_REPORTING; 1227 priv->base = base; 1228 priv->clk_ipg = clk_ipg; 1229 priv->clk_per = clk_per; 1230 priv->pdata = dev_get_platdata(&pdev->dev); 1231 priv->devtype_data = devtype_data; 1232 1233 priv->reg_xceiver = reg_xceiver; 1234 1235 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); 1236 1237 platform_set_drvdata(pdev, dev); 1238 SET_NETDEV_DEV(dev, &pdev->dev); 1239 1240 err = register_flexcandev(dev); 1241 if (err) { 1242 dev_err(&pdev->dev, "registering netdev failed\n"); 1243 goto failed_register; 1244 } 1245 1246 devm_can_led_init(dev); 1247 1248 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1249 priv->base, dev->irq); 1250 1251 return 0; 1252 1253 failed_register: 1254 free_candev(dev); 1255 return err; 1256} 1257 1258static int flexcan_remove(struct platform_device *pdev) 1259{ 1260 struct net_device *dev = platform_get_drvdata(pdev); 1261 struct flexcan_priv *priv = netdev_priv(dev); 1262 1263 unregister_flexcandev(dev); 1264 netif_napi_del(&priv->napi); 1265 free_candev(dev); 1266 1267 return 0; 1268} 1269 1270static int __maybe_unused flexcan_suspend(struct device *device) 1271{ 1272 struct net_device *dev = dev_get_drvdata(device); 1273 struct flexcan_priv *priv = netdev_priv(dev); 1274 int err; 1275 1276 err = flexcan_chip_disable(priv); 1277 if (err) 1278 return err; 1279 1280 if (netif_running(dev)) { 1281 netif_stop_queue(dev); 1282 netif_device_detach(dev); 1283 } 1284 priv->can.state = CAN_STATE_SLEEPING; 1285 1286 return 0; 1287} 1288 1289static int __maybe_unused flexcan_resume(struct device *device) 1290{ 1291 struct net_device *dev = dev_get_drvdata(device); 1292 struct flexcan_priv *priv = netdev_priv(dev); 1293 1294 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1295 if (netif_running(dev)) { 1296 netif_device_attach(dev); 1297 netif_start_queue(dev); 1298 } 1299 return flexcan_chip_enable(priv); 1300} 1301 1302static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume); 1303 1304static struct platform_driver flexcan_driver = { 1305 .driver = { 1306 .name = DRV_NAME, 1307 .pm = &flexcan_pm_ops, 1308 .of_match_table = flexcan_of_match, 1309 }, 1310 .probe = flexcan_probe, 1311 .remove = flexcan_remove, 1312 .id_table = flexcan_id_table, 1313}; 1314 1315module_platform_driver(flexcan_driver); 1316 1317MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 1318 "Marc Kleine-Budde <kernel@pengutronix.de>"); 1319MODULE_LICENSE("GPL v2"); 1320MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 1321