1/*
2 * Broadcom GENET MDIO routines
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11
12#include <linux/types.h>
13#include <linux/delay.h>
14#include <linux/wait.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/bitops.h>
18#include <linux/netdevice.h>
19#include <linux/platform_device.h>
20#include <linux/phy.h>
21#include <linux/phy_fixed.h>
22#include <linux/brcmphy.h>
23#include <linux/of.h>
24#include <linux/of_net.h>
25#include <linux/of_mdio.h>
26#include <linux/platform_data/bcmgenet.h>
27
28#include "bcmgenet.h"
29
30/* read a value from the MII */
31static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
32{
33	int ret;
34	struct net_device *dev = bus->priv;
35	struct bcmgenet_priv *priv = netdev_priv(dev);
36	u32 reg;
37
38	bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
39			     (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
40	/* Start MDIO transaction*/
41	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
42	reg |= MDIO_START_BUSY;
43	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
44	wait_event_timeout(priv->wq,
45			   !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
46			   & MDIO_START_BUSY),
47			   HZ / 100);
48	ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
49
50	if (ret & MDIO_READ_FAIL)
51		return -EIO;
52
53	return ret & 0xffff;
54}
55
56/* write a value to the MII */
57static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
58			      int location, u16 val)
59{
60	struct net_device *dev = bus->priv;
61	struct bcmgenet_priv *priv = netdev_priv(dev);
62	u32 reg;
63
64	bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
65			     (location << MDIO_REG_SHIFT) | (0xffff & val)),
66			     UMAC_MDIO_CMD);
67	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
68	reg |= MDIO_START_BUSY;
69	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
70	wait_event_timeout(priv->wq,
71			   !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
72			   MDIO_START_BUSY),
73			   HZ / 100);
74
75	return 0;
76}
77
78/* setup netdev link state when PHY link status change and
79 * update UMAC and RGMII block when link up
80 */
81void bcmgenet_mii_setup(struct net_device *dev)
82{
83	struct bcmgenet_priv *priv = netdev_priv(dev);
84	struct phy_device *phydev = priv->phydev;
85	u32 reg, cmd_bits = 0;
86	bool status_changed = false;
87
88	if (priv->old_link != phydev->link) {
89		status_changed = true;
90		priv->old_link = phydev->link;
91	}
92
93	if (phydev->link) {
94		/* check speed/duplex/pause changes */
95		if (priv->old_speed != phydev->speed) {
96			status_changed = true;
97			priv->old_speed = phydev->speed;
98		}
99
100		if (priv->old_duplex != phydev->duplex) {
101			status_changed = true;
102			priv->old_duplex = phydev->duplex;
103		}
104
105		if (priv->old_pause != phydev->pause) {
106			status_changed = true;
107			priv->old_pause = phydev->pause;
108		}
109
110		/* done if nothing has changed */
111		if (!status_changed)
112			return;
113
114		/* speed */
115		if (phydev->speed == SPEED_1000)
116			cmd_bits = UMAC_SPEED_1000;
117		else if (phydev->speed == SPEED_100)
118			cmd_bits = UMAC_SPEED_100;
119		else
120			cmd_bits = UMAC_SPEED_10;
121		cmd_bits <<= CMD_SPEED_SHIFT;
122
123		/* duplex */
124		if (phydev->duplex != DUPLEX_FULL)
125			cmd_bits |= CMD_HD_EN;
126
127		/* pause capability */
128		if (!phydev->pause)
129			cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
130
131		/*
132		 * Program UMAC and RGMII block based on established
133		 * link speed, duplex, and pause. The speed set in
134		 * umac->cmd tell RGMII block which clock to use for
135		 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
136		 * Receive clock is provided by the PHY.
137		 */
138		reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
139		reg &= ~OOB_DISABLE;
140		reg |= RGMII_LINK;
141		bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
142
143		reg = bcmgenet_umac_readl(priv, UMAC_CMD);
144		reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
145			       CMD_HD_EN |
146			       CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
147		reg |= cmd_bits;
148		bcmgenet_umac_writel(priv, reg, UMAC_CMD);
149	} else {
150		/* done if nothing has changed */
151		if (!status_changed)
152			return;
153
154		/* needed for MoCA fixed PHY to reflect correct link status */
155		netif_carrier_off(dev);
156	}
157
158	phy_print_status(phydev);
159}
160
161void bcmgenet_mii_reset(struct net_device *dev)
162{
163	struct bcmgenet_priv *priv = netdev_priv(dev);
164
165	if (priv->phydev) {
166		phy_init_hw(priv->phydev);
167		phy_start_aneg(priv->phydev);
168	}
169}
170
171void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
172{
173	struct bcmgenet_priv *priv = netdev_priv(dev);
174	u32 reg = 0;
175
176	/* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
177	if (!GENET_IS_V4(priv))
178		return;
179
180	reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
181	if (enable) {
182		reg &= ~EXT_CK25_DIS;
183		bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
184		mdelay(1);
185
186		reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
187		reg |= EXT_GPHY_RESET;
188		bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
189		mdelay(1);
190
191		reg &= ~EXT_GPHY_RESET;
192	} else {
193		reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_GPHY_RESET;
194		bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
195		mdelay(1);
196		reg |= EXT_CK25_DIS;
197	}
198	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
199	udelay(60);
200}
201
202static void bcmgenet_internal_phy_setup(struct net_device *dev)
203{
204	struct bcmgenet_priv *priv = netdev_priv(dev);
205	u32 reg;
206
207	/* Power up PHY */
208	bcmgenet_phy_power_set(dev, true);
209	/* enable APD */
210	reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
211	reg |= EXT_PWR_DN_EN_LD;
212	bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
213	bcmgenet_mii_reset(dev);
214}
215
216static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
217{
218	u32 reg;
219
220	/* Speed settings are set in bcmgenet_mii_setup() */
221	reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
222	reg |= LED_ACT_SOURCE_MAC;
223	bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
224}
225
226int bcmgenet_mii_config(struct net_device *dev, bool init)
227{
228	struct bcmgenet_priv *priv = netdev_priv(dev);
229	struct phy_device *phydev = priv->phydev;
230	struct device *kdev = &priv->pdev->dev;
231	const char *phy_name = NULL;
232	u32 id_mode_dis = 0;
233	u32 port_ctrl;
234	u32 reg;
235
236	priv->ext_phy = !phy_is_internal(priv->phydev) &&
237			(priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
238
239	if (phy_is_internal(priv->phydev))
240		priv->phy_interface = PHY_INTERFACE_MODE_NA;
241
242	switch (priv->phy_interface) {
243	case PHY_INTERFACE_MODE_NA:
244	case PHY_INTERFACE_MODE_MOCA:
245		/* Irrespective of the actually configured PHY speed (100 or
246		 * 1000) GENETv4 only has an internal GPHY so we will just end
247		 * up masking the Gigabit features from what we support, not
248		 * switching to the EPHY
249		 */
250		if (GENET_IS_V4(priv))
251			port_ctrl = PORT_MODE_INT_GPHY;
252		else
253			port_ctrl = PORT_MODE_INT_EPHY;
254
255		bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
256
257		if (phy_is_internal(priv->phydev)) {
258			phy_name = "internal PHY";
259			bcmgenet_internal_phy_setup(dev);
260		} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
261			phy_name = "MoCA";
262			bcmgenet_moca_phy_setup(priv);
263		}
264		break;
265
266	case PHY_INTERFACE_MODE_MII:
267		phy_name = "external MII";
268		phydev->supported &= PHY_BASIC_FEATURES;
269		bcmgenet_sys_writel(priv,
270				    PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
271		break;
272
273	case PHY_INTERFACE_MODE_REVMII:
274		phy_name = "external RvMII";
275		/* of_mdiobus_register took care of reading the 'max-speed'
276		 * PHY property for us, effectively limiting the PHY supported
277		 * capabilities, use that knowledge to also configure the
278		 * Reverse MII interface correctly.
279		 */
280		if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
281				PHY_BASIC_FEATURES)
282			port_ctrl = PORT_MODE_EXT_RVMII_25;
283		else
284			port_ctrl = PORT_MODE_EXT_RVMII_50;
285		bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
286		break;
287
288	case PHY_INTERFACE_MODE_RGMII:
289		/* RGMII_NO_ID: TXC transitions at the same time as TXD
290		 *		(requires PCB or receiver-side delay)
291		 * RGMII:	Add 2ns delay on TXC (90 degree shift)
292		 *
293		 * ID is implicitly disabled for 100Mbps (RG)MII operation.
294		 */
295		id_mode_dis = BIT(16);
296		/* fall through */
297	case PHY_INTERFACE_MODE_RGMII_TXID:
298		if (id_mode_dis)
299			phy_name = "external RGMII (no delay)";
300		else
301			phy_name = "external RGMII (TX delay)";
302		bcmgenet_sys_writel(priv,
303				    PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
304		break;
305	default:
306		dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
307		return -EINVAL;
308	}
309
310	/* This is an external PHY (xMII), so we need to enable the RGMII
311	 * block for the interface to work
312	 */
313	if (priv->ext_phy) {
314		reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
315		reg |= RGMII_MODE_EN | id_mode_dis;
316		bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
317	}
318
319	if (init)
320		dev_info(kdev, "configuring instance for %s\n", phy_name);
321
322	return 0;
323}
324
325static int bcmgenet_mii_probe(struct net_device *dev)
326{
327	struct bcmgenet_priv *priv = netdev_priv(dev);
328	struct device_node *dn = priv->pdev->dev.of_node;
329	struct phy_device *phydev;
330	u32 phy_flags;
331	int ret;
332
333	/* Communicate the integrated PHY revision */
334	phy_flags = priv->gphy_rev;
335
336	/* Initialize link state variables that bcmgenet_mii_setup() uses */
337	priv->old_link = -1;
338	priv->old_speed = -1;
339	priv->old_duplex = -1;
340	priv->old_pause = -1;
341
342	if (dn) {
343		if (priv->phydev) {
344			pr_info("PHY already attached\n");
345			return 0;
346		}
347
348		/* In the case of a fixed PHY, the DT node associated
349		 * to the PHY is the Ethernet MAC DT node.
350		 */
351		if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
352			ret = of_phy_register_fixed_link(dn);
353			if (ret)
354				return ret;
355
356			priv->phy_dn = of_node_get(dn);
357		}
358
359		phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
360					phy_flags, priv->phy_interface);
361		if (!phydev) {
362			pr_err("could not attach to PHY\n");
363			return -ENODEV;
364		}
365	} else {
366		phydev = priv->phydev;
367		phydev->dev_flags = phy_flags;
368
369		ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
370					 priv->phy_interface);
371		if (ret) {
372			pr_err("could not attach to PHY\n");
373			return -ENODEV;
374		}
375	}
376
377	priv->phydev = phydev;
378
379	/* Configure port multiplexer based on what the probed PHY device since
380	 * reading the 'max-speed' property determines the maximum supported
381	 * PHY speed which is needed for bcmgenet_mii_config() to configure
382	 * things appropriately.
383	 */
384	ret = bcmgenet_mii_config(dev, true);
385	if (ret) {
386		phy_disconnect(priv->phydev);
387		return ret;
388	}
389
390	phydev->advertising = phydev->supported;
391
392	/* The internal PHY has its link interrupts routed to the
393	 * Ethernet MAC ISRs
394	 */
395	if (phy_is_internal(priv->phydev))
396		priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT;
397	else
398		priv->mii_bus->irq[phydev->addr] = PHY_POLL;
399
400	pr_info("attached PHY at address %d [%s]\n",
401		phydev->addr, phydev->drv->name);
402
403	return 0;
404}
405
406static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
407{
408	struct mii_bus *bus;
409
410	if (priv->mii_bus)
411		return 0;
412
413	priv->mii_bus = mdiobus_alloc();
414	if (!priv->mii_bus) {
415		pr_err("failed to allocate\n");
416		return -ENOMEM;
417	}
418
419	bus = priv->mii_bus;
420	bus->priv = priv->dev;
421	bus->name = "bcmgenet MII bus";
422	bus->parent = &priv->pdev->dev;
423	bus->read = bcmgenet_mii_read;
424	bus->write = bcmgenet_mii_write;
425	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
426		 priv->pdev->name, priv->pdev->id);
427
428	bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
429	if (!bus->irq) {
430		mdiobus_free(priv->mii_bus);
431		return -ENOMEM;
432	}
433
434	return 0;
435}
436
437static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
438{
439	struct device_node *dn = priv->pdev->dev.of_node;
440	struct device *kdev = &priv->pdev->dev;
441	struct device_node *mdio_dn;
442	char *compat;
443	int ret;
444
445	compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
446	if (!compat)
447		return -ENOMEM;
448
449	mdio_dn = of_find_compatible_node(dn, NULL, compat);
450	kfree(compat);
451	if (!mdio_dn) {
452		dev_err(kdev, "unable to find MDIO bus node\n");
453		return -ENODEV;
454	}
455
456	ret = of_mdiobus_register(priv->mii_bus, mdio_dn);
457	if (ret) {
458		dev_err(kdev, "failed to register MDIO bus\n");
459		return ret;
460	}
461
462	/* Fetch the PHY phandle */
463	priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
464
465	/* Get the link mode */
466	priv->phy_interface = of_get_phy_mode(dn);
467
468	return 0;
469}
470
471static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
472					  struct fixed_phy_status *status)
473{
474	if (dev && dev->phydev && status)
475		status->link = dev->phydev->link;
476
477	return 0;
478}
479
480static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
481{
482	struct device *kdev = &priv->pdev->dev;
483	struct bcmgenet_platform_data *pd = kdev->platform_data;
484	struct mii_bus *mdio = priv->mii_bus;
485	struct phy_device *phydev;
486	int ret;
487
488	if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
489		/*
490		 * Internal or external PHY with MDIO access
491		 */
492		if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
493			mdio->phy_mask = ~(1 << pd->phy_address);
494		else
495			mdio->phy_mask = 0;
496
497		ret = mdiobus_register(mdio);
498		if (ret) {
499			dev_err(kdev, "failed to register MDIO bus\n");
500			return ret;
501		}
502
503		if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
504			phydev = mdio->phy_map[pd->phy_address];
505		else
506			phydev = phy_find_first(mdio);
507
508		if (!phydev) {
509			dev_err(kdev, "failed to register PHY device\n");
510			mdiobus_unregister(mdio);
511			return -ENODEV;
512		}
513	} else {
514		/*
515		 * MoCA port or no MDIO access.
516		 * Use fixed PHY to represent the link layer.
517		 */
518		struct fixed_phy_status fphy_status = {
519			.link = 1,
520			.speed = pd->phy_speed,
521			.duplex = pd->phy_duplex,
522			.pause = 0,
523			.asym_pause = 0,
524		};
525
526		phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
527		if (!phydev || IS_ERR(phydev)) {
528			dev_err(kdev, "failed to register fixed PHY device\n");
529			return -ENODEV;
530		}
531
532		if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) {
533			ret = fixed_phy_set_link_update(
534				phydev, bcmgenet_fixed_phy_link_update);
535			if (!ret)
536				phydev->link = 0;
537		}
538	}
539
540	priv->phydev = phydev;
541	priv->phy_interface = pd->phy_interface;
542
543	return 0;
544}
545
546static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
547{
548	struct device_node *dn = priv->pdev->dev.of_node;
549
550	if (dn)
551		return bcmgenet_mii_of_init(priv);
552	else
553		return bcmgenet_mii_pd_init(priv);
554}
555
556int bcmgenet_mii_init(struct net_device *dev)
557{
558	struct bcmgenet_priv *priv = netdev_priv(dev);
559	int ret;
560
561	ret = bcmgenet_mii_alloc(priv);
562	if (ret)
563		return ret;
564
565	ret = bcmgenet_mii_bus_init(priv);
566	if (ret)
567		goto out_free;
568
569	ret = bcmgenet_mii_probe(dev);
570	if (ret)
571		goto out;
572
573	return 0;
574
575out:
576	of_node_put(priv->phy_dn);
577	mdiobus_unregister(priv->mii_bus);
578out_free:
579	kfree(priv->mii_bus->irq);
580	mdiobus_free(priv->mii_bus);
581	return ret;
582}
583
584void bcmgenet_mii_exit(struct net_device *dev)
585{
586	struct bcmgenet_priv *priv = netdev_priv(dev);
587
588	of_node_put(priv->phy_dn);
589	mdiobus_unregister(priv->mii_bus);
590	kfree(priv->mii_bus->irq);
591	mdiobus_free(priv->mii_bus);
592}
593