1/* 2 * Linux network driver for QLogic BR-series Converged Network Adapter. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License (GPL) Version 2 as 6 * published by the Free Software Foundation 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 * General Public License for more details. 12 */ 13/* 14 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. 15 * Copyright (c) 2014-2015 QLogic Corporation 16 * All rights reserved 17 * www.qlogic.com 18 */ 19#ifndef __BFI_H__ 20#define __BFI_H__ 21 22#include "bfa_defs.h" 23 24#pragma pack(1) 25 26/* BFI FW image type */ 27#define BFI_FLASH_CHUNK_SZ 256 /*!< Flash chunk size */ 28#define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32)) 29#define BFI_FLASH_IMAGE_SZ 0x100000 30 31/* Msg header common to all msgs */ 32struct bfi_mhdr { 33 u8 msg_class; /*!< @ref enum bfi_mclass */ 34 u8 msg_id; /*!< msg opcode with in the class */ 35 union { 36 struct { 37 u8 qid; 38 u8 fn_lpu; /*!< msg destination */ 39 } h2i; 40 u16 i2htok; /*!< token in msgs to host */ 41 } mtag; 42}; 43 44#define bfi_fn_lpu(__fn, __lpu) ((__fn) << 1 | (__lpu)) 45#define bfi_mhdr_2_fn(_mh) ((_mh)->mtag.h2i.fn_lpu >> 1) 46#define bfi_mhdr_2_qid(_mh) ((_mh)->mtag.h2i.qid) 47 48#define bfi_h2i_set(_mh, _mc, _op, _fn_lpu) do { \ 49 (_mh).msg_class = (_mc); \ 50 (_mh).msg_id = (_op); \ 51 (_mh).mtag.h2i.fn_lpu = (_fn_lpu); \ 52} while (0) 53 54#define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \ 55 (_mh).msg_class = (_mc); \ 56 (_mh).msg_id = (_op); \ 57 (_mh).mtag.i2htok = (_i2htok); \ 58} while (0) 59 60/* 61 * Message opcodes: 0-127 to firmware, 128-255 to host 62 */ 63#define BFI_I2H_OPCODE_BASE 128 64#define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE) 65 66/**************************************************************************** 67 * 68 * Scatter Gather Element and Page definition 69 * 70 **************************************************************************** 71 */ 72 73/* DMA addresses */ 74union bfi_addr_u { 75 struct { 76 u32 addr_lo; 77 u32 addr_hi; 78 } a32; 79}; 80 81/* Generic DMA addr-len pair. */ 82struct bfi_alen { 83 union bfi_addr_u al_addr; /* DMA addr of buffer */ 84 u32 al_len; /* length of buffer */ 85}; 86 87/* 88 * Large Message structure - 128 Bytes size Msgs 89 */ 90#define BFI_LMSG_SZ 128 91#define BFI_LMSG_PL_WSZ \ 92 ((BFI_LMSG_SZ - sizeof(struct bfi_mhdr)) / 4) 93 94/* Mailbox message structure */ 95#define BFI_MBMSG_SZ 7 96struct bfi_mbmsg { 97 struct bfi_mhdr mh; 98 u32 pl[BFI_MBMSG_SZ]; 99}; 100 101/* Supported PCI function class codes (personality) */ 102enum bfi_pcifn_class { 103 BFI_PCIFN_CLASS_FC = 0x0c04, 104 BFI_PCIFN_CLASS_ETH = 0x0200, 105}; 106 107/* Message Classes */ 108enum bfi_mclass { 109 BFI_MC_IOC = 1, /*!< IO Controller (IOC) */ 110 BFI_MC_DIAG = 2, /*!< Diagnostic Msgs */ 111 BFI_MC_FLASH = 3, /*!< Flash message class */ 112 BFI_MC_CEE = 4, /*!< CEE */ 113 BFI_MC_FCPORT = 5, /*!< FC port */ 114 BFI_MC_IOCFC = 6, /*!< FC - IO Controller (IOC) */ 115 BFI_MC_LL = 7, /*!< Link Layer */ 116 BFI_MC_UF = 8, /*!< Unsolicited frame receive */ 117 BFI_MC_FCXP = 9, /*!< FC Transport */ 118 BFI_MC_LPS = 10, /*!< lport fc login services */ 119 BFI_MC_RPORT = 11, /*!< Remote port */ 120 BFI_MC_ITNIM = 12, /*!< I-T nexus (Initiator mode) */ 121 BFI_MC_IOIM_READ = 13, /*!< read IO (Initiator mode) */ 122 BFI_MC_IOIM_WRITE = 14, /*!< write IO (Initiator mode) */ 123 BFI_MC_IOIM_IO = 15, /*!< IO (Initiator mode) */ 124 BFI_MC_IOIM = 16, /*!< IO (Initiator mode) */ 125 BFI_MC_IOIM_IOCOM = 17, /*!< good IO completion */ 126 BFI_MC_TSKIM = 18, /*!< Initiator Task management */ 127 BFI_MC_SBOOT = 19, /*!< SAN boot services */ 128 BFI_MC_IPFC = 20, /*!< IP over FC Msgs */ 129 BFI_MC_PORT = 21, /*!< Physical port */ 130 BFI_MC_SFP = 22, /*!< SFP module */ 131 BFI_MC_MSGQ = 23, /*!< MSGQ */ 132 BFI_MC_ENET = 24, /*!< ENET commands/responses */ 133 BFI_MC_PHY = 25, /*!< External PHY message class */ 134 BFI_MC_NBOOT = 26, /*!< Network Boot */ 135 BFI_MC_TIO_READ = 27, /*!< read IO (Target mode) */ 136 BFI_MC_TIO_WRITE = 28, /*!< write IO (Target mode) */ 137 BFI_MC_TIO_DATA_XFERED = 29, /*!< ds transferred (target mode) */ 138 BFI_MC_TIO_IO = 30, /*!< IO (Target mode) */ 139 BFI_MC_TIO = 31, /*!< IO (target mode) */ 140 BFI_MC_MFG = 32, /*!< MFG/ASIC block commands */ 141 BFI_MC_EDMA = 33, /*!< EDMA copy commands */ 142 BFI_MC_MAX = 34 143}; 144 145#define BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */ 146 147#define BFI_FWBOOT_ENV_OS 0 148 149/*---------------------------------------------------------------------- 150 * IOC 151 *---------------------------------------------------------------------- 152 */ 153 154/* Different asic generations */ 155enum bfi_asic_gen { 156 BFI_ASIC_GEN_CB = 1, 157 BFI_ASIC_GEN_CT = 2, 158 BFI_ASIC_GEN_CT2 = 3, 159}; 160 161enum bfi_asic_mode { 162 BFI_ASIC_MODE_FC = 1, /* FC up to 8G speed */ 163 BFI_ASIC_MODE_FC16 = 2, /* FC up to 16G speed */ 164 BFI_ASIC_MODE_ETH = 3, /* Ethernet ports */ 165 BFI_ASIC_MODE_COMBO = 4, /* FC 16G and Ethernet 10G port */ 166}; 167 168enum bfi_ioc_h2i_msgs { 169 BFI_IOC_H2I_ENABLE_REQ = 1, 170 BFI_IOC_H2I_DISABLE_REQ = 2, 171 BFI_IOC_H2I_GETATTR_REQ = 3, 172 BFI_IOC_H2I_DBG_SYNC = 4, 173 BFI_IOC_H2I_DBG_DUMP = 5, 174}; 175 176enum bfi_ioc_i2h_msgs { 177 BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1), 178 BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2), 179 BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3), 180 BFI_IOC_I2H_HBEAT = BFA_I2HM(4), 181}; 182 183/* BFI_IOC_H2I_GETATTR_REQ message */ 184struct bfi_ioc_getattr_req { 185 struct bfi_mhdr mh; 186 union bfi_addr_u attr_addr; 187}; 188 189struct bfi_ioc_attr { 190 u64 mfg_pwwn; /*!< Mfg port wwn */ 191 u64 mfg_nwwn; /*!< Mfg node wwn */ 192 mac_t mfg_mac; /*!< Mfg mac */ 193 u8 port_mode; /* enum bfi_port_mode */ 194 u8 rsvd_a; 195 u64 pwwn; 196 u64 nwwn; 197 mac_t mac; /*!< PBC or Mfg mac */ 198 u16 rsvd_b; 199 mac_t fcoe_mac; 200 u16 rsvd_c; 201 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)]; 202 u8 pcie_gen; 203 u8 pcie_lanes_orig; 204 u8 pcie_lanes; 205 u8 rx_bbcredit; /*!< receive buffer credits */ 206 u32 adapter_prop; /*!< adapter properties */ 207 u16 maxfrsize; /*!< max receive frame size */ 208 char asic_rev; 209 u8 rsvd_d; 210 char fw_version[BFA_VERSION_LEN]; 211 char optrom_version[BFA_VERSION_LEN]; 212 struct bfa_mfg_vpd vpd; 213 u32 card_type; /*!< card type */ 214}; 215 216/* BFI_IOC_I2H_GETATTR_REPLY message */ 217struct bfi_ioc_getattr_reply { 218 struct bfi_mhdr mh; /*!< Common msg header */ 219 u8 status; /*!< cfg reply status */ 220 u8 rsvd[3]; 221}; 222 223/* Firmware memory page offsets */ 224#define BFI_IOC_SMEM_PG0_CB (0x40) 225#define BFI_IOC_SMEM_PG0_CT (0x180) 226 227/* Firmware statistic offset */ 228#define BFI_IOC_FWSTATS_OFF (0x6B40) 229#define BFI_IOC_FWSTATS_SZ (4096) 230 231/* Firmware trace offset */ 232#define BFI_IOC_TRC_OFF (0x4b00) 233#define BFI_IOC_TRC_ENTS 256 234#define BFI_IOC_TRC_ENT_SZ 16 235#define BFI_IOC_TRC_HDR_SZ 32 236 237#define BFI_IOC_FW_SIGNATURE (0xbfadbfad) 238#define BFI_IOC_FW_INV_SIGN (0xdeaddead) 239#define BFI_IOC_MD5SUM_SZ 4 240 241struct bfi_ioc_fwver { 242#ifdef __BIG_ENDIAN 243 u8 patch; 244 u8 maint; 245 u8 minor; 246 u8 major; 247 u8 rsvd[2]; 248 u8 build; 249 u8 phase; 250#else 251 u8 major; 252 u8 minor; 253 u8 maint; 254 u8 patch; 255 u8 phase; 256 u8 build; 257 u8 rsvd[2]; 258#endif 259}; 260 261struct bfi_ioc_image_hdr { 262 u32 signature; /*!< constant signature */ 263 u8 asic_gen; /*!< asic generation */ 264 u8 asic_mode; 265 u8 port0_mode; /*!< device mode for port 0 */ 266 u8 port1_mode; /*!< device mode for port 1 */ 267 u32 exec; /*!< exec vector */ 268 u32 bootenv; /*!< firmware boot env */ 269 u32 rsvd_b[2]; 270 struct bfi_ioc_fwver fwver; 271 u32 md5sum[BFI_IOC_MD5SUM_SZ]; 272}; 273 274enum bfi_ioc_img_ver_cmp { 275 BFI_IOC_IMG_VER_INCOMP, 276 BFI_IOC_IMG_VER_OLD, 277 BFI_IOC_IMG_VER_SAME, 278 BFI_IOC_IMG_VER_BETTER 279}; 280 281#define BFI_FWBOOT_DEVMODE_OFF 4 282#define BFI_FWBOOT_TYPE_OFF 8 283#define BFI_FWBOOT_ENV_OFF 12 284#define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \ 285 (((u32)(__asic_gen)) << 24 | \ 286 ((u32)(__asic_mode)) << 16 | \ 287 ((u32)(__p0_mode)) << 8 | \ 288 ((u32)(__p1_mode))) 289 290enum bfi_fwboot_type { 291 BFI_FWBOOT_TYPE_NORMAL = 0, 292 BFI_FWBOOT_TYPE_FLASH = 1, 293 BFI_FWBOOT_TYPE_MEMTEST = 2, 294}; 295 296enum bfi_port_mode { 297 BFI_PORT_MODE_FC = 1, 298 BFI_PORT_MODE_ETH = 2, 299}; 300 301struct bfi_ioc_hbeat { 302 struct bfi_mhdr mh; /*!< common msg header */ 303 u32 hb_count; /*!< current heart beat count */ 304}; 305 306/* IOC hardware/firmware state */ 307enum bfi_ioc_state { 308 BFI_IOC_UNINIT = 0, /*!< not initialized */ 309 BFI_IOC_INITING = 1, /*!< h/w is being initialized */ 310 BFI_IOC_HWINIT = 2, /*!< h/w is initialized */ 311 BFI_IOC_CFG = 3, /*!< IOC configuration in progress */ 312 BFI_IOC_OP = 4, /*!< IOC is operational */ 313 BFI_IOC_DISABLING = 5, /*!< IOC is being disabled */ 314 BFI_IOC_DISABLED = 6, /*!< IOC is disabled */ 315 BFI_IOC_CFG_DISABLED = 7, /*!< IOC is being disabled;transient */ 316 BFI_IOC_FAIL = 8, /*!< IOC heart-beat failure */ 317 BFI_IOC_MEMTEST = 9, /*!< IOC is doing memtest */ 318}; 319 320#define BFI_IOC_ENDIAN_SIG 0x12345678 321 322enum { 323 BFI_ADAPTER_TYPE_FC = 0x01, /*!< FC adapters */ 324 BFI_ADAPTER_TYPE_MK = 0x0f0000, /*!< adapter type mask */ 325 BFI_ADAPTER_TYPE_SH = 16, /*!< adapter type shift */ 326 BFI_ADAPTER_NPORTS_MK = 0xff00, /*!< number of ports mask */ 327 BFI_ADAPTER_NPORTS_SH = 8, /*!< number of ports shift */ 328 BFI_ADAPTER_SPEED_MK = 0xff, /*!< adapter speed mask */ 329 BFI_ADAPTER_SPEED_SH = 0, /*!< adapter speed shift */ 330 BFI_ADAPTER_PROTO = 0x100000, /*!< prototype adapaters */ 331 BFI_ADAPTER_TTV = 0x200000, /*!< TTV debug capable */ 332 BFI_ADAPTER_UNSUPP = 0x400000, /*!< unknown adapter type */ 333}; 334 335#define BFI_ADAPTER_GETP(__prop, __adap_prop) \ 336 (((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >> \ 337 BFI_ADAPTER_ ## __prop ## _SH) 338#define BFI_ADAPTER_SETP(__prop, __val) \ 339 ((__val) << BFI_ADAPTER_ ## __prop ## _SH) 340#define BFI_ADAPTER_IS_PROTO(__adap_type) \ 341 ((__adap_type) & BFI_ADAPTER_PROTO) 342#define BFI_ADAPTER_IS_TTV(__adap_type) \ 343 ((__adap_type) & BFI_ADAPTER_TTV) 344#define BFI_ADAPTER_IS_UNSUPP(__adap_type) \ 345 ((__adap_type) & BFI_ADAPTER_UNSUPP) 346#define BFI_ADAPTER_IS_SPECIAL(__adap_type) \ 347 ((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO | \ 348 BFI_ADAPTER_UNSUPP)) 349 350/* BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages */ 351struct bfi_ioc_ctrl_req { 352 struct bfi_mhdr mh; 353 u16 clscode; 354 u16 rsvd; 355 u32 tv_sec; 356}; 357 358/* BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages */ 359struct bfi_ioc_ctrl_reply { 360 struct bfi_mhdr mh; /*!< Common msg header */ 361 u8 status; /*!< enable/disable status */ 362 u8 port_mode; /*!< enum bfa_mode */ 363 u8 cap_bm; /*!< capability bit mask */ 364 u8 rsvd; 365}; 366 367#define BFI_IOC_MSGSZ 8 368/* H2I Messages */ 369union bfi_ioc_h2i_msg_u { 370 struct bfi_mhdr mh; 371 struct bfi_ioc_ctrl_req enable_req; 372 struct bfi_ioc_ctrl_req disable_req; 373 struct bfi_ioc_getattr_req getattr_req; 374 u32 mboxmsg[BFI_IOC_MSGSZ]; 375}; 376 377/* I2H Messages */ 378union bfi_ioc_i2h_msg_u { 379 struct bfi_mhdr mh; 380 struct bfi_ioc_ctrl_reply fw_event; 381 u32 mboxmsg[BFI_IOC_MSGSZ]; 382}; 383 384/*---------------------------------------------------------------------- 385 * MSGQ 386 *---------------------------------------------------------------------- 387 */ 388 389enum bfi_msgq_h2i_msgs { 390 BFI_MSGQ_H2I_INIT_REQ = 1, 391 BFI_MSGQ_H2I_DOORBELL_PI = 2, 392 BFI_MSGQ_H2I_DOORBELL_CI = 3, 393 BFI_MSGQ_H2I_CMDQ_COPY_RSP = 4, 394}; 395 396enum bfi_msgq_i2h_msgs { 397 BFI_MSGQ_I2H_INIT_RSP = BFA_I2HM(BFI_MSGQ_H2I_INIT_REQ), 398 BFI_MSGQ_I2H_DOORBELL_PI = BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_PI), 399 BFI_MSGQ_I2H_DOORBELL_CI = BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_CI), 400 BFI_MSGQ_I2H_CMDQ_COPY_REQ = BFA_I2HM(BFI_MSGQ_H2I_CMDQ_COPY_RSP), 401}; 402 403/* Messages(commands/responsed/AENS will have the following header */ 404struct bfi_msgq_mhdr { 405 u8 msg_class; 406 u8 msg_id; 407 u16 msg_token; 408 u16 num_entries; 409 u8 enet_id; 410 u8 rsvd[1]; 411}; 412 413#define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do { \ 414 (_mh).msg_class = (_mc); \ 415 (_mh).msg_id = (_mid); \ 416 (_mh).msg_token = (_tok); \ 417 (_mh).enet_id = (_enet_id); \ 418} while (0) 419 420/* 421 * Mailbox for messaging interface 422 */ 423#define BFI_MSGQ_CMD_ENTRY_SIZE (64) /* TBD */ 424#define BFI_MSGQ_RSP_ENTRY_SIZE (64) /* TBD */ 425 426#define bfi_msgq_num_cmd_entries(_size) \ 427 (((_size) + BFI_MSGQ_CMD_ENTRY_SIZE - 1) / BFI_MSGQ_CMD_ENTRY_SIZE) 428 429struct bfi_msgq { 430 union bfi_addr_u addr; 431 u16 q_depth; /* Total num of entries in the queue */ 432 u8 rsvd[2]; 433}; 434 435/* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */ 436struct bfi_msgq_cfg_req { 437 struct bfi_mhdr mh; 438 struct bfi_msgq cmdq; 439 struct bfi_msgq rspq; 440}; 441 442/* BFI_ENET_MSGQ_CFG_RSP */ 443struct bfi_msgq_cfg_rsp { 444 struct bfi_mhdr mh; 445 u8 cmd_status; 446 u8 rsvd[3]; 447}; 448 449/* BFI_MSGQ_H2I_DOORBELL */ 450struct bfi_msgq_h2i_db { 451 struct bfi_mhdr mh; 452 union { 453 u16 cmdq_pi; 454 u16 rspq_ci; 455 } idx; 456}; 457 458/* BFI_MSGQ_I2H_DOORBELL */ 459struct bfi_msgq_i2h_db { 460 struct bfi_mhdr mh; 461 union { 462 u16 rspq_pi; 463 u16 cmdq_ci; 464 } idx; 465}; 466 467#define BFI_CMD_COPY_SZ 28 468 469/* BFI_MSGQ_H2I_CMD_COPY_RSP */ 470struct bfi_msgq_h2i_cmdq_copy_rsp { 471 struct bfi_mhdr mh; 472 u8 data[BFI_CMD_COPY_SZ]; 473}; 474 475/* BFI_MSGQ_I2H_CMD_COPY_REQ */ 476struct bfi_msgq_i2h_cmdq_copy_req { 477 struct bfi_mhdr mh; 478 u16 offset; 479 u16 len; 480}; 481 482/* 483 * FLASH module specific 484 */ 485enum bfi_flash_h2i_msgs { 486 BFI_FLASH_H2I_QUERY_REQ = 1, 487 BFI_FLASH_H2I_ERASE_REQ = 2, 488 BFI_FLASH_H2I_WRITE_REQ = 3, 489 BFI_FLASH_H2I_READ_REQ = 4, 490 BFI_FLASH_H2I_BOOT_VER_REQ = 5, 491}; 492 493enum bfi_flash_i2h_msgs { 494 BFI_FLASH_I2H_QUERY_RSP = BFA_I2HM(1), 495 BFI_FLASH_I2H_ERASE_RSP = BFA_I2HM(2), 496 BFI_FLASH_I2H_WRITE_RSP = BFA_I2HM(3), 497 BFI_FLASH_I2H_READ_RSP = BFA_I2HM(4), 498 BFI_FLASH_I2H_BOOT_VER_RSP = BFA_I2HM(5), 499 BFI_FLASH_I2H_EVENT = BFA_I2HM(127), 500}; 501 502/* 503 * Flash query request 504 */ 505struct bfi_flash_query_req { 506 struct bfi_mhdr mh; /* Common msg header */ 507 struct bfi_alen alen; 508}; 509 510/* 511 * Flash write request 512 */ 513struct bfi_flash_write_req { 514 struct bfi_mhdr mh; /* Common msg header */ 515 struct bfi_alen alen; 516 u32 type; /* partition type */ 517 u8 instance; /* partition instance */ 518 u8 last; 519 u8 rsv[2]; 520 u32 offset; 521 u32 length; 522}; 523 524/* 525 * Flash read request 526 */ 527struct bfi_flash_read_req { 528 struct bfi_mhdr mh; /* Common msg header */ 529 u32 type; /* partition type */ 530 u8 instance; /* partition instance */ 531 u8 rsv[3]; 532 u32 offset; 533 u32 length; 534 struct bfi_alen alen; 535}; 536 537/* 538 * Flash query response 539 */ 540struct bfi_flash_query_rsp { 541 struct bfi_mhdr mh; /* Common msg header */ 542 u32 status; 543}; 544 545/* 546 * Flash read response 547 */ 548struct bfi_flash_read_rsp { 549 struct bfi_mhdr mh; /* Common msg header */ 550 u32 type; /* partition type */ 551 u8 instance; /* partition instance */ 552 u8 rsv[3]; 553 u32 status; 554 u32 length; 555}; 556 557/* 558 * Flash write response 559 */ 560struct bfi_flash_write_rsp { 561 struct bfi_mhdr mh; /* Common msg header */ 562 u32 type; /* partition type */ 563 u8 instance; /* partition instance */ 564 u8 rsv[3]; 565 u32 status; 566 u32 length; 567}; 568 569#pragma pack() 570 571#endif /* __BFI_H__ */ 572