1/* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22#ifndef _E1000_HW_H_ 23#define _E1000_HW_H_ 24 25#include "regs.h" 26#include "defines.h" 27 28struct e1000_hw; 29 30#define E1000_DEV_ID_82571EB_COPPER 0x105E 31#define E1000_DEV_ID_82571EB_FIBER 0x105F 32#define E1000_DEV_ID_82571EB_SERDES 0x1060 33#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 34#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 35#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 36#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 37#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 38#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 39#define E1000_DEV_ID_82572EI_COPPER 0x107D 40#define E1000_DEV_ID_82572EI_FIBER 0x107E 41#define E1000_DEV_ID_82572EI_SERDES 0x107F 42#define E1000_DEV_ID_82572EI 0x10B9 43#define E1000_DEV_ID_82573E 0x108B 44#define E1000_DEV_ID_82573E_IAMT 0x108C 45#define E1000_DEV_ID_82573L 0x109A 46#define E1000_DEV_ID_82574L 0x10D3 47#define E1000_DEV_ID_82574LA 0x10F6 48#define E1000_DEV_ID_82583V 0x150C 49#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 50#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 51#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 52#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 53#define E1000_DEV_ID_ICH8_82567V_3 0x1501 54#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 55#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 56#define E1000_DEV_ID_ICH8_IGP_C 0x104B 57#define E1000_DEV_ID_ICH8_IFE 0x104C 58#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 59#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 60#define E1000_DEV_ID_ICH8_IGP_M 0x104D 61#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 62#define E1000_DEV_ID_ICH9_BM 0x10E5 63#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 64#define E1000_DEV_ID_ICH9_IGP_M 0x10BF 65#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 66#define E1000_DEV_ID_ICH9_IGP_C 0x294C 67#define E1000_DEV_ID_ICH9_IFE 0x10C0 68#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 69#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 70#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 71#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 72#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 73#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 74#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 75#define E1000_DEV_ID_ICH10_D_BM_V 0x1525 76#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 77#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 78#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 79#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 80#define E1000_DEV_ID_PCH2_LV_LM 0x1502 81#define E1000_DEV_ID_PCH2_LV_V 0x1503 82#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 83#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 84#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 85#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 86#define E1000_DEV_ID_PCH_I218_LM2 0x15A0 87#define E1000_DEV_ID_PCH_I218_V2 0x15A1 88#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 89#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 90#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */ 91#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */ 92#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */ 93#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */ 94 95#define E1000_REVISION_4 4 96 97#define E1000_FUNC_1 1 98 99#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 100#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 101 102enum e1000_mac_type { 103 e1000_82571, 104 e1000_82572, 105 e1000_82573, 106 e1000_82574, 107 e1000_82583, 108 e1000_80003es2lan, 109 e1000_ich8lan, 110 e1000_ich9lan, 111 e1000_ich10lan, 112 e1000_pchlan, 113 e1000_pch2lan, 114 e1000_pch_lpt, 115 e1000_pch_spt, 116}; 117 118enum e1000_media_type { 119 e1000_media_type_unknown = 0, 120 e1000_media_type_copper = 1, 121 e1000_media_type_fiber = 2, 122 e1000_media_type_internal_serdes = 3, 123 e1000_num_media_types 124}; 125 126enum e1000_nvm_type { 127 e1000_nvm_unknown = 0, 128 e1000_nvm_none, 129 e1000_nvm_eeprom_spi, 130 e1000_nvm_flash_hw, 131 e1000_nvm_flash_sw 132}; 133 134enum e1000_nvm_override { 135 e1000_nvm_override_none = 0, 136 e1000_nvm_override_spi_small, 137 e1000_nvm_override_spi_large 138}; 139 140enum e1000_phy_type { 141 e1000_phy_unknown = 0, 142 e1000_phy_none, 143 e1000_phy_m88, 144 e1000_phy_igp, 145 e1000_phy_igp_2, 146 e1000_phy_gg82563, 147 e1000_phy_igp_3, 148 e1000_phy_ife, 149 e1000_phy_bm, 150 e1000_phy_82578, 151 e1000_phy_82577, 152 e1000_phy_82579, 153 e1000_phy_i217, 154}; 155 156enum e1000_bus_width { 157 e1000_bus_width_unknown = 0, 158 e1000_bus_width_pcie_x1, 159 e1000_bus_width_pcie_x2, 160 e1000_bus_width_pcie_x4 = 4, 161 e1000_bus_width_pcie_x8 = 8, 162 e1000_bus_width_32, 163 e1000_bus_width_64, 164 e1000_bus_width_reserved 165}; 166 167enum e1000_1000t_rx_status { 168 e1000_1000t_rx_status_not_ok = 0, 169 e1000_1000t_rx_status_ok, 170 e1000_1000t_rx_status_undefined = 0xFF 171}; 172 173enum e1000_rev_polarity { 174 e1000_rev_polarity_normal = 0, 175 e1000_rev_polarity_reversed, 176 e1000_rev_polarity_undefined = 0xFF 177}; 178 179enum e1000_fc_mode { 180 e1000_fc_none = 0, 181 e1000_fc_rx_pause, 182 e1000_fc_tx_pause, 183 e1000_fc_full, 184 e1000_fc_default = 0xFF 185}; 186 187enum e1000_ms_type { 188 e1000_ms_hw_default = 0, 189 e1000_ms_force_master, 190 e1000_ms_force_slave, 191 e1000_ms_auto 192}; 193 194enum e1000_smart_speed { 195 e1000_smart_speed_default = 0, 196 e1000_smart_speed_on, 197 e1000_smart_speed_off 198}; 199 200enum e1000_serdes_link_state { 201 e1000_serdes_link_down = 0, 202 e1000_serdes_link_autoneg_progress, 203 e1000_serdes_link_autoneg_complete, 204 e1000_serdes_link_forced_up 205}; 206 207/* Receive Descriptor - Extended */ 208union e1000_rx_desc_extended { 209 struct { 210 __le64 buffer_addr; 211 __le64 reserved; 212 } read; 213 struct { 214 struct { 215 __le32 mrq; /* Multiple Rx Queues */ 216 union { 217 __le32 rss; /* RSS Hash */ 218 struct { 219 __le16 ip_id; /* IP id */ 220 __le16 csum; /* Packet Checksum */ 221 } csum_ip; 222 } hi_dword; 223 } lower; 224 struct { 225 __le32 status_error; /* ext status/error */ 226 __le16 length; 227 __le16 vlan; /* VLAN tag */ 228 } upper; 229 } wb; /* writeback */ 230}; 231 232#define MAX_PS_BUFFERS 4 233 234/* Number of packet split data buffers (not including the header buffer) */ 235#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 236 237/* Receive Descriptor - Packet Split */ 238union e1000_rx_desc_packet_split { 239 struct { 240 /* one buffer for protocol header(s), three data buffers */ 241 __le64 buffer_addr[MAX_PS_BUFFERS]; 242 } read; 243 struct { 244 struct { 245 __le32 mrq; /* Multiple Rx Queues */ 246 union { 247 __le32 rss; /* RSS Hash */ 248 struct { 249 __le16 ip_id; /* IP id */ 250 __le16 csum; /* Packet Checksum */ 251 } csum_ip; 252 } hi_dword; 253 } lower; 254 struct { 255 __le32 status_error; /* ext status/error */ 256 __le16 length0; /* length of buffer 0 */ 257 __le16 vlan; /* VLAN tag */ 258 } middle; 259 struct { 260 __le16 header_status; 261 /* length of buffers 1-3 */ 262 __le16 length[PS_PAGE_BUFFERS]; 263 } upper; 264 __le64 reserved; 265 } wb; /* writeback */ 266}; 267 268/* Transmit Descriptor */ 269struct e1000_tx_desc { 270 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 271 union { 272 __le32 data; 273 struct { 274 __le16 length; /* Data buffer length */ 275 u8 cso; /* Checksum offset */ 276 u8 cmd; /* Descriptor control */ 277 } flags; 278 } lower; 279 union { 280 __le32 data; 281 struct { 282 u8 status; /* Descriptor status */ 283 u8 css; /* Checksum start */ 284 __le16 special; 285 } fields; 286 } upper; 287}; 288 289/* Offload Context Descriptor */ 290struct e1000_context_desc { 291 union { 292 __le32 ip_config; 293 struct { 294 u8 ipcss; /* IP checksum start */ 295 u8 ipcso; /* IP checksum offset */ 296 __le16 ipcse; /* IP checksum end */ 297 } ip_fields; 298 } lower_setup; 299 union { 300 __le32 tcp_config; 301 struct { 302 u8 tucss; /* TCP checksum start */ 303 u8 tucso; /* TCP checksum offset */ 304 __le16 tucse; /* TCP checksum end */ 305 } tcp_fields; 306 } upper_setup; 307 __le32 cmd_and_length; 308 union { 309 __le32 data; 310 struct { 311 u8 status; /* Descriptor status */ 312 u8 hdr_len; /* Header length */ 313 __le16 mss; /* Maximum segment size */ 314 } fields; 315 } tcp_seg_setup; 316}; 317 318/* Offload data descriptor */ 319struct e1000_data_desc { 320 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 321 union { 322 __le32 data; 323 struct { 324 __le16 length; /* Data buffer length */ 325 u8 typ_len_ext; 326 u8 cmd; 327 } flags; 328 } lower; 329 union { 330 __le32 data; 331 struct { 332 u8 status; /* Descriptor status */ 333 u8 popts; /* Packet Options */ 334 __le16 special; 335 } fields; 336 } upper; 337}; 338 339/* Statistics counters collected by the MAC */ 340struct e1000_hw_stats { 341 u64 crcerrs; 342 u64 algnerrc; 343 u64 symerrs; 344 u64 rxerrc; 345 u64 mpc; 346 u64 scc; 347 u64 ecol; 348 u64 mcc; 349 u64 latecol; 350 u64 colc; 351 u64 dc; 352 u64 tncrs; 353 u64 sec; 354 u64 cexterr; 355 u64 rlec; 356 u64 xonrxc; 357 u64 xontxc; 358 u64 xoffrxc; 359 u64 xofftxc; 360 u64 fcruc; 361 u64 prc64; 362 u64 prc127; 363 u64 prc255; 364 u64 prc511; 365 u64 prc1023; 366 u64 prc1522; 367 u64 gprc; 368 u64 bprc; 369 u64 mprc; 370 u64 gptc; 371 u64 gorc; 372 u64 gotc; 373 u64 rnbc; 374 u64 ruc; 375 u64 rfc; 376 u64 roc; 377 u64 rjc; 378 u64 mgprc; 379 u64 mgpdc; 380 u64 mgptc; 381 u64 tor; 382 u64 tot; 383 u64 tpr; 384 u64 tpt; 385 u64 ptc64; 386 u64 ptc127; 387 u64 ptc255; 388 u64 ptc511; 389 u64 ptc1023; 390 u64 ptc1522; 391 u64 mptc; 392 u64 bptc; 393 u64 tsctc; 394 u64 tsctfc; 395 u64 iac; 396 u64 icrxptc; 397 u64 icrxatc; 398 u64 ictxptc; 399 u64 ictxatc; 400 u64 ictxqec; 401 u64 ictxqmtc; 402 u64 icrxdmtc; 403 u64 icrxoc; 404}; 405 406struct e1000_phy_stats { 407 u32 idle_errors; 408 u32 receive_errors; 409}; 410 411struct e1000_host_mng_dhcp_cookie { 412 u32 signature; 413 u8 status; 414 u8 reserved0; 415 u16 vlan_id; 416 u32 reserved1; 417 u16 reserved2; 418 u8 reserved3; 419 u8 checksum; 420}; 421 422/* Host Interface "Rev 1" */ 423struct e1000_host_command_header { 424 u8 command_id; 425 u8 command_length; 426 u8 command_options; 427 u8 checksum; 428}; 429 430#define E1000_HI_MAX_DATA_LENGTH 252 431struct e1000_host_command_info { 432 struct e1000_host_command_header command_header; 433 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 434}; 435 436/* Host Interface "Rev 2" */ 437struct e1000_host_mng_command_header { 438 u8 command_id; 439 u8 checksum; 440 u16 reserved1; 441 u16 reserved2; 442 u16 command_length; 443}; 444 445#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 446struct e1000_host_mng_command_info { 447 struct e1000_host_mng_command_header command_header; 448 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 449}; 450 451#include "mac.h" 452#include "phy.h" 453#include "nvm.h" 454#include "manage.h" 455 456/* Function pointers for the MAC. */ 457struct e1000_mac_operations { 458 s32 (*id_led_init)(struct e1000_hw *); 459 s32 (*blink_led)(struct e1000_hw *); 460 bool (*check_mng_mode)(struct e1000_hw *); 461 s32 (*check_for_link)(struct e1000_hw *); 462 s32 (*cleanup_led)(struct e1000_hw *); 463 void (*clear_hw_cntrs)(struct e1000_hw *); 464 void (*clear_vfta)(struct e1000_hw *); 465 s32 (*get_bus_info)(struct e1000_hw *); 466 void (*set_lan_id)(struct e1000_hw *); 467 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 468 s32 (*led_on)(struct e1000_hw *); 469 s32 (*led_off)(struct e1000_hw *); 470 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 471 s32 (*reset_hw)(struct e1000_hw *); 472 s32 (*init_hw)(struct e1000_hw *); 473 s32 (*setup_link)(struct e1000_hw *); 474 s32 (*setup_physical_interface)(struct e1000_hw *); 475 s32 (*setup_led)(struct e1000_hw *); 476 void (*write_vfta)(struct e1000_hw *, u32, u32); 477 void (*config_collision_dist)(struct e1000_hw *); 478 int (*rar_set)(struct e1000_hw *, u8 *, u32); 479 s32 (*read_mac_addr)(struct e1000_hw *); 480 u32 (*rar_get_count)(struct e1000_hw *); 481}; 482 483/* When to use various PHY register access functions: 484 * 485 * Func Caller 486 * Function Does Does When to use 487 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 488 * X_reg L,P,A n/a for simple PHY reg accesses 489 * X_reg_locked P,A L for multiple accesses of different regs 490 * on different pages 491 * X_reg_page A L,P for multiple accesses of different regs 492 * on the same page 493 * 494 * Where X=[read|write], L=locking, P=sets page, A=register access 495 * 496 */ 497struct e1000_phy_operations { 498 s32 (*acquire)(struct e1000_hw *); 499 s32 (*cfg_on_link_up)(struct e1000_hw *); 500 s32 (*check_polarity)(struct e1000_hw *); 501 s32 (*check_reset_block)(struct e1000_hw *); 502 s32 (*commit)(struct e1000_hw *); 503 s32 (*force_speed_duplex)(struct e1000_hw *); 504 s32 (*get_cfg_done)(struct e1000_hw *hw); 505 s32 (*get_cable_length)(struct e1000_hw *); 506 s32 (*get_info)(struct e1000_hw *); 507 s32 (*set_page)(struct e1000_hw *, u16); 508 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 509 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 510 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 511 void (*release)(struct e1000_hw *); 512 s32 (*reset)(struct e1000_hw *); 513 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 514 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 515 s32 (*write_reg)(struct e1000_hw *, u32, u16); 516 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 517 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 518 void (*power_up)(struct e1000_hw *); 519 void (*power_down)(struct e1000_hw *); 520}; 521 522/* Function pointers for the NVM. */ 523struct e1000_nvm_operations { 524 s32 (*acquire)(struct e1000_hw *); 525 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 526 void (*release)(struct e1000_hw *); 527 void (*reload)(struct e1000_hw *); 528 s32 (*update)(struct e1000_hw *); 529 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 530 s32 (*validate)(struct e1000_hw *); 531 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 532}; 533 534struct e1000_mac_info { 535 struct e1000_mac_operations ops; 536 u8 addr[ETH_ALEN]; 537 u8 perm_addr[ETH_ALEN]; 538 539 enum e1000_mac_type type; 540 541 u32 collision_delta; 542 u32 ledctl_default; 543 u32 ledctl_mode1; 544 u32 ledctl_mode2; 545 u32 mc_filter_type; 546 u32 tx_packet_delta; 547 u32 txcw; 548 549 u16 current_ifs_val; 550 u16 ifs_max_val; 551 u16 ifs_min_val; 552 u16 ifs_ratio; 553 u16 ifs_step_size; 554 u16 mta_reg_count; 555 556 /* Maximum size of the MTA register table in all supported adapters */ 557#define MAX_MTA_REG 128 558 u32 mta_shadow[MAX_MTA_REG]; 559 u16 rar_entry_count; 560 561 u8 forced_speed_duplex; 562 563 bool adaptive_ifs; 564 bool has_fwsm; 565 bool arc_subsystem_valid; 566 bool autoneg; 567 bool autoneg_failed; 568 bool get_link_status; 569 bool in_ifs_mode; 570 bool serdes_has_link; 571 bool tx_pkt_filtering; 572 enum e1000_serdes_link_state serdes_link_state; 573}; 574 575struct e1000_phy_info { 576 struct e1000_phy_operations ops; 577 578 enum e1000_phy_type type; 579 580 enum e1000_1000t_rx_status local_rx; 581 enum e1000_1000t_rx_status remote_rx; 582 enum e1000_ms_type ms_type; 583 enum e1000_ms_type original_ms_type; 584 enum e1000_rev_polarity cable_polarity; 585 enum e1000_smart_speed smart_speed; 586 587 u32 addr; 588 u32 id; 589 u32 reset_delay_us; /* in usec */ 590 u32 revision; 591 592 enum e1000_media_type media_type; 593 594 u16 autoneg_advertised; 595 u16 autoneg_mask; 596 u16 cable_length; 597 u16 max_cable_length; 598 u16 min_cable_length; 599 600 u8 mdix; 601 602 bool disable_polarity_correction; 603 bool is_mdix; 604 bool polarity_correction; 605 bool speed_downgraded; 606 bool autoneg_wait_to_complete; 607}; 608 609struct e1000_nvm_info { 610 struct e1000_nvm_operations ops; 611 612 enum e1000_nvm_type type; 613 enum e1000_nvm_override override; 614 615 u32 flash_bank_size; 616 u32 flash_base_addr; 617 618 u16 word_size; 619 u16 delay_usec; 620 u16 address_bits; 621 u16 opcode_bits; 622 u16 page_size; 623}; 624 625struct e1000_bus_info { 626 enum e1000_bus_width width; 627 628 u16 func; 629}; 630 631struct e1000_fc_info { 632 u32 high_water; /* Flow control high-water mark */ 633 u32 low_water; /* Flow control low-water mark */ 634 u16 pause_time; /* Flow control pause timer */ 635 u16 refresh_time; /* Flow control refresh timer */ 636 bool send_xon; /* Flow control send XON */ 637 bool strict_ieee; /* Strict IEEE mode */ 638 enum e1000_fc_mode current_mode; /* FC mode in effect */ 639 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 640}; 641 642struct e1000_dev_spec_82571 { 643 bool laa_is_present; 644 u32 smb_counter; 645}; 646 647struct e1000_dev_spec_80003es2lan { 648 bool mdic_wa_enable; 649}; 650 651struct e1000_shadow_ram { 652 u16 value; 653 bool modified; 654}; 655 656#define E1000_ICH8_SHADOW_RAM_WORDS 2048 657 658/* I218 PHY Ultra Low Power (ULP) states */ 659enum e1000_ulp_state { 660 e1000_ulp_state_unknown, 661 e1000_ulp_state_off, 662 e1000_ulp_state_on, 663}; 664 665struct e1000_dev_spec_ich8lan { 666 bool kmrn_lock_loss_workaround_enabled; 667 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS]; 668 bool nvm_k1_enabled; 669 bool eee_disable; 670 u16 eee_lp_ability; 671 enum e1000_ulp_state ulp_state; 672}; 673 674struct e1000_hw { 675 struct e1000_adapter *adapter; 676 677 void __iomem *hw_addr; 678 void __iomem *flash_address; 679 680 struct e1000_mac_info mac; 681 struct e1000_fc_info fc; 682 struct e1000_phy_info phy; 683 struct e1000_nvm_info nvm; 684 struct e1000_bus_info bus; 685 struct e1000_host_mng_dhcp_cookie mng_cookie; 686 687 union { 688 struct e1000_dev_spec_82571 e82571; 689 struct e1000_dev_spec_80003es2lan e80003es2lan; 690 struct e1000_dev_spec_ich8lan ich8lan; 691 } dev_spec; 692}; 693 694#include "82571.h" 695#include "80003es2lan.h" 696#include "ich8lan.h" 697 698#endif 699