1/*******************************************************************************
2
3  Intel(R) 82576 Virtual Function Linux driver
4  Copyright(c) 2009 - 2012 Intel Corporation.
5
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  more details.
14
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, see <http://www.gnu.org/licenses/>.
17
18  The full GNU General Public License is included in this distribution in
19  the file called "COPYING".
20
21  Contact Information:
22  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25*******************************************************************************/
26
27#ifndef _E1000_VF_H_
28#define _E1000_VF_H_
29
30#include <linux/pci.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/if_ether.h>
34
35#include "regs.h"
36#include "defines.h"
37
38struct e1000_hw;
39
40#define E1000_DEV_ID_82576_VF		0x10CA
41#define E1000_DEV_ID_I350_VF		0x1520
42#define E1000_REVISION_0	0
43#define E1000_REVISION_1	1
44#define E1000_REVISION_2	2
45#define E1000_REVISION_3	3
46#define E1000_REVISION_4	4
47
48#define E1000_FUNC_0	0
49#define E1000_FUNC_1	1
50
51/* Receive Address Register Count
52 * Number of high/low register pairs in the RAR.  The RAR (Receive Address
53 * Registers) holds the directed and multicast addresses that we monitor.
54 * These entries are also used for MAC-based filtering.
55 */
56#define E1000_RAR_ENTRIES_VF	1
57
58/* Receive Descriptor - Advanced */
59union e1000_adv_rx_desc {
60	struct {
61		u64 pkt_addr; /* Packet buffer address */
62		u64 hdr_addr; /* Header buffer address */
63	} read;
64	struct {
65		struct {
66			union {
67				u32 data;
68				struct {
69					u16 pkt_info; /* RSS/Packet type */
70					/* Split Header, hdr buffer length */
71					u16 hdr_info;
72				} hs_rss;
73			} lo_dword;
74			union {
75				u32 rss; /* RSS Hash */
76				struct {
77					u16 ip_id; /* IP id */
78					u16 csum;  /* Packet Checksum */
79				} csum_ip;
80			} hi_dword;
81		} lower;
82		struct {
83			u32 status_error; /* ext status/error */
84			u16 length; /* Packet length */
85			u16 vlan;   /* VLAN tag */
86		} upper;
87	} wb;  /* writeback */
88};
89
90#define E1000_RXDADV_HDRBUFLEN_MASK	0x7FE0
91#define E1000_RXDADV_HDRBUFLEN_SHIFT	5
92
93/* Transmit Descriptor - Advanced */
94union e1000_adv_tx_desc {
95	struct {
96		u64 buffer_addr; /* Address of descriptor's data buf */
97		u32 cmd_type_len;
98		u32 olinfo_status;
99	} read;
100	struct {
101		u64 rsvd; /* Reserved */
102		u32 nxtseq_seed;
103		u32 status;
104	} wb;
105};
106
107/* Adv Transmit Descriptor Config Masks */
108#define E1000_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
109#define E1000_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
110#define E1000_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
111#define E1000_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
112#define E1000_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
113#define E1000_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
114#define E1000_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
115#define E1000_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
116#define E1000_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
117
118/* Context descriptors */
119struct e1000_adv_tx_context_desc {
120	u32 vlan_macip_lens;
121	u32 seqnum_seed;
122	u32 type_tucmd_mlhl;
123	u32 mss_l4len_idx;
124};
125
126#define E1000_ADVTXD_MACLEN_SHIFT	9  /* Adv ctxt desc mac len shift */
127#define E1000_ADVTXD_TUCMD_IPV4		0x00000400 /* IP Packet Type: 1=IPv4 */
128#define E1000_ADVTXD_TUCMD_L4T_TCP	0x00000800 /* L4 Packet TYPE of TCP */
129#define E1000_ADVTXD_L4LEN_SHIFT	8  /* Adv ctxt L4LEN shift */
130#define E1000_ADVTXD_MSS_SHIFT		16 /* Adv ctxt MSS shift */
131
132enum e1000_mac_type {
133	e1000_undefined = 0,
134	e1000_vfadapt,
135	e1000_vfadapt_i350,
136	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
137};
138
139struct e1000_vf_stats {
140	u64 base_gprc;
141	u64 base_gptc;
142	u64 base_gorc;
143	u64 base_gotc;
144	u64 base_mprc;
145	u64 base_gotlbc;
146	u64 base_gptlbc;
147	u64 base_gorlbc;
148	u64 base_gprlbc;
149
150	u32 last_gprc;
151	u32 last_gptc;
152	u32 last_gorc;
153	u32 last_gotc;
154	u32 last_mprc;
155	u32 last_gotlbc;
156	u32 last_gptlbc;
157	u32 last_gorlbc;
158	u32 last_gprlbc;
159
160	u64 gprc;
161	u64 gptc;
162	u64 gorc;
163	u64 gotc;
164	u64 mprc;
165	u64 gotlbc;
166	u64 gptlbc;
167	u64 gorlbc;
168	u64 gprlbc;
169};
170
171#include "mbx.h"
172
173struct e1000_mac_operations {
174	/* Function pointers for the MAC. */
175	s32  (*init_params)(struct e1000_hw *);
176	s32  (*check_for_link)(struct e1000_hw *);
177	void (*clear_vfta)(struct e1000_hw *);
178	s32  (*get_bus_info)(struct e1000_hw *);
179	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
180	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32);
181	s32  (*reset_hw)(struct e1000_hw *);
182	s32  (*init_hw)(struct e1000_hw *);
183	s32  (*setup_link)(struct e1000_hw *);
184	void (*write_vfta)(struct e1000_hw *, u32, u32);
185	void (*mta_set)(struct e1000_hw *, u32);
186	void (*rar_set)(struct e1000_hw *, u8*, u32);
187	s32  (*read_mac_addr)(struct e1000_hw *);
188	s32  (*set_vfta)(struct e1000_hw *, u16, bool);
189};
190
191struct e1000_mac_info {
192	struct e1000_mac_operations ops;
193	u8 addr[6];
194	u8 perm_addr[6];
195
196	enum e1000_mac_type type;
197
198	u16 mta_reg_count;
199	u16 rar_entry_count;
200
201	bool get_link_status;
202};
203
204struct e1000_mbx_operations {
205	s32 (*init_params)(struct e1000_hw *hw);
206	s32 (*read)(struct e1000_hw *, u32 *, u16);
207	s32 (*write)(struct e1000_hw *, u32 *, u16);
208	s32 (*read_posted)(struct e1000_hw *, u32 *, u16);
209	s32 (*write_posted)(struct e1000_hw *, u32 *, u16);
210	s32 (*check_for_msg)(struct e1000_hw *);
211	s32 (*check_for_ack)(struct e1000_hw *);
212	s32 (*check_for_rst)(struct e1000_hw *);
213};
214
215struct e1000_mbx_stats {
216	u32 msgs_tx;
217	u32 msgs_rx;
218
219	u32 acks;
220	u32 reqs;
221	u32 rsts;
222};
223
224struct e1000_mbx_info {
225	struct e1000_mbx_operations ops;
226	struct e1000_mbx_stats stats;
227	u32 timeout;
228	u32 usec_delay;
229	u16 size;
230};
231
232struct e1000_dev_spec_vf {
233	u32 vf_number;
234	u32 v2p_mailbox;
235};
236
237struct e1000_hw {
238	void *back;
239
240	u8 __iomem *hw_addr;
241	u8 __iomem *flash_address;
242	unsigned long io_base;
243
244	struct e1000_mac_info  mac;
245	struct e1000_mbx_info mbx;
246
247	union {
248		struct e1000_dev_spec_vf vf;
249	} dev_spec;
250
251	u16 device_id;
252	u16 subsystem_vendor_id;
253	u16 subsystem_device_id;
254	u16 vendor_id;
255
256	u8  revision_id;
257};
258
259/* These functions must be implemented by drivers */
260void e1000_rlpml_set_vf(struct e1000_hw *, u16);
261void e1000_init_function_pointers_vf(struct e1000_hw *hw);
262
263#endif /* _E1000_VF_H_ */
264