1/******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27*******************************************************************************/ 28 29#ifndef _IXGBE_H_ 30#define _IXGBE_H_ 31 32#include <linux/bitops.h> 33#include <linux/types.h> 34#include <linux/pci.h> 35#include <linux/netdevice.h> 36#include <linux/cpumask.h> 37#include <linux/aer.h> 38#include <linux/if_vlan.h> 39#include <linux/jiffies.h> 40 41#include <linux/timecounter.h> 42#include <linux/net_tstamp.h> 43#include <linux/ptp_clock_kernel.h> 44 45#include "ixgbe_type.h" 46#include "ixgbe_common.h" 47#include "ixgbe_dcb.h" 48#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) 49#define IXGBE_FCOE 50#include "ixgbe_fcoe.h" 51#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ 52#ifdef CONFIG_IXGBE_DCA 53#include <linux/dca.h> 54#endif 55 56#include <net/busy_poll.h> 57 58#ifdef CONFIG_NET_RX_BUSY_POLL 59#define BP_EXTENDED_STATS 60#endif 61/* common prefix used by pr_<> macros */ 62#undef pr_fmt 63#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 64 65/* TX/RX descriptor defines */ 66#define IXGBE_DEFAULT_TXD 512 67#define IXGBE_DEFAULT_TX_WORK 256 68#define IXGBE_MAX_TXD 4096 69#define IXGBE_MIN_TXD 64 70 71#if (PAGE_SIZE < 8192) 72#define IXGBE_DEFAULT_RXD 512 73#else 74#define IXGBE_DEFAULT_RXD 128 75#endif 76#define IXGBE_MAX_RXD 4096 77#define IXGBE_MIN_RXD 64 78 79#define IXGBE_ETH_P_LLDP 0x88CC 80 81/* flow control */ 82#define IXGBE_MIN_FCRTL 0x40 83#define IXGBE_MAX_FCRTL 0x7FF80 84#define IXGBE_MIN_FCRTH 0x600 85#define IXGBE_MAX_FCRTH 0x7FFF0 86#define IXGBE_DEFAULT_FCPAUSE 0xFFFF 87#define IXGBE_MIN_FCPAUSE 0 88#define IXGBE_MAX_FCPAUSE 0xFFFF 89 90/* Supported Rx Buffer Sizes */ 91#define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 92#define IXGBE_RXBUFFER_2K 2048 93#define IXGBE_RXBUFFER_3K 3072 94#define IXGBE_RXBUFFER_4K 4096 95#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 96 97/* 98 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 99 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 100 * this adds up to 448 bytes of extra data. 101 * 102 * Since netdev_alloc_skb now allocates a page fragment we can use a value 103 * of 256 and the resultant skb will have a truesize of 960 or less. 104 */ 105#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 106 107/* How many Rx Buffers do we bundle into one write to the hardware ? */ 108#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 109 110enum ixgbe_tx_flags { 111 /* cmd_type flags */ 112 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 113 IXGBE_TX_FLAGS_TSO = 0x02, 114 IXGBE_TX_FLAGS_TSTAMP = 0x04, 115 116 /* olinfo flags */ 117 IXGBE_TX_FLAGS_CC = 0x08, 118 IXGBE_TX_FLAGS_IPV4 = 0x10, 119 IXGBE_TX_FLAGS_CSUM = 0x20, 120 121 /* software defined flags */ 122 IXGBE_TX_FLAGS_SW_VLAN = 0x40, 123 IXGBE_TX_FLAGS_FCOE = 0x80, 124}; 125 126/* VLAN info */ 127#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 128#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 129#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 130#define IXGBE_TX_FLAGS_VLAN_SHIFT 16 131 132#define IXGBE_MAX_VF_MC_ENTRIES 30 133#define IXGBE_MAX_VF_FUNCTIONS 64 134#define IXGBE_MAX_VFTA_ENTRIES 128 135#define MAX_EMULATION_MAC_ADDRS 16 136#define IXGBE_MAX_PF_MACVLANS 15 137#define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 138#define IXGBE_82599_VF_DEVICE_ID 0x10ED 139#define IXGBE_X540_VF_DEVICE_ID 0x1515 140 141struct vf_data_storage { 142 unsigned char vf_mac_addresses[ETH_ALEN]; 143 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 144 u16 num_vf_mc_hashes; 145 u16 default_vf_vlan_id; 146 u16 vlans_enabled; 147 bool clear_to_send; 148 bool pf_set_mac; 149 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 150 u16 pf_qos; 151 u16 tx_rate; 152 u16 vlan_count; 153 u8 spoofchk_enabled; 154 bool rss_query_enabled; 155 unsigned int vf_api; 156}; 157 158struct vf_macvlans { 159 struct list_head l; 160 int vf; 161 bool free; 162 bool is_macvlan; 163 u8 vf_macvlan[ETH_ALEN]; 164}; 165 166#define IXGBE_MAX_TXD_PWR 14 167#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) 168 169/* Tx Descriptors needed, worst case */ 170#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 171#define DESC_NEEDED (MAX_SKB_FRAGS + 4) 172 173/* wrapper around a pointer to a socket buffer, 174 * so a DMA handle can be stored along with the buffer */ 175struct ixgbe_tx_buffer { 176 union ixgbe_adv_tx_desc *next_to_watch; 177 unsigned long time_stamp; 178 struct sk_buff *skb; 179 unsigned int bytecount; 180 unsigned short gso_segs; 181 __be16 protocol; 182 DEFINE_DMA_UNMAP_ADDR(dma); 183 DEFINE_DMA_UNMAP_LEN(len); 184 u32 tx_flags; 185}; 186 187struct ixgbe_rx_buffer { 188 struct sk_buff *skb; 189 dma_addr_t dma; 190 struct page *page; 191 unsigned int page_offset; 192}; 193 194struct ixgbe_queue_stats { 195 u64 packets; 196 u64 bytes; 197#ifdef BP_EXTENDED_STATS 198 u64 yields; 199 u64 misses; 200 u64 cleaned; 201#endif /* BP_EXTENDED_STATS */ 202}; 203 204struct ixgbe_tx_queue_stats { 205 u64 restart_queue; 206 u64 tx_busy; 207 u64 tx_done_old; 208}; 209 210struct ixgbe_rx_queue_stats { 211 u64 rsc_count; 212 u64 rsc_flush; 213 u64 non_eop_descs; 214 u64 alloc_rx_page_failed; 215 u64 alloc_rx_buff_failed; 216 u64 csum_err; 217}; 218 219enum ixgbe_ring_state_t { 220 __IXGBE_TX_FDIR_INIT_DONE, 221 __IXGBE_TX_XPS_INIT_DONE, 222 __IXGBE_TX_DETECT_HANG, 223 __IXGBE_HANG_CHECK_ARMED, 224 __IXGBE_RX_RSC_ENABLED, 225 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 226 __IXGBE_RX_FCOE, 227}; 228 229struct ixgbe_fwd_adapter { 230 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 231 struct net_device *netdev; 232 struct ixgbe_adapter *real_adapter; 233 unsigned int tx_base_queue; 234 unsigned int rx_base_queue; 235 int pool; 236}; 237 238#define check_for_tx_hang(ring) \ 239 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 240#define set_check_for_tx_hang(ring) \ 241 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 242#define clear_check_for_tx_hang(ring) \ 243 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 244#define ring_is_rsc_enabled(ring) \ 245 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 246#define set_ring_rsc_enabled(ring) \ 247 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 248#define clear_ring_rsc_enabled(ring) \ 249 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 250struct ixgbe_ring { 251 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 252 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 253 struct net_device *netdev; /* netdev ring belongs to */ 254 struct device *dev; /* device for DMA mapping */ 255 struct ixgbe_fwd_adapter *l2_accel_priv; 256 void *desc; /* descriptor ring memory */ 257 union { 258 struct ixgbe_tx_buffer *tx_buffer_info; 259 struct ixgbe_rx_buffer *rx_buffer_info; 260 }; 261 unsigned long state; 262 u8 __iomem *tail; 263 dma_addr_t dma; /* phys. address of descriptor ring */ 264 unsigned int size; /* length in bytes */ 265 266 u16 count; /* amount of descriptors */ 267 268 u8 queue_index; /* needed for multiqueue queue management */ 269 u8 reg_idx; /* holds the special value that gets 270 * the hardware register offset 271 * associated with this ring, which is 272 * different for DCB and RSS modes 273 */ 274 u16 next_to_use; 275 u16 next_to_clean; 276 277 union { 278 u16 next_to_alloc; 279 struct { 280 u8 atr_sample_rate; 281 u8 atr_count; 282 }; 283 }; 284 285 u8 dcb_tc; 286 struct ixgbe_queue_stats stats; 287 struct u64_stats_sync syncp; 288 union { 289 struct ixgbe_tx_queue_stats tx_stats; 290 struct ixgbe_rx_queue_stats rx_stats; 291 }; 292} ____cacheline_internodealigned_in_smp; 293 294enum ixgbe_ring_f_enum { 295 RING_F_NONE = 0, 296 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 297 RING_F_RSS, 298 RING_F_FDIR, 299#ifdef IXGBE_FCOE 300 RING_F_FCOE, 301#endif /* IXGBE_FCOE */ 302 303 RING_F_ARRAY_SIZE /* must be last in enum set */ 304}; 305 306#define IXGBE_MAX_RSS_INDICES 16 307#define IXGBE_MAX_RSS_INDICES_X550 64 308#define IXGBE_MAX_VMDQ_INDICES 64 309#define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 310#define IXGBE_MAX_FCOE_INDICES 8 311#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 312#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 313#define IXGBE_MAX_L2A_QUEUES 4 314#define IXGBE_BAD_L2A_QUEUE 3 315#define IXGBE_MAX_MACVLANS 31 316#define IXGBE_MAX_DCBMACVLANS 8 317 318struct ixgbe_ring_feature { 319 u16 limit; /* upper limit on feature indices */ 320 u16 indices; /* current value of indices */ 321 u16 mask; /* Mask used for feature to ring mapping */ 322 u16 offset; /* offset to start of feature */ 323} ____cacheline_internodealigned_in_smp; 324 325#define IXGBE_82599_VMDQ_8Q_MASK 0x78 326#define IXGBE_82599_VMDQ_4Q_MASK 0x7C 327#define IXGBE_82599_VMDQ_2Q_MASK 0x7E 328 329/* 330 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 331 * this is twice the size of a half page we need to double the page order 332 * for FCoE enabled Rx queues. 333 */ 334static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 335{ 336#ifdef IXGBE_FCOE 337 if (test_bit(__IXGBE_RX_FCOE, &ring->state)) 338 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K : 339 IXGBE_RXBUFFER_3K; 340#endif 341 return IXGBE_RXBUFFER_2K; 342} 343 344static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 345{ 346#ifdef IXGBE_FCOE 347 if (test_bit(__IXGBE_RX_FCOE, &ring->state)) 348 return (PAGE_SIZE < 8192) ? 1 : 0; 349#endif 350 return 0; 351} 352#define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 353 354struct ixgbe_ring_container { 355 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 356 unsigned int total_bytes; /* total bytes processed this int */ 357 unsigned int total_packets; /* total packets processed this int */ 358 u16 work_limit; /* total work allowed per interrupt */ 359 u8 count; /* total number of rings in vector */ 360 u8 itr; /* current ITR setting for ring */ 361}; 362 363/* iterator for handling rings in ring container */ 364#define ixgbe_for_each_ring(pos, head) \ 365 for (pos = (head).ring; pos != NULL; pos = pos->next) 366 367#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 368 ? 8 : 1) 369#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 370 371/* MAX_Q_VECTORS of these are allocated, 372 * but we only use one per queue-specific vector. 373 */ 374struct ixgbe_q_vector { 375 struct ixgbe_adapter *adapter; 376#ifdef CONFIG_IXGBE_DCA 377 int cpu; /* CPU for DCA */ 378#endif 379 u16 v_idx; /* index of q_vector within array, also used for 380 * finding the bit in EICR and friends that 381 * represents the vector for this ring */ 382 u16 itr; /* Interrupt throttle rate written to EITR */ 383 struct ixgbe_ring_container rx, tx; 384 385 struct napi_struct napi; 386 cpumask_t affinity_mask; 387 int numa_node; 388 struct rcu_head rcu; /* to avoid race with update stats on free */ 389 char name[IFNAMSIZ + 9]; 390 391#ifdef CONFIG_NET_RX_BUSY_POLL 392 atomic_t state; 393#endif /* CONFIG_NET_RX_BUSY_POLL */ 394 395 /* for dynamic allocation of rings associated with this q_vector */ 396 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; 397}; 398 399#ifdef CONFIG_NET_RX_BUSY_POLL 400enum ixgbe_qv_state_t { 401 IXGBE_QV_STATE_IDLE = 0, 402 IXGBE_QV_STATE_NAPI, 403 IXGBE_QV_STATE_POLL, 404 IXGBE_QV_STATE_DISABLE 405}; 406 407static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) 408{ 409 /* reset state to idle */ 410 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); 411} 412 413/* called from the device poll routine to get ownership of a q_vector */ 414static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) 415{ 416 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, 417 IXGBE_QV_STATE_NAPI); 418#ifdef BP_EXTENDED_STATS 419 if (rc != IXGBE_QV_STATE_IDLE) 420 q_vector->tx.ring->stats.yields++; 421#endif 422 423 return rc == IXGBE_QV_STATE_IDLE; 424} 425 426/* returns true is someone tried to get the qv while napi had it */ 427static inline void ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) 428{ 429 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_NAPI); 430 431 /* flush any outstanding Rx frames */ 432 if (q_vector->napi.gro_list) 433 napi_gro_flush(&q_vector->napi, false); 434 435 /* reset state to idle */ 436 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); 437} 438 439/* called from ixgbe_low_latency_poll() */ 440static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) 441{ 442 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, 443 IXGBE_QV_STATE_POLL); 444#ifdef BP_EXTENDED_STATS 445 if (rc != IXGBE_QV_STATE_IDLE) 446 q_vector->tx.ring->stats.yields++; 447#endif 448 return rc == IXGBE_QV_STATE_IDLE; 449} 450 451/* returns true if someone tried to get the qv while it was locked */ 452static inline void ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) 453{ 454 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_POLL); 455 456 /* reset state to idle */ 457 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); 458} 459 460/* true if a socket is polling, even if it did not get the lock */ 461static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) 462{ 463 return atomic_read(&q_vector->state) == IXGBE_QV_STATE_POLL; 464} 465 466/* false if QV is currently owned */ 467static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) 468{ 469 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, 470 IXGBE_QV_STATE_DISABLE); 471 472 return rc == IXGBE_QV_STATE_IDLE; 473} 474 475#else /* CONFIG_NET_RX_BUSY_POLL */ 476static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) 477{ 478} 479 480static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) 481{ 482 return true; 483} 484 485static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) 486{ 487 return false; 488} 489 490static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) 491{ 492 return false; 493} 494 495static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) 496{ 497 return false; 498} 499 500static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) 501{ 502 return false; 503} 504 505static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) 506{ 507 return true; 508} 509 510#endif /* CONFIG_NET_RX_BUSY_POLL */ 511 512#ifdef CONFIG_IXGBE_HWMON 513 514#define IXGBE_HWMON_TYPE_LOC 0 515#define IXGBE_HWMON_TYPE_TEMP 1 516#define IXGBE_HWMON_TYPE_CAUTION 2 517#define IXGBE_HWMON_TYPE_MAX 3 518 519struct hwmon_attr { 520 struct device_attribute dev_attr; 521 struct ixgbe_hw *hw; 522 struct ixgbe_thermal_diode_data *sensor; 523 char name[12]; 524}; 525 526struct hwmon_buff { 527 struct attribute_group group; 528 const struct attribute_group *groups[2]; 529 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; 530 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; 531 unsigned int n_hwmon; 532}; 533#endif /* CONFIG_IXGBE_HWMON */ 534 535/* 536 * microsecond values for various ITR rates shifted by 2 to fit itr register 537 * with the first 3 bits reserved 0 538 */ 539#define IXGBE_MIN_RSC_ITR 24 540#define IXGBE_100K_ITR 40 541#define IXGBE_20K_ITR 200 542#define IXGBE_10K_ITR 400 543#define IXGBE_8K_ITR 500 544 545/* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 546static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 547 const u32 stat_err_bits) 548{ 549 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 550} 551 552static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 553{ 554 u16 ntc = ring->next_to_clean; 555 u16 ntu = ring->next_to_use; 556 557 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 558} 559 560#define IXGBE_RX_DESC(R, i) \ 561 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 562#define IXGBE_TX_DESC(R, i) \ 563 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 564#define IXGBE_TX_CTXTDESC(R, i) \ 565 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 566 567#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 568#ifdef IXGBE_FCOE 569/* Use 3K as the baby jumbo frame size for FCoE */ 570#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 571#endif /* IXGBE_FCOE */ 572 573#define OTHER_VECTOR 1 574#define NON_Q_VECTORS (OTHER_VECTOR) 575 576#define MAX_MSIX_VECTORS_82599 64 577#define MAX_Q_VECTORS_82599 64 578#define MAX_MSIX_VECTORS_82598 18 579#define MAX_Q_VECTORS_82598 16 580 581struct ixgbe_mac_addr { 582 u8 addr[ETH_ALEN]; 583 u16 queue; 584 u16 state; /* bitmask */ 585}; 586#define IXGBE_MAC_STATE_DEFAULT 0x1 587#define IXGBE_MAC_STATE_MODIFIED 0x2 588#define IXGBE_MAC_STATE_IN_USE 0x4 589 590#define MAX_Q_VECTORS MAX_Q_VECTORS_82599 591#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 592 593#define MIN_MSIX_Q_VECTORS 1 594#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 595 596/* default to trying for four seconds */ 597#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 598 599/* board specific private data structure */ 600struct ixgbe_adapter { 601 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 602 /* OS defined structs */ 603 struct net_device *netdev; 604 struct pci_dev *pdev; 605 606 unsigned long state; 607 608 /* Some features need tri-state capability, 609 * thus the additional *_CAPABLE flags. 610 */ 611 u32 flags; 612#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) 613#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3) 614#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4) 615#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5) 616#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6) 617#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) 618#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9) 619#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10) 620#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11) 621#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12) 622#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13) 623#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14) 624#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15) 625#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16) 626#define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17) 627#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18) 628#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19) 629#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20) 630#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21) 631#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22) 632#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23) 633 634 u32 flags2; 635#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0) 636#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) 637#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) 638#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) 639#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) 640#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) 641#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) 642#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) 643#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) 644#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) 645#define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10) 646 647 /* Tx fast path data */ 648 int num_tx_queues; 649 u16 tx_itr_setting; 650 u16 tx_work_limit; 651 652 /* Rx fast path data */ 653 int num_rx_queues; 654 u16 rx_itr_setting; 655 656 /* TX */ 657 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 658 659 u64 restart_queue; 660 u64 lsc_int; 661 u32 tx_timeout_count; 662 663 /* RX */ 664 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 665 int num_rx_pools; /* == num_rx_queues in 82598 */ 666 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 667 u64 hw_csum_rx_error; 668 u64 hw_rx_no_dma_resources; 669 u64 rsc_total_count; 670 u64 rsc_total_flush; 671 u64 non_eop_descs; 672 u32 alloc_rx_page_failed; 673 u32 alloc_rx_buff_failed; 674 675 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 676 677 /* DCB parameters */ 678 struct ieee_pfc *ixgbe_ieee_pfc; 679 struct ieee_ets *ixgbe_ieee_ets; 680 struct ixgbe_dcb_config dcb_cfg; 681 struct ixgbe_dcb_config temp_dcb_cfg; 682 u8 dcb_set_bitmap; 683 u8 dcbx_cap; 684 enum ixgbe_fc_mode last_lfc_mode; 685 686 int num_q_vectors; /* current number of q_vectors for device */ 687 int max_q_vectors; /* true count of q_vectors for device */ 688 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 689 struct msix_entry *msix_entries; 690 691 u32 test_icr; 692 struct ixgbe_ring test_tx_ring; 693 struct ixgbe_ring test_rx_ring; 694 695 /* structs defined in ixgbe_hw.h */ 696 struct ixgbe_hw hw; 697 u16 msg_enable; 698 struct ixgbe_hw_stats stats; 699 700 u64 tx_busy; 701 unsigned int tx_ring_count; 702 unsigned int rx_ring_count; 703 704 u32 link_speed; 705 bool link_up; 706 unsigned long link_check_timeout; 707 708 struct timer_list service_timer; 709 struct work_struct service_task; 710 711 struct hlist_head fdir_filter_list; 712 unsigned long fdir_overflow; /* number of times ATR was backed off */ 713 union ixgbe_atr_input fdir_mask; 714 int fdir_filter_count; 715 u32 fdir_pballoc; 716 u32 atr_sample_rate; 717 spinlock_t fdir_perfect_lock; 718 719#ifdef IXGBE_FCOE 720 struct ixgbe_fcoe fcoe; 721#endif /* IXGBE_FCOE */ 722 u8 __iomem *io_addr; /* Mainly for iounmap use */ 723 u32 wol; 724 725 u16 bridge_mode; 726 727 u16 eeprom_verh; 728 u16 eeprom_verl; 729 u16 eeprom_cap; 730 731 u32 interrupt_event; 732 u32 led_reg; 733 734 struct ptp_clock *ptp_clock; 735 struct ptp_clock_info ptp_caps; 736 struct work_struct ptp_tx_work; 737 struct sk_buff *ptp_tx_skb; 738 struct hwtstamp_config tstamp_config; 739 unsigned long ptp_tx_start; 740 unsigned long last_overflow_check; 741 unsigned long last_rx_ptp_check; 742 unsigned long last_rx_timestamp; 743 spinlock_t tmreg_lock; 744 struct cyclecounter cc; 745 struct timecounter tc; 746 u32 base_incval; 747 748 /* SR-IOV */ 749 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 750 unsigned int num_vfs; 751 struct vf_data_storage *vfinfo; 752 int vf_rate_link_speed; 753 struct vf_macvlans vf_mvs; 754 struct vf_macvlans *mv_list; 755 756 u32 timer_event_accumulator; 757 u32 vferr_refcount; 758 struct ixgbe_mac_addr *mac_table; 759 u16 vxlan_port; 760 struct kobject *info_kobj; 761#ifdef CONFIG_IXGBE_HWMON 762 struct hwmon_buff *ixgbe_hwmon_buff; 763#endif /* CONFIG_IXGBE_HWMON */ 764#ifdef CONFIG_DEBUG_FS 765 struct dentry *ixgbe_dbg_adapter; 766#endif /*CONFIG_DEBUG_FS*/ 767 768 u8 default_up; 769 unsigned long fwd_bitmask; /* Bitmask indicating in use pools */ 770 771/* maximum number of RETA entries among all devices supported by ixgbe 772 * driver: currently it's x550 device in non-SRIOV mode 773 */ 774#define IXGBE_MAX_RETA_ENTRIES 512 775 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES]; 776 777#define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ 778 u32 rss_key[IXGBE_RSS_KEY_SIZE / sizeof(u32)]; 779}; 780 781static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) 782{ 783 switch (adapter->hw.mac.type) { 784 case ixgbe_mac_82598EB: 785 case ixgbe_mac_82599EB: 786 case ixgbe_mac_X540: 787 return IXGBE_MAX_RSS_INDICES; 788 case ixgbe_mac_X550: 789 case ixgbe_mac_X550EM_x: 790 return IXGBE_MAX_RSS_INDICES_X550; 791 default: 792 return 0; 793 } 794} 795 796struct ixgbe_fdir_filter { 797 struct hlist_node fdir_node; 798 union ixgbe_atr_input filter; 799 u16 sw_idx; 800 u16 action; 801}; 802 803enum ixgbe_state_t { 804 __IXGBE_TESTING, 805 __IXGBE_RESETTING, 806 __IXGBE_DOWN, 807 __IXGBE_DISABLED, 808 __IXGBE_REMOVING, 809 __IXGBE_SERVICE_SCHED, 810 __IXGBE_SERVICE_INITED, 811 __IXGBE_IN_SFP_INIT, 812 __IXGBE_PTP_RUNNING, 813 __IXGBE_PTP_TX_IN_PROGRESS, 814}; 815 816struct ixgbe_cb { 817 union { /* Union defining head/tail partner */ 818 struct sk_buff *head; 819 struct sk_buff *tail; 820 }; 821 dma_addr_t dma; 822 u16 append_cnt; 823 bool page_released; 824}; 825#define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 826 827enum ixgbe_boards { 828 board_82598, 829 board_82599, 830 board_X540, 831 board_X550, 832 board_X550EM_x, 833}; 834 835extern struct ixgbe_info ixgbe_82598_info; 836extern struct ixgbe_info ixgbe_82599_info; 837extern struct ixgbe_info ixgbe_X540_info; 838extern struct ixgbe_info ixgbe_X550_info; 839extern struct ixgbe_info ixgbe_X550EM_x_info; 840#ifdef CONFIG_IXGBE_DCB 841extern const struct dcbnl_rtnl_ops dcbnl_ops; 842#endif 843 844extern char ixgbe_driver_name[]; 845extern const char ixgbe_driver_version[]; 846#ifdef IXGBE_FCOE 847extern char ixgbe_default_device_descr[]; 848#endif /* IXGBE_FCOE */ 849 850void ixgbe_up(struct ixgbe_adapter *adapter); 851void ixgbe_down(struct ixgbe_adapter *adapter); 852void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 853void ixgbe_reset(struct ixgbe_adapter *adapter); 854void ixgbe_set_ethtool_ops(struct net_device *netdev); 855int ixgbe_setup_rx_resources(struct ixgbe_ring *); 856int ixgbe_setup_tx_resources(struct ixgbe_ring *); 857void ixgbe_free_rx_resources(struct ixgbe_ring *); 858void ixgbe_free_tx_resources(struct ixgbe_ring *); 859void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 860void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 861void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); 862void ixgbe_update_stats(struct ixgbe_adapter *adapter); 863int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 864int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 865 u16 subdevice_id); 866#ifdef CONFIG_PCI_IOV 867void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); 868#endif 869int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 870 u8 *addr, u16 queue); 871int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 872 u8 *addr, u16 queue); 873void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 874netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, 875 struct ixgbe_ring *); 876void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 877 struct ixgbe_tx_buffer *); 878void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 879void ixgbe_write_eitr(struct ixgbe_q_vector *); 880int ixgbe_poll(struct napi_struct *napi, int budget); 881int ethtool_ioctl(struct ifreq *ifr); 882s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 883s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 884s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 885s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 886 union ixgbe_atr_hash_dword input, 887 union ixgbe_atr_hash_dword common, 888 u8 queue); 889s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 890 union ixgbe_atr_input *input_mask); 891s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 892 union ixgbe_atr_input *input, 893 u16 soft_id, u8 queue); 894s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 895 union ixgbe_atr_input *input, 896 u16 soft_id); 897void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 898 union ixgbe_atr_input *mask); 899void ixgbe_set_rx_mode(struct net_device *netdev); 900#ifdef CONFIG_IXGBE_DCB 901void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 902#endif 903int ixgbe_setup_tc(struct net_device *dev, u8 tc); 904void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 905void ixgbe_do_reset(struct net_device *netdev); 906#ifdef CONFIG_IXGBE_HWMON 907void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 908int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 909#endif /* CONFIG_IXGBE_HWMON */ 910#ifdef IXGBE_FCOE 911void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 912int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 913 u8 *hdr_len); 914int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 915 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); 916int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 917 struct scatterlist *sgl, unsigned int sgc); 918int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 919 struct scatterlist *sgl, unsigned int sgc); 920int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 921int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 922void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 923int ixgbe_fcoe_enable(struct net_device *netdev); 924int ixgbe_fcoe_disable(struct net_device *netdev); 925#ifdef CONFIG_IXGBE_DCB 926u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 927u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 928#endif /* CONFIG_IXGBE_DCB */ 929int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 930int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 931 struct netdev_fcoe_hbainfo *info); 932u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 933#endif /* IXGBE_FCOE */ 934#ifdef CONFIG_DEBUG_FS 935void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 936void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 937void ixgbe_dbg_init(void); 938void ixgbe_dbg_exit(void); 939#else 940static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} 941static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} 942static inline void ixgbe_dbg_init(void) {} 943static inline void ixgbe_dbg_exit(void) {} 944#endif /* CONFIG_DEBUG_FS */ 945static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 946{ 947 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 948} 949 950void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 951void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); 952void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 953void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 954void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 955void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb); 956int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 957int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 958void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 959void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 960void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr); 961#ifdef CONFIG_PCI_IOV 962void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 963#endif 964 965netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 966 struct ixgbe_adapter *adapter, 967 struct ixgbe_ring *tx_ring); 968u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter); 969#endif /* _IXGBE_H_ */ 970